Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1 (Results 1 – 1 of 1) sorted by relevance
| /f-stack/freebsd/arm64/nvidia/tegra210/ |
| H A D | tegra210_xusbpadctl.c | 214 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 macro
583 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
585 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
606 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
610 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
612 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
614 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
616 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
618 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
664 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
[all …]
|