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Searched refs:TEGRA210_CLK_PLL_P (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra210-car.h274 #define TEGRA210_CLK_PLL_P 243 macro
/f-stack/freebsd/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt350 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
351 <&tegra_car TEGRA210_CLK_PLL_P>,
352 <&tegra_car TEGRA210_CLK_PLL_P>;
/f-stack/freebsd/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210.dtsi163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 <&tegra_car TEGRA210_CLK_PLL_P>;
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c361 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),