Searched refs:TEGRA210_CLK_PLL_A_OUT0 (Results 1 – 4 of 4) sorted by relevance
80 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;117 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;128 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
77 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
95 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
280 #define TEGRA210_CLK_PLL_A_OUT0 249 macro