| /f-stack/freebsd/contrib/device-tree/Bindings/reset/ |
| H A D | amlogic,meson-reset.yaml | 8 title: Amlogic Meson SoC Reset Controller
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
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| H A D | nxp,lpc1850-rgu.txt | 1 NXP LPC1850 Reset Generation Unit (RGU)
18 Reset Peripheral
64 Reset provider example:
73 Reset consumer example:
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| H A D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
24 Reset outputs:
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| H A D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
12 A SysCon Reset Controller node defines a device that uses a syscon node
16 SysCon Reset Controller Node
49 SysCon Reset Consumer Nodes
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| H A D | renesas,rst.yaml | 7 title: Renesas R-Car and RZ/G Reset Controller
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
18 - Reset control of peripheral devices (on R-Car Gen1),
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| H A D | reset.txt | 1 = Reset Signal Device Tree Bindings =
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
32 = Reset providers =
45 = Reset consumers =
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| H A D | ti,sci-reset.txt | 1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
12 TI-SCI Reset Controller Node
24 TI-SCI Reset Consumer Nodes
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| H A D | intel,rcu-gw.yaml | 7 title: System Reset Controller on Intel Gateway SoCs
19 description: Reset controller registers.
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| H A D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Peripheral Reset Controller
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| H A D | st,stm32mp1-rcc.txt | 1 STMicroelectronics STM32MP1 Peripheral Reset Controller
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| /f-stack/freebsd/contrib/device-tree/Bindings/watchdog/ |
| H A D | aspeed-wdt.txt | 16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
26 Reset types:
28 - cpu: Reset CPU on watchdog timeout
30 - soc: Reset 'System on Chip' on watchdog timeout
32 - system: Reset system on watchdog timeout
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| /f-stack/app/micro_thread/ |
| H A D | mt_connection.cpp | 60 void IMtConnection::Reset() in Reset() function in IMtConnection
200 void UdpShortConn::Reset() in Reset() function in UdpShortConn
203 this->IMtConnection::Reset(); in Reset()
387 void TcpKeepConn::Reset() in Reset() function in TcpKeepConn
391 this->IMtConnection::Reset(); in Reset()
396 this->IMtConnection::Reset(); in ConnReuseClean()
585 conn->Reset(); in FreeTcpKeepConn()
593 conn->Reset(); in FreeTcpKeepConn()
751 conn->Reset(); in FreeConnection()
760 conn->Reset(); in FreeConnection()
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| H A D | mt_connection.h | 53 virtual void Reset();
115 virtual void Reset();
174 virtual void Reset();
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| H A D | mt_net.cpp | 46 net_handler->Reset(); in ~CNetHelper()
179 void CNetHandler::Reset() in Reset() function in CNetHandler
210 this->Reset(); in CNetHandler()
215 this->Reset(); in ~CNetHandler()
751 void CSockLink::Reset() in Reset() function in CSockLink
774 this->KqueuerObj::Reset(); in Reset()
796 this->Reset(); in ~CSockLink()
1469 void CDestLinks::Reset() in Reset() function in CDestLinks
1497 this->Reset(); in ~CDestLinks()
1522 sock->Reset(); in FreeSockLink()
[all …]
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| H A D | mt_mbuf_pool.h | 81 void Reset() { in Reset() function
165 ptr->Reset(); in FreeMsgBuf()
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| H A D | mt_action.cpp | 43 void IMtAction::Reset() in Reset() function in IMtAction
215 Reset(); in ~IMtAction()
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | nvidia,tegra210-car.txt | 1 NVIDIA Tegra210 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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| H A D | nvidia,tegra30-car.txt | 1 NVIDIA Tegra30 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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| H A D | nvidia,tegra20-car.txt | 1 NVIDIA Tegra20 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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| H A D | nvidia,tegra114-car.txt | 1 NVIDIA Tegra114 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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| H A D | renesas,cpg-mssr.yaml | 7 title: Renesas Clock Pulse Generator / Module Standby and Software Reset
14 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
22 2. Reset Control, to perform a software reset of individual SoC devices.
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| /f-stack/freebsd/contrib/device-tree/Bindings/display/ |
| H A D | allwinner,sun4i-a10-tcon.yaml | 85 - description: TCON Reset Line
88 - description: TCON Reset Line
89 - description: TCON LVDS Reset Line
92 - description: TCON Reset Line
93 - description: TCON eDP Reset Line
96 - description: TCON Reset Line
97 - description: TCON eDP Reset Line
98 - description: TCON LVDS Reset Line
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| /f-stack/freebsd/contrib/device-tree/Bindings/mfd/ |
| H A D | altera-a10sr.txt | 20 a10sr_rst Reset Controller
30 Arria10 Peripheral PHY Reset
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/nfc/ |
| H A D | nfcmrvl.txt | 57 /* Reset IO */
81 /* Reset IO */
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| /f-stack/freebsd/contrib/device-tree/Bindings/power/reset/ |
| H A D | brcm,bcm21664-resetmgr.txt | 1 Broadcom Kona Family Reset Manager
|