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Searched refs:READ4 (Results 1 – 25 of 43) sorted by relevance

12

/f-stack/freebsd/arm/altera/socfpga/
H A Dsocfpga_a10_manager.c156 reg = READ4(sc, IMGCFG_STAT); in fpga_open()
163 reg = READ4(sc, IMGCFG_STAT); in fpga_open()
176 reg = READ4(sc, IMGCFG_CTRL_02); in fpga_open()
180 reg = READ4(sc, IMGCFG_CTRL_02); in fpga_open()
185 reg = READ4(sc, IMGCFG_CTRL_01); in fpga_open()
189 reg = READ4(sc, IMGCFG_CTRL_00); in fpga_open()
194 reg = READ4(sc, IMGCFG_CTRL_01); in fpga_open()
199 reg = READ4(sc, IMGCFG_CTRL_02); in fpga_open()
232 reg = READ4(sc, IMGCFG_STAT); in fpga_open()
264 reg = READ4(sc, IMGCFG_STAT); in fpga_close()
[all …]
H A Dsocfpga_manager.c167 reg = READ4(sc, FPGAMGR_STAT); in fpgamgr_state_get()
205 msel = READ4(sc, FPGAMGR_STAT); in fpga_open()
221 reg = READ4(sc, FPGAMGR_CTRL); in fpga_open()
230 reg = READ4(sc, FPGAMGR_CTRL); in fpga_open()
235 reg = READ4(sc, FPGAMGR_CTRL); in fpga_open()
246 reg = READ4(sc, FPGAMGR_CTRL); in fpga_open()
259 reg = READ4(sc, FPGAMGR_CTRL); in fpga_open()
272 if (READ4(sc, FPGAMGR_DCLKSTAT) != 0) in fpga_wait_dclk_pulses()
304 reg = READ4(sc, GPIO_EXT_PORTA); in fpga_close()
311 reg = READ4(sc, FPGAMGR_CTRL); in fpga_close()
[all …]
/f-stack/freebsd/arm/freescale/imx/
H A Dimx_gpt.c56 #define READ4(_sc, _r) \ macro
59 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
61 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
217 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) in imx_gpt_attach()
239 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); in imx_gpt_attach()
258 t1 = READ4(sc, IMX_GPT_CNT); in imx_gpt_attach()
260 t2 = READ4(sc, IMX_GPT_CNT); in imx_gpt_attach()
347 status = READ4(sc, IMX_GPT_SR); in imx_gpt_intr()
382 return (READ4(sc, IMX_GPT_CNT)); in imx_gpt_get_timecount()
418 curcnt = startcnt = READ4(sc, IMX_GPT_CNT); in imx_gpt_do_delay()
[all …]
H A Dimx_gpio.c76 #define READ4(_sc, _r) \ macro
79 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
81 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
382 wrk = READ4(sc, reg); in gpio_pic_setup_intr()
472 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); in gpio_pic_filter()
551 pad = READ4(sc, IMX_GPIO_PSR_REG); in imx51_gpio_pin_configure()
553 pad = READ4(sc, IMX_GPIO_DR_REG); in imx51_gpio_pin_configure()
694 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; in imx51_gpio_pin_get()
711 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); in imx51_gpio_pin_toggle()
729 *orig_pins = READ4(sc, IMX_GPIO_DR_REG); in imx51_gpio_pin_access_32()
[all …]
H A Dimx6_sdma.c65 #define READ4(_sc, _reg) \ macro
97 pending = READ4(sc, SDMAARM_INTR); in sdma_intr()
217 reg = READ4(sc, SDMAARM_EVTOVR); in sdma_overrides()
225 reg = READ4(sc, SDMAARM_HOSTOVR); in sdma_overrides()
233 reg = READ4(sc, SDMAARM_DSPOVR); in sdma_overrides()
336 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { in sdma_configure()
445 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { in boot_firmware()
/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_anadig.c137 reg = READ4(sc, pll_ctrl); in enable_pll()
146 while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED)) in enable_pll()
149 reg = READ4(sc, pll_ctrl); in enable_pll()
168 reg = READ4(sc, ANADIG_PLL4_CTRL); in pll4_configure_output()
209 reg = READ4(sc, ANADIG_REG_3P0); in anadig_attach()
214 reg = READ4(sc, USB_MISC(0)); in anadig_attach()
218 reg = READ4(sc, USB_MISC(1)); in anadig_attach()
224 READ4(sc, USB_ANALOG_USB_MISC(0))); in anadig_attach()
226 READ4(sc, USB_ANALOG_USB_MISC(1))); in anadig_attach()
H A Dvf_spi.c163 reg = READ4(sc, SPI_MCR); in spi_attach()
171 reg = READ4(sc, SPI_RSER); in spi_attach()
175 reg = READ4(sc, SPI_MCR); in spi_attach()
179 reg = READ4(sc, SPI_CTAR0); in spi_attach()
197 reg = READ4(sc, SPI_CTAR0); in spi_attach()
231 while((READ4(sc, SPI_SR) & SR_EOQF) == 0) in spi_txrx()
234 reg = READ4(sc, SPI_SR); in spi_txrx()
240 while((READ4(sc, SPI_SR) & SR_RFDF) == 0) in spi_txrx()
H A Dvf_adc.c161 return (READ4(sc, ADC_R0)); in adc_read()
174 reg = READ4(sc, ADC_HC0); in adc_enable()
211 reg = READ4(sc, ADC_CFG); in adc_attach()
217 reg = READ4(sc, ADC_GC); in adc_attach()
222 reg = READ4(sc, ADC_HC0); in adc_attach()
H A Dvf_edma.c103 interrupts = READ4(sc, DMA_INT); in edma_transfer_complete_intr()
126 reg = READ4(sc, DMA_ERR); in edma_err_intr()
130 reg, READ4(sc, DMA_ES)); in edma_err_intr()
199 reg = READ4(sc, DMA_ERQ); in dma_stop()
246 reg = READ4(sc, DMA_ERQ); in dma_setup()
251 reg = READ4(sc, DMA_EEI); in dma_setup()
H A Dvf_sai.c359 reg = READ4(sc, I2S_TCR2); in sai_configure_clock()
613 READ4(sc, I2S_TCSR)); in sai_intr()
625 reg = READ4(sc, I2S_TCSR); in setup_sai()
629 reg = READ4(sc, I2S_TCR3); in setup_sai()
636 reg = READ4(sc, I2S_TCR2); in setup_sai()
644 reg = READ4(sc, I2S_TCR3); in setup_sai()
649 reg = READ4(sc, I2S_TCR4); in setup_sai()
657 reg = READ4(sc, I2S_TCR5); in setup_sai()
667 reg = READ4(sc, I2S_TCSR); in setup_sai()
H A Dvf_ccm.c380 reg = READ4(sc, clk->sel_reg); in set_clock()
386 reg = READ4(sc, clk->reg); in set_clock()
462 reg = READ4(sc, CCM_CCR); in ccm_attach()
468 if (READ4(sc, CCM_CSR) & FXOSC_RDY) { in ccm_attach()
/f-stack/freebsd/arm64/rockchip/clk/
H A Drk_clk_pll.c60 #define READ4(_clk, off, val) \ macro
133 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_init()
172 READ4(clk, sc->base_offset, &raw0); in rk3066_clk_pll_recalc()
173 READ4(clk, sc->base_offset + 4, &raw1); in rk3066_clk_pll_recalc()
174 READ4(clk, sc->base_offset + 8, &raw2); in rk3066_clk_pll_recalc()
175 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_recalc()
255 READ4(clk, sc->base_offset + 4, &reg); in rk3066_clk_pll_set_freq()
398 READ4(clk, sc->base_offset, &raw1); in rk3328_clk_pll_recalc()
399 READ4(clk, sc->base_offset + 4, &raw2); in rk3328_clk_pll_recalc()
400 READ4(clk, sc->base_offset + 8, &raw3); in rk3328_clk_pll_recalc()
[all …]
/f-stack/freebsd/arm64/freescale/imx/clk/
H A Dimx_clk_frac_pll.c49 #define READ4(_clk, off, val) \ macro
95 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
105 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
127 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_recalc()
128 READ4(clk, sc->offset + CFG1, &cfg1); in imx_clk_frac_pll_recalc()
H A Dimx_clk_sscg_pll.c49 #define READ4(_clk, off, val) \ macro
107 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
117 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
139 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_recalc()
140 READ4(clk, sc->offset + CFG2, &cfg2); in imx_clk_sscg_pll_recalc()
H A Dimx_clk_composite.c63 #define READ4(_clk, off, val) \ macro
88 READ4(clk, sc->offset, &val); in imx_clk_composite_init()
107 READ4(clk, sc->offset, &val); in imx_clk_composite_set_gate()
128 READ4(clk, sc->offset, &val); in imx_clk_composite_set_mux()
146 READ4(clk, sc->offset, &reg); in imx_clk_composite_recalc()
265 READ4(clk, sc->offset, &val); in imx_clk_composite_set_freq()
/f-stack/freebsd/arm/ti/clk/
H A Dti_clk_clkctrl.c77 #define READ4(_clk, off, val) \ macro
105 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gdbclk_gate()
123 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gdbclk_gate()
155 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gate()
163 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gate()
H A Dti_clk_dpll.c69 #define READ4(_clk, off, val) \ macro
224 READ4(clk, sc->ti_idlest_offset, &val); in ti_dpll_clk_set_freq()
233 READ4(clk, sc->ti_clksel_offset, &val); in ti_dpll_clk_set_freq()
257 READ4(clk, sc->ti_idlest_offset, &val); in ti_dpll_clk_set_freq()
280 READ4(clk, sc->ti_clksel_offset, &val); in ti_dpll_clk_recalc()
/f-stack/freebsd/arm/allwinner/clkng/
H A Daw_clk_m.c66 #define READ4(_clk, off, val) \ macro
84 READ4(clk, sc->offset, &val); in aw_clk_m_init()
106 READ4(clk, sc->offset, &val); in aw_clk_m_set_gate()
129 READ4(clk, sc->offset, &val); in aw_clk_m_set_mux()
213 READ4(clk, sc->offset, &val); in aw_clk_m_set_freq()
237 READ4(clk, sc->offset, &val); in aw_clk_m_recalc()
H A Daw_clk_nkmp.c69 #define READ4(_clk, off, val) \ macro
89 READ4(clk, sc->offset, &val); in aw_clk_nkmp_init()
111 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_gate()
134 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_mux()
202 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq_scale()
246 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq_scale()
291 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq()
306 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq()
315 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq()
338 READ4(clk, sc->offset, &val); in aw_clk_nkmp_recalc()
H A Daw_clk_np.c66 #define READ4(_clk, off, val) \ macro
96 READ4(clk, sc->offset, &val); in aw_clk_np_set_gate()
172 READ4(clk, sc->offset, &val); in aw_clk_np_set_freq()
186 READ4(clk, sc->offset, &val); in aw_clk_np_set_freq()
208 READ4(clk, sc->offset, &val); in aw_clk_np_recalc()
H A Daw_clk_nm.c67 #define READ4(_clk, off, val) \ macro
85 READ4(clk, sc->offset, &val); in aw_clk_nm_init()
107 READ4(clk, sc->offset, &val); in aw_clk_nm_set_gate()
130 READ4(clk, sc->offset, &val); in aw_clk_nm_set_mux()
242 READ4(clk, sc->offset, &val); in aw_clk_nm_set_freq()
256 READ4(clk, sc->offset, &val); in aw_clk_nm_set_freq()
278 READ4(clk, sc->offset, &val); in aw_clk_nm_recalc()
H A Daw_clk_prediv_mux.c65 #define READ4(_clk, off, val) \ macro
83 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_init()
102 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_set_mux()
120 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_recalc()
H A Daw_clk_frac.c74 #define READ4(_clk, off, val) \ macro
92 READ4(clk, sc->offset, &val); in aw_clk_frac_init()
116 READ4(clk, sc->offset, &val); in aw_clk_frac_set_gate()
140 READ4(clk, sc->offset, &val); in aw_clk_frac_set_mux()
269 READ4(clk, sc->offset, &val); in aw_clk_frac_set_freq()
301 READ4(clk, sc->offset, &val); in aw_clk_frac_set_freq()
322 READ4(clk, sc->offset, &val); in aw_clk_frac_recalc()
H A Daw_clk_nmm.c67 #define READ4(_clk, off, val) \ macro
97 READ4(clk, sc->offset, &val); in aw_clk_nmm_set_gate()
180 READ4(clk, sc->offset, &val); in aw_clk_nmm_set_freq()
197 READ4(clk, sc->offset, &val); in aw_clk_nmm_set_freq()
219 READ4(clk, sc->offset, &val); in aw_clk_nmm_recalc()
H A Daw_clk_mipi.c72 #define READ4(_clk, off, val) \ macro
104 READ4(clk, sc->offset, &val); in aw_clk_mipi_set_gate()
180 READ4(clk, sc->offset, &val); in aw_clk_mipi_set_freq()
204 READ4(clk, sc->offset, &val); in aw_clk_mipi_set_freq()
225 READ4(clk, sc->offset, &val); in aw_clk_mipi_recalc()

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