Searched refs:QCA953X_PLL_ETH_XMII_CONTROL_REG (Results 1 – 2 of 2) sorted by relevance
68 #define QCA953X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c) macro
196 ATH_WRITE_REG(QCA953X_PLL_ETH_XMII_CONTROL_REG, pll); in qca953x_chip_set_pll_ge()