| /f-stack/freebsd/contrib/device-tree/Bindings/mfd/ |
| H A D | omap-usb-host.txt | 40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
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| H A D | stmpe.txt | 28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
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| /f-stack/freebsd/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos5433-tmu.dtsi | 56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
248 /* Set maximum frequency as 900MHz */
[all …]
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| /f-stack/freebsd/contrib/device-tree/src/arm/ |
| H A D | integratorcp.dts | 49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
146 /* TIMER0 runs directly on the 25MHz chrystal */
152 /* TIMER1 runs @ 1MHz */
158 /* TIMER2 runs @ 1MHz */
294 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
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| H A D | rk3288-veyron-mickey.dts | 86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
206 /* When really hot, don't let GPU go _above_ 300 MHz */
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| H A D | exynos5422-odroid-core.dtsi | 41 /* derived from 532MHz MPLL */
67 /* derived from 666MHz CPLL */
85 /* derived from 666MHz CPLL */
97 /* derived from 600MHz DPLL */
112 /* derived from 666MHz CPLL */
133 /* derived from 532MHz MPLL */
151 /* derived from 666MHz CPLL */
160 /* derived from 666MHz CPLL */
181 /* derived from 532MHz MPLL */
199 /* derived from 600MHz DPLL */
[all …]
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| H A D | integratorap.dts | 31 * that the maximum frequency for this clock is 200 MHz
33 * is actually just hanging the system above 71 MHz.
59 /* 24 MHz chrystal on the Integrator/AP development board */
74 /* The UART clock is 14.74 MHz divided by an ICS525 */
83 /* 24 MHz chrystal on the core module */
99 /* Auxilary oscillator on the core module, 32.369MHz at boot */
125 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| H A D | allwinner,sun7i-a20-gmac-clk.yaml | 26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
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| /f-stack/freebsd/contrib/device-tree/Bindings/display/bridge/ |
| H A D | toshiba,tc358767.txt | 8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
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| H A D | ti,sn65dsi86.txt | 29 clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
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| H A D | ti,sn65dsi86.yaml | 56 be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
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| /f-stack/freebsd/contrib/device-tree/Bindings/regulator/ |
| H A D | max8952.txt | 15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
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| H A D | mps,mpq7920.yaml | 37 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
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| /f-stack/freebsd/contrib/device-tree/Bindings/usb/ |
| H A D | rockchip,dwc3.txt | 8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
11 operation and >= 30MHz for HS operation
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| H A D | qcom,dwc3.yaml | 44 - description: Master/Core clock, has to be >= 125 MHz
45 for SS operation and >= 60MHz for HS operation.
48 in host mode. Its frequency should be 19.2MHz.
67 - description: Must be 19.2MHz (19200000).
68 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
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| /f-stack/freebsd/contrib/device-tree/Bindings/mips/cavium/ |
| H A D | uctl.txt | 29 /* 12MHz, 24MHz and 48MHz allowed */
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| /f-stack/dpdk/doc/guides/linux_gsg/ |
| H A D | nic_perf_intel_platform.rst | 46 Speed: 2133 MHz
47 Configured Clock Speed: 2134 MHz
50 Speed: 2133 MHz
51 Configured Clock Speed: 2134 MHz
54 Speed: 2133 MHz
55 Configured Clock Speed: 2134 MHz
58 Speed: 2133 MHz
59 Configured Clock Speed: 2134 MHz
63 The output shows a speed of 2133 MHz (DDR4) and Unknown (not existing).
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| /f-stack/freebsd/contrib/device-tree/src/powerpc/ |
| H A D | media5200.dts | 29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
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| H A D | gamecube.dts | 34 clock-frequency = <486000000>; /* 486MHz */
35 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
36 timebase-frequency = <40500000>; /* 162MHz / 4 */
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| /f-stack/freebsd/contrib/device-tree/Bindings/input/touchscreen/ |
| H A D | stmpe.txt | 53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
79 /* 3.25 MHz ADC clock speed */
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| /f-stack/freebsd/contrib/device-tree/Bindings/media/spi/ |
| H A D | sony-cxd2880.txt | 6 - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
17 spi-max-frequency = <55000000>; /* 55MHz */
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| /f-stack/freebsd/contrib/device-tree/Bindings/ufs/ |
| H A D | ufshcd-pltfrm.txt | 42 specification allows host to provide one of the 4 frequencies (19.2 MHz,
43 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
45 Defaults to 26 MHz(as per specification) if not specified by host.
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | micrel.txt | 23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
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| /f-stack/freebsd/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,qmp-phy.yaml | 115 - description: 19.2 MHz ref clk.
143 - description: 19.2 MHz ref clk.
174 - description: 19.2 MHz ref clk.
198 - description: 19.2 MHz ref clk.
221 - description: 19.2 MHz ref clk.
268 - description: 19.2 MHz ref clk.
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