Searched refs:LR (Results 1 – 9 of 9) sorted by relevance
83 state->registers[LR]); in db_stack_trace_cmd()84 db_printsym(state->registers[LR], DB_STGY_PROC); in db_stack_trace_cmd()91 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()162 state.registers[LR] = ctx->pcb_regs.sf_lr; in db_trace_thread()182 state.registers[LR] = (uint32_t)__builtin_return_address(0); in db_trace_self()
63 state.registers[LR] = (uint32_t)__builtin_return_address(0); in stack_save()83 state.registers[LR] = td->td_pcb->pcb_regs.sf_lr; in stack_save_td()
487 state->registers[FP], state->registers[SP], state->registers[LR], in unwind_exec_insn()528 state->registers[PC] = state->registers[LR]; in unwind_tab()
35 GPIO ordered MO, LR, and UD as specified in LS037V7DW01.pdf58 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
55 #define LR 14 macro
18 * Intel® 10 Gigabit XF LR Server Adapter
105 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
308 - Intel 10 Gigabit XF LR Server Adapter
112 UINT64 LR; member