Searched refs:JZ_TCU_BASE (Results 1 – 2 of 2) sorted by relevance
103 writereg(JZ_TCU_BASE + JZ_WDOG_TCER, 0); /* disable watchdog */ in platform_reset()104 writereg(JZ_TCU_BASE + JZ_WDOG_TCNT, 0); /* reset counter */ in platform_reset()105 writereg(JZ_TCU_BASE + JZ_WDOG_TDR, 128); /* wait for ~1s */ in platform_reset()106 writereg(JZ_TCU_BASE + JZ_WDOG_TCSR, TCSR_RTC_EN | TCSR_DIV_256); in platform_reset()107 writereg(JZ_TCU_BASE + JZ_WDOG_TCER, TCER_ENABLE); /* fire! */ in platform_reset()
49 #define JZ_TCU_BASE 0x10002000 macro