Searched refs:IMX7D_PLL_ENET_MAIN_100M_CLK (Results 1 – 9 of 9) sorted by relevance
186 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,192 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
199 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;226 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
52 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro