Home
last modified time | relevance | path

Searched refs:GATE_PLL (Results 1 – 3 of 3) sorted by relevance

/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_car.c109 #define GATE_PLL(_id, cname, plist, o, s) \ macro
247 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
248 GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0),
249 GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
250 GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0),
251 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
252 GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16),
253 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
254 GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
255 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
[all …]
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c225 #define GATE_PLL(_id, cname, plist, o, s) \ macro
504 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
506 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
507 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
508 GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
509 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
511 GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0),
512 GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16),
517 GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0),
518 GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0),
[all …]
H A Dtegra210_car.c110 #define GATE_PLL(_id, cname, plist, o, s) \ macro