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Searched refs:E1000_EIMS (Results 1 – 4 of 4) sorted by relevance

/f-stack/dpdk/drivers/net/e1000/
H A Digb_regs.h39 {E1000_EIMS, 1, 1, "E1000_EIMS"},
H A Digb_ethdev.c524 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC); in igb_intr_enable()
557 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX); in igbvf_intr_enable()
2799 regval = E1000_READ_REG(hw, E1000_EIMS); in eth_igb_rxq_interrupt_setup()
2800 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); in eth_igb_rxq_interrupt_setup()
5159 regval = E1000_READ_REG(hw, E1000_EIMS); in eth_igb_rx_queue_intr_enable()
5160 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); in eth_igb_rx_queue_intr_enable()
5258 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER); in eth_igb_configure_msix_intr()
5279 regval = E1000_READ_REG(hw, E1000_EIMS); in eth_igb_configure_msix_intr()
5280 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); in eth_igb_configure_msix_intr()
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_vf.h45 #define E1000_EIMS 0x01524 /* Ext. Intr Mask Set/Read -RW */ macro
H A De1000_regs.h66 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ macro