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Searched refs:Control (Results 1 – 25 of 182) sorted by relevance

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/f-stack/freebsd/contrib/dev/acpica/components/dispatcher/
H A Ddscontrol.c202 if (WalkState->ControlState->Control.AmlPredicateStart == in AcpiDsExecBeginControlOp()
231 ControlState->Control.AmlPredicateStart = in AcpiDsExecBeginControlOp()
233 ControlState->Control.PackageEnd = in AcpiDsExecBeginControlOp()
235 ControlState->Control.Opcode = in AcpiDsExecBeginControlOp()
237 ControlState->Control.LoopTimeout = AcpiOsGetTimer () + in AcpiDsExecBeginControlOp()
337 ControlState->Control.LoopTimeout)) in AcpiDsExecEndControlOp()
349 ControlState->Control.AmlPredicateStart; in AcpiDsExecEndControlOp()
486 (WalkState->ControlState->Control.Opcode != AML_WHILE_OP)) in AcpiDsExecEndControlOp()
502 WalkState->ControlState->Control.PackageEnd; in AcpiDsExecEndControlOp()
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dwm8960.txt26 hp-cfg[0]: HPSEL[1:0] of R48 (Additional Control 4).
27 hp-cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2).
28 hp-cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1).
33 gpio-cfg[1]: {GPIOPOL:GPIOSEL[2:0]} of R48 (Additional Control 4).
H A Dalc5623.txt10 - add-ctrl: Default register value for Reg-40h, Additional Control
15 Control Register. If absent or has value 0, the
H A Dwm8962.txt13 of R51 (Class D Control 2) gets set, indicating that the speaker is
16 - mic-cfg : Default register value for R48 (Additional Control 4).
H A Dcs35l35.txt84 Section 7.29 Class H Control
89 Section 7.30 Class H Headroom Control
95 Section 7.32 Class H Weak FET Drive Control
100 Section 7.34 Class H VP Control
111 See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet
H A Dwm8524.txt3 This device does not use I2C or SPI but a simple Hardware Control Interface.
/f-stack/freebsd/contrib/device-tree/Bindings/arm/omap/
H A Dctrl.txt1 OMAP Control Module bindings
3 Control Module contains miscellaneous features under it based on SoC type.
30 - reg: Contains Control Module register address range
/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Dscu.txt1 * ARM Snoop Control Unit (SCU)
4 with a Snoop Control Unit. The register range is usually 256 (0x100)
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Ddove-divider-clock.txt19 Control 0 register. This will cover that register, as well as the
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
H A Dbaikal,bt1-ccu-div.yaml8 title: Baikal-T1 Clock Control Unit Dividers
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
146 # AXI-bus Clock Control Unit node:
161 # System Devices Clock Control Unit node:
178 # Required Clock Control Unit PLL node:
H A Dimx8mq-clock.yaml7 title: NXP i.MX8M Quad Clock Control Module Binding
58 # Clock Control Module node:
H A Dimx8mp-clock.yaml7 title: NXP i.MX8M Plus Clock Control Module Binding
58 # Clock Control Module node:
H A Dimx8mm-clock.yaml7 title: NXP i.MX8M Mini Clock Control Module Binding
56 # Clock Control Module node:
H A Dimx8mn-clock.yaml7 title: NXP i.MX8M Nano Clock Control Module Binding
58 # Clock Control Module node:
H A Dimx7ulp-pcc-clock.yaml7 title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
28 The Peripheral Clock Control (PCC) is responsible for clock selection,
H A Dimx7ulp-clock.txt4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
36 Peripheral Clock Control (PCC) modules:
38 The Peripheral Clock Control (PCC) is responsible for clock selection,
H A Dlpc1850-ccu.txt1 * NXP LPC1850 Clock Control Unit (CCU)
4 or off independently by the Clock Control Units CCU1 or CCU2. The
/f-stack/freebsd/contrib/device-tree/Bindings/hwmon/
H A Dadi,axi-fan-control.yaml8 title: Analog Devices AXI FAN Control Device Tree Bindings
14 Bindings for the Analog Devices AXI FAN Control driver. Spefications of the
/f-stack/freebsd/contrib/device-tree/Bindings/gpio/
H A Dgpio-xra1403.txt11 - Output Level Control
12 - Output Three-State Control
/f-stack/dpdk/doc/guides/prog_guide/
H A Dglossary.rst9 Access Control List
26 Control Plane
88 Input/Output Control
214 Transmission Control Protocol
/f-stack/freebsd/contrib/dev/acpica/components/parser/
H A Dpsloop.c334 WalkState->ControlState->Control.PackageEnd = in AcpiPsGetArguments()
556 ((WalkState->ControlState->Control.Opcode == AML_IF_OP) || in AcpiPsParseLoop()
557 (WalkState->ControlState->Control.Opcode == AML_WHILE_OP))) in AcpiPsParseLoop()
564 WalkState->ControlState->Control.AmlPredicateStart + 1; in AcpiPsParseLoop()
/f-stack/freebsd/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx-fb.txt21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
23 - fsl,lpccr: Contrast Control Register value. This property provides the
/f-stack/freebsd/contrib/device-tree/Bindings/iio/adc/
H A Dadi,ad7292.yaml7 title: Analog Devices AD7292 10-Bit Monitor and Control System
13 Analog Devices AD7292 10-Bit Monitor and Control System with ADC, DACs,
/f-stack/freebsd/contrib/device-tree/Bindings/arm/marvell/
H A D98dx3236-resume-ctrl.txt1 Resume Control
/f-stack/freebsd/contrib/device-tree/Bindings/power/
H A Dfsl,imx-gpcv2.yaml13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
14 Control (PGC) for various power domains.

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