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Searched refs:CSR_READ_4 (Results 1 – 7 of 7) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c578 *val = CSR_READ_4(sc, addr); in jz4780_clock_read_4()
590 val = CSR_READ_4(sc, addr); in jz4780_clock_modify_4()
686 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ohci_enable()
717 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
722 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ehci_enable()
742 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
746 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
751 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
757 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
800 reg = CSR_READ_4(sc, JZ_USBRDT); in jz4780_otg_enable()
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H A Djz4780_efuse.c75 #define CSR_READ_4(sc, reg) \ macro
104 while ((CSR_READ_4(sc, JZ_EFUSTATE) & JZ_EFUSE_RD_DONE) == 0) in jz4780_efuse_read_chunk()
111 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
118 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
H A Djz4780_gpio.c110 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
240 val = CSR_READ_4(sc, JZ_GPIO_INT); in jz4780_gpio_pin_probe()
243 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
249 val = CSR_READ_4(sc, JZ_GPIO_PAT0); in jz4780_gpio_pin_probe()
260 val = CSR_READ_4(sc, JZ_GPIO_MASK); in jz4780_gpio_pin_probe()
263 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
269 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
277 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
524 data = CSR_READ_4(sc, JZ_GPIO_PIN); in jz4780_gpio_pin_get()
547 data = CSR_READ_4(sc, JZ_GPIO_PIN); in jz4780_gpio_pin_toggle()
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H A Djz4780_timer.c79 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
87 return CSR_READ_4(sc, JZ_OST_CNT_LO); in jz4780_get_timecount()
H A Djz4780_nemc.c77 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
122 smcr = CSR_READ_4(sc, JZ_NEMC_SMCR(bank)); in jz4780_nemc_configure_bank()
/f-stack/freebsd/mips/atheros/ar531x/
H A Dif_are.c462 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) in are_miibus_readreg()
466 return (CSR_READ_4(sc, CSR_MIIDATA) & 0xffff); in are_miibus_readreg()
485 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) in are_miibus_writereg()
551 if ((CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) == 0) in are_reset()
555 if (CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) in are_reset()
834 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7; in are_encap()
893 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7; in are_start_locked()
920 CSR_READ_4(sc, CSR_MACCTL) & ~(MACCTL_TE | MACCTL_RE)); in are_stop()
933 macctl = CSR_READ_4(sc, CSR_MACCTL); in are_set_filter()
1633 status = CSR_READ_4(sc, CSR_STATUS); in are_intr()
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H A Dif_arereg.h141 #define CSR_READ_4(sc, reg) \ macro