| /f-stack/app/redis-5.0.5/deps/jemalloc/ |
| H A D | .appveyor.yml | 6 CPU: x86_64
9 CPU: i686
12 CPU: x86_64
14 CPU: i686
16 CPU: x86_64
20 CPU: i686
24 CPU: x86_64
27 CPU: i686
33 - if defined MSVC pacman --noconfirm -Rsc mingw-w64-%CPU%-gcc gcc
34 - pacman --noconfirm -Suy mingw-w64-%CPU%-make
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| /f-stack/dpdk/doc/guides/cryptodevs/features/ |
| H A D | aesni_gcm.ini | 9 CPU AESNI = Y
10 CPU SSE = Y
11 CPU AVX = Y
12 CPU AVX2 = Y
13 CPU AVX512 = Y
17 CPU crypto = Y
|
| H A D | default.ini | 14 CPU SSE =
15 CPU AVX =
16 CPU AVX2 =
17 CPU AVX512 =
18 CPU AESNI =
19 CPU NEON =
20 CPU ARM CE =
30 CPU crypto =
|
| H A D | aesni_mb.ini | 10 CPU SSE = Y
11 CPU AVX = Y
12 CPU AVX2 = Y
13 CPU AVX512 = Y
14 CPU AESNI = Y
16 CPU crypto = Y
|
| /f-stack/freebsd/contrib/device-tree/Bindings/arm/ |
| H A D | coresight-cpu-debug.txt | 1 * CoreSight CPU Debug Component:
3 CoreSight CPU debug component are compliant with the ARMv8 architecture
7 and eventually the debug module connects with CPU for debugging. And the
9 to sample CPU program counter, secure state and exception level, etc;
10 usually every CPU has one dedicated debug module to be connected.
26 processor core is clocked by the internal CPU clock, so it
27 is enabled with CPU clock by default.
29 - cpu : the CPU phandle the debug module is affined to. Do not assume it
38 constrain idle states to ensure registers in the CPU power
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| H A D | cpu-capacity.txt | 15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
36 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
53 fall back to the default capacity value for every CPU. If cpufreq is not
|
| /f-stack/dpdk/doc/guides/compressdevs/features/ |
| H A D | default.ini | 10 CPU SSE =
11 CPU AVX =
12 CPU AVX2 =
13 CPU AVX512 =
14 CPU NEON =
|
| H A D | isal.ini | 7 CPU SSE = Y
8 CPU AVX = Y
9 CPU AVX2 = Y
10 CPU AVX512 = Y
|
| /f-stack/freebsd/contrib/device-tree/Bindings/mips/ |
| H A D | mscc.txt | 12 o CPU chip regs:
29 o CPU system control:
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
33 endianness, CPU bus control, CPU status.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/nios2/ |
| H A D | nios2.txt | 12 - reg: Contains CPU index.
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
26 - altr,has-mul: Specifies CPU hardware multipy support, should be 1.
27 - altr,has-mmu: Specifies CPU support MMU support, should be 1.
28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
29 - altr,reset-addr: Specifies CPU reset address
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
31 - altr,exception-addr: Specifies CPU exception address
34 - altr,has-div: Specifies CPU hardware divide support
|
| /f-stack/freebsd/contrib/device-tree/Bindings/cpufreq/ |
| H A D | nvidia,tegra20-cpufreq.txt | 5 - clocks: Must contain an entry for the CPU clock.
13 1. CPU process ID mask
17 1. CPU process ID mask
18 2. CPU speedo ID mask
23 - opp-microvolt: CPU voltage triplet.
26 - cpu-supply: Phandle to the CPU power supply.
|
| H A D | brcm,stb-avs-cpu-freq.txt | 5 references the mailbox register used to communicate with the AVS CPU[1]. The
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
15 [1] The AVS CPU is an independent co-processor that runs proprietary
30 - interrupts: The interrupt that the AVS CPU will use to interrupt the host
|
| /f-stack/freebsd/contrib/device-tree/Bindings/regulator/ |
| H A D | nvidia,tegra-regulators-coupling.txt | 11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
13 and they both shall be higher than the CPU voltage by at least 120mV.
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
20 voltage shall be higher than the CPU by N mV, where N depends on the CPU
29 as the "CPU domain" voltage regulator.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/watchdog/ |
| H A D | atmel-sama5d4-wdt.txt | 9 - interrupts: interrupt number to the CPU.
15 - atmel,idle-halt: present if you want to stop the watchdog when the CPU is
18 watchdog not counting when the CPU is in idle state, therefore the
19 watchdog reset time depends on mean CPU usage and will not reset at all
20 if the CPU stop working while it is in idle state, which is probably
22 - atmel,dbg-halt: present if you want to stop the watchdog when the CPU is
|
| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | hisilicon-hns-nic.txt | 16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
19 | CPU |
27 LAN Switch while the CPU side assume itself have one single NIC connect to
30 | CPU |
44 to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram:
46 | CPU |
54 ports connected to a LAN Switch while the CPU side assume itself have one
58 | CPU |
|
| /f-stack/freebsd/contrib/device-tree/Bindings/mips/img/ |
| H A D | pistachio.txt | 8 CPU nodes:
13 A CPU sub-node is also required for at least CPU 0. Since the topology may
18 - reg: CPU number.
19 - clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for
|
| /f-stack/freebsd/contrib/device-tree/Bindings/openrisc/opencores/ |
| H A D | or1ksim.txt | 13 CPU nodes:
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
22 - reg: CPU number.
23 - clock-frequency: The CPU clock frequency in Hz.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/arm/marvell/ |
| H A D | mvebu-cpu-config.txt | 1 MVEBU CPU Config registers
12 - reg: Should contain CPU config registers location and length, in
13 their per-CPU variant
|
| /f-stack/freebsd/contrib/device-tree/Bindings/arm/freescale/ |
| H A D | fsl,vf610-mscm-cpucfg.txt | 1 Freescale Vybrid Miscellaneous System Control - CPU Configuration
4 block of registers which contains CPU configuration information.
8 - reg: the register range of the MSCM CPU configuration registers
|
| /f-stack/dpdk/doc/guides/rel_notes/ |
| H A D | release_20_08.rst | 360 * List of CPU
371 * CPU
373 * Intel\ |reg| Atom\ |trade| CPU C3758 @ 2.20GHz
374 * Intel\ |reg| Atom\ |trade| CPU C3858 @ 2.00GHz
375 * Intel\ |reg| Atom\ |trade| CPU C3958 @ 2.00GHz
376 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
377 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
478 * CPU:
486 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
590 * CPU:
[all …]
|
| H A D | release_20_05.rst | 392 * List of CPU
403 * CPU:
453 * CPU
455 * Intel\ |reg| Atom\ |trade| CPU C3758 @ 2.20GHz
456 * Intel\ |reg| Atom\ |trade| CPU C3858 @ 2.00GHz
457 * Intel\ |reg| Atom\ |trade| CPU C3958 @ 2.00GHz
458 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
459 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
560 * CPU:
567 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
[all …]
|
| /f-stack/freebsd/contrib/device-tree/Bindings/arm/msm/ |
| H A D | qcom,kpss-acc.txt | 3 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
4 There is one ACC register region per CPU within the KPSS remapped region as
6 with the CPU accessing the region.
38 CPU number starting at 0.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | brcm,bcm6345-l1-intc.txt | 4 directly to one of the HW INT lines on each CPU.
12 - A separate instance of the register set for each CPU, allowing individual
13 peripheral IRQs to be routed to any CPU
15 - Contains one or more enable/status word pairs per CPU
40 The driver operates in native CPU endian by default, there is no support for
|
| /f-stack/freebsd/contrib/device-tree/Bindings/arm/bcm/ |
| H A D | brcm,bcm63138.txt | 11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
20 Optional properties for the primary CPU node:
23 Optional properties for the secondary CPU node:
26 bus number, and a second integer indicating the address of the CPU in the PMB
|
| /f-stack/freebsd/contrib/device-tree/Bindings/power/ |
| H A D | renesas,apmu.yaml | 15 CPU core power domain control including SMP boot and CPU Hotplug.
39 Array of phandles pointing to CPU cores, which should match the order of
40 CPU cores used by the WUPCR and PSTR registers in the Advanced Power
|