Searched refs:CLK_TOP_UNIVPLL2_D4 (Results 1 – 12 of 12) sorted by relevance
19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
31 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
49 #define CLK_TOP_UNIVPLL2_D4 38 macro
55 #define CLK_TOP_UNIVPLL2_D4 45 macro
49 #define CLK_TOP_UNIVPLL2_D4 37 macro
73 #define CLK_TOP_UNIVPLL2_D4 63 macro
62 #define CLK_TOP_UNIVPLL2_D4 27 macro
78 #define CLK_TOP_UNIVPLL2_D4 68 macro
62 #define CLK_TOP_UNIVPLL2_D4 31 macro
40 #define CLK_TOP_UNIVPLL2_D4 30 macro
254 <&topckgen CLK_TOP_UNIVPLL2_D4>;324 <&topckgen CLK_TOP_UNIVPLL2_D4>,385 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
554 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,633 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,646 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,659 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,672 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,