Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 – 13 of 13) sorted by relevance
16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
111 <&topckgen CLK_TOP_UNIVPLL1_D2>,120 <&topckgen CLK_TOP_UNIVPLL1_D2>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;325 <&topckgen CLK_TOP_UNIVPLL1_D2>;387 <&topckgen CLK_TOP_UNIVPLL1_D2>;470 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
43 #define CLK_TOP_UNIVPLL1_D2 32 macro
50 #define CLK_TOP_UNIVPLL1_D2 40 macro
44 #define CLK_TOP_UNIVPLL1_D2 32 macro
68 #define CLK_TOP_UNIVPLL1_D2 58 macro
58 #define CLK_TOP_UNIVPLL1_D2 23 macro
73 #define CLK_TOP_UNIVPLL1_D2 63 macro
57 #define CLK_TOP_UNIVPLL1_D2 26 macro
36 #define CLK_TOP_UNIVPLL1_D2 26 macro
322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
1426 <&topckgen CLK_TOP_UNIVPLL1_D2>,