Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 8 of 8) sorted by relevance
46 #define CLK_TOP_SYSPLL4_D2 36 macro
39 #define CLK_TOP_SYSPLL4_D2 27 macro
60 #define CLK_TOP_SYSPLL4_D2 50 macro
49 #define CLK_TOP_SYSPLL4_D2 14 macro
65 #define CLK_TOP_SYSPLL4_D2 55 macro
48 #define CLK_TOP_SYSPLL4_D2 17 macro
25 #define CLK_TOP_SYSPLL4_D2 15 macro
30 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.