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Searched refs:ATH_WRITE_REG (Results 1 – 20 of 20) sorted by relevance

/f-stack/freebsd/mips/atheros/
H A Dar71xx_pci.c122 ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq)); in ar71xx_pci_unmask_irq()
165 ATH_WRITE_REG(AR71XX_PCI_ERROR, error); in ar71xx_pci_check_bus_error()
177 ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error); in ar71xx_pci_check_bus_error()
204 ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr); in ar71xx_pci_conf_setup()
205 ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd); in ar71xx_pci_conf_setup()
261 ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); in ar71xx_pci_local_write()
262 ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data); in ar71xx_pci_local_write()
278 ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data); in ar71xx_pci_write_config()
320 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val); in ar71xx_pci_fixup()
409 ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0); in ar71xx_pci_attach()
[all …]
H A Dar71xx_wdog.c87 ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL, RST_WDOG_ACTION_NOACTION); in ar71xx_wdog_watchdog_fn()
95 ATH_WRITE_REG(AR71XX_RST_WDOG_TIMER, timer_val); in ar71xx_wdog_watchdog_fn()
102 ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL, action); in ar71xx_wdog_watchdog_fn()
109 ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL, in ar71xx_wdog_watchdog_fn()
162 ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL, RST_WDOG_ACTION_NOACTION); in ar71xx_wdog_attach()
H A Dar71xx_chip.c126 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask); in ar71xx_chip_device_stop()
135 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask); in ar71xx_chip_device_start()
184 ATH_WRITE_REG(reg, val); in ar71xx_chip_set_mii_speed()
230 ATH_WRITE_REG(reg, val); in ar71xx_chip_set_mii_if()
314 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG, in ar71xx_chip_init_usb_peripheral()
320 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, in ar71xx_chip_init_usb_peripheral()
H A Dqca955x_chip.c163 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg | mask); in qca955x_chip_device_stop()
172 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg & ~mask); in qca955x_chip_device_start()
197 ATH_WRITE_REG(QCA955X_PLL_ETH_XMII_CONTROL_REG, pll); in qca955x_chip_set_pll_ge()
200 ATH_WRITE_REG(QCA955X_PLL_ETH_SGMII_CONTROL_REG, pll); in qca955x_chip_set_pll_ge()
282 ATH_WRITE_REG(QCA955X_GMAC_REG_ETH_CFG, reg); in qca955x_configure_gmac()
379 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t); in qca955x_chip_gpio_output_configure()
H A Dar71xxreg.h539 #define ATH_WRITE_REG(reg, val) \ macro
545 ATH_WRITE_REG(reg, 1); in ar71xx_ddr_flush()
548 ATH_WRITE_REG(reg, 1); in ar71xx_ddr_flush()
563 ATH_WRITE_REG(cfg_reg, sec_cfg); in ar71xx_write_pll()
566 ATH_WRITE_REG(pll_reg, pll); in ar71xx_write_pll()
568 ATH_WRITE_REG(cfg_reg, sec_cfg); in ar71xx_write_pll()
572 ATH_WRITE_REG(cfg_reg, sec_cfg); in ar71xx_write_pll()
H A Dar724x_pci.c113 ATH_WRITE_REG(reg + (offset & ~3), val); in ar724x_pci_write()
198 ATH_WRITE_REG(AR724X_PCI_INTR_MASK, in ar724x_pci_mask_irq()
203 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, in ar724x_pci_mask_irq()
219 ATH_WRITE_REG(AR724X_PCI_INTR_MASK, in ar724x_pci_unmask_irq()
239 ATH_WRITE_REG(AR724X_PCI_RESET, 0); in ar724x_pci_setup()
241 ATH_WRITE_REG(AR724X_PCI_RESET, 4); in ar724x_pci_setup()
249 ATH_WRITE_REG(AR724X_PCI_APP, reg); in ar724x_pci_setup()
265 ATH_WRITE_REG(AR724X_PCI_APP, reg); in ar724x_pci_setup()
314 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val); in ar724x_pci_fixup()
398 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0); in ar724x_pci_attach()
[all …]
H A Dqca953x_chip.c162 ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg | mask); in qca953x_chip_device_stop()
171 ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg & ~mask); in qca953x_chip_device_start()
196 ATH_WRITE_REG(QCA953X_PLL_ETH_XMII_CONTROL_REG, pll); in qca953x_chip_set_pll_ge()
273 ATH_WRITE_REG(QCA953X_GMAC_REG_ETH_CFG, reg); in qca953x_configure_gmac()
370 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t); in qca953x_chip_gpio_output_configure()
H A Dqca955x_pci.c127 ATH_WRITE_REG(reg + (offset & ~3), val); in qca955x_pci_write()
195 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, in qca955x_pci_mask_irq()
200 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS, in qca955x_pci_mask_irq()
216 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, in qca955x_pci_unmask_irq()
239 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET, 0); in qca955x_pci_setup()
242 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET, 4); in qca955x_pci_setup()
247 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP, 0x1ffc1); in qca955x_pci_setup()
313 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS, 0); in qca955x_pci_attach()
314 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, 0); in qca955x_pci_attach()
H A Dar724x_chip.c106 ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); in ar724x_chip_device_stop()
118 ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); in ar724x_chip_device_start()
211 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, in ar724x_chip_init_usb_peripheral()
H A Dar934x_chip.c213 ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg | mask); in ar934x_chip_device_stop()
222 ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg & ~mask); in ar934x_chip_device_start()
251 ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll); in ar934x_chip_set_pll_ge()
339 ATH_WRITE_REG(AR934X_GMAC_REG_ETH_CFG, reg); in ar934x_configure_gmac()
452 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t); in ar934x_chip_gpio_output_configure()
H A Dar933x_chip.c145 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask); in ar933x_chip_device_stop()
154 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask); in ar933x_chip_device_start()
280 ATH_WRITE_REG(AR933X_GMAC_REG_ETH_CFG, reg); in ar933x_configure_gmac()
H A Dar91xx_chip.c97 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask); in ar91xx_chip_device_stop()
106 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask); in ar91xx_chip_device_start()
H A Duart_bus_ar71xx.c103 ATH_WRITE_REG(AR71XX_UART_ADDR + AR71XX_UART_THR, (c & 0xff)); in ar71xx_early_putc()
H A Duart_bus_ar933x.c111 ATH_WRITE_REG(AR71XX_UART_ADDR + AR933X_UART_DATA_REG, in ar933x_early_putc()
H A Dapb.c92 ATH_WRITE_REG(AR71XX_MISC_INTR_MASK, reg & ~(1 << irq)); in apb_mask_irq()
103 ATH_WRITE_REG(AR71XX_MISC_INTR_MASK, reg | (1 << irq)); in apb_unmask_irq()
373 ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS, in apb_filter()
/f-stack/freebsd/mips/atheros/ar531x/
H A Dar5315_wdog.c73 ATH_WRITE_REG(ar531x_wdog_timer(), in ar5315_wdog_watchdog_fn()
75 ATH_WRITE_REG(ar531x_wdog_ctl(), in ar5315_wdog_watchdog_fn()
77 ATH_WRITE_REG(ar531x_wdog_timer(), in ar5315_wdog_watchdog_fn()
85 ATH_WRITE_REG(ar531x_wdog_ctl(), in ar5315_wdog_watchdog_fn()
128 ATH_WRITE_REG(ar531x_wdog_ctl(), AR5315_WDOG_CTL_IGNORE); in ar5315_wdog_attach()
H A Dar5315_chip.c166 ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET, in ar5315_chip_device_reset()
173 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR0, in ar5315_chip_device_start()
176 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_WDOG_CTL, in ar5315_chip_device_start()
181 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL, in ar5315_chip_device_start()
192 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_GPIO_INT, 0); in ar5315_chip_device_start()
H A Dar5312_chip.c114 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL, in ar5312_chip_device_reset()
142 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_ENABLE, 0); in ar5312_chip_device_start()
144 ATH_WRITE_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE, in ar5312_chip_device_start()
H A Dapb.c104 ATH_WRITE_REG(AR5315_SYSREG_BASE in apb_mask_irq()
109 ATH_WRITE_REG(AR5312_SYSREG_BASE in apb_mask_irq()
123 ATH_WRITE_REG(AR5315_SYSREG_BASE + in apb_unmask_irq()
128 ATH_WRITE_REG(AR5312_SYSREG_BASE + in apb_unmask_irq()
254 ATH_WRITE_REG(AR5315_SYSREG_BASE in apb_attach()
257 ATH_WRITE_REG(AR5312_SYSREG_BASE in apb_attach()
498 ATH_WRITE_REG(AR5315_SYSREG_BASE + in apb_filter()
502 ATH_WRITE_REG(AR5312_SYSREG_BASE + in apb_filter()
697 ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_MISC_INTSTAT, in apb_pic_post_filter()
702 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_MISC_INTSTAT, in apb_pic_post_filter()
H A Dar5315reg.h227 #define ATH_WRITE_REG(reg, val) \ macro