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Searched refs:FIELD_PREP (Results 1 – 6 of 6) sorted by relevance

/dpdk/drivers/common/cnxk/
H A Droc_bphy_cgx.c56 val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1); in roc_bphy_cgx_ack()
129 scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE); in roc_bphy_cgx_intf_req()
238 val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) | in roc_bphy_cgx_start_stop_rxtx()
239 FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1); in roc_bphy_cgx_start_stop_rxtx()
259 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) | in roc_bphy_cgx_intlbk_ena_dis()
260 FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable); in roc_bphy_cgx_intlbk_ena_dis()
281 FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable); in roc_bphy_cgx_ptp_rx_ena_dis()
332 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS); in roc_bphy_cgx_get_linkinfo()
365 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) | in roc_bphy_cgx_set_link_mode()
411 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_FEC) | in roc_bphy_cgx_fec_set()
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H A Droc_bitfield.h10 #define FIELD_PREP(mask, val) (((typeof(mask))(val) << __bf_shf(mask)) & (mask)) macro
H A Droc_ree.c537 val |= FIELD_PREP(REE_LF_SBUF_ADDR_PTR_MASK, qp->iq_dma_addr >> 7); in roc_ree_iq_enable()
544 val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 1); in roc_ree_iq_enable()
558 val |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 0); in roc_ree_iq_disable()
/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_nsp.c232 FIELD_PREP(NSP_BUFFER_CPP, buff_cpp >> 8) | in nfp_nsp_command()
233 FIELD_PREP(NSP_BUFFER_ADDRESS, buff_addr)); in nfp_nsp_command()
238 FIELD_PREP(NSP_COMMAND_OPTION, option) | in nfp_nsp_command()
239 FIELD_PREP(NSP_COMMAND_CODE, code) | in nfp_nsp_command()
240 FIELD_PREP(NSP_COMMAND_START, 1)); in nfp_nsp_command()
H A Dnfp_nsp_eth.c31 #define FIELD_PREP(_mask, _val) \ macro
456 reg |= FIELD_PREP(NSP_ETH_CTRL_ENABLED, enable); in nfp_eth_set_mod_enable()
505 reg |= FIELD_PREP(NSP_ETH_CTRL_CONFIGURED, configed); in nfp_eth_set_configured()
H A Dnfp_nsp.h30 #define FIELD_PREP(_mask, _val) \ macro