Searched refs:ENETFEC_MIBC (Results 1 – 2 of 2) sorted by relevance
83 #define ENETFEC_MIBC 0x064 /* MIB control and status register */ macro
142 rte_write32(0, (uint8_t *)fep->hw_baseaddr_v + ENETFEC_MIBC); in enetfec_restart()