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/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_common_interceptors.inc924 // Common code for `memcmp` and `bcmp`.
3970 // * POSIX version returns 0 on success, negative error code on failure,
5544 // 2. It can be called recursively if sanitizer code uses __tls_get_addr
6707 // buggy code path while the non-sanitized build of the same code works fine.
7653 // Reuse the rest of the code in the strlcpy() interceptor
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrMVE.td27 let DiagnosticString = "condition code for sign-independent integer "#
37 let DiagnosticString = "condition code for signed integer "#
47 let DiagnosticString = "condition code for unsigned integer "#
57 let DiagnosticString = "condition code for floating-point "#
5907 // register comes from (when this instruction is used in code
6504 // code.)
H A DARMScheduleA57.td804 // VMOVRRS/VMOVRRD in common code declared with one WriteFPMOV (instead of 2).
H A DARMInstrThumb.td1537 // Defs. By doing so, we also cause the prologue/epilogue code to actively
/llvm-project-15.0.7/clang/unittests/Format/
H A DFormatTest.cpp22685 std::string code = "#if A\n" in TEST_F() local
22695 EXPECT_EQ(code, format(code)); in TEST_F()
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AMDGPU/
H A Drem.ll7 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
8 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
9 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
10 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
H A Ddiv.ll7 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
8 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
9 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
10 ; RUN: opt -passes='print<cost-model>' -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-un…
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Dmasked_load_store.ll9 ; The source code:
684 ; The source code:
1040 ; The source code:
1318 ; The source code:
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dblock-placement.ll7 ; Test a chain of ifs, where the block guarded by the if is error handling code
H A Dshuffle-vs-trunc-256.ll18 ; Ideally, the shuffles should be lowered to code with the same quality as the truncates.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dp10-setnbc-rr.ll10 ; comparisons (cmplwi, cmpldi). This is because alternative code is generated
H A Dp10-setnbcr-rr.ll10 ; comparisons (cmplwi, cmpldi). This is because alternative code is generated
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-stN-reg-imm-addr-mode.ll7 ; instruction (`st<N>b`), as the code for detecting the immediate is
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dlogical-select.ll160 ; other vector code because of canonicalization to i64 elements for vectors.
H A Dselect-binop-cmp.ll988 ; (optimized code would return -0.0, but this returns +0.0).
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A Darith-overflow.ll5 ; RUN: opt -passes='print<cost-model>' 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.…
6 ; RUN: opt -passes='print<cost-model>' 2>&1 -disable-output -cost-kind=code-size -mtriple=armv8a-li…
7 ; RUN: opt -passes='print<cost-model>' 2>&1 -disable-output -cost-kind=code-size -mtriple=armv8.1m.…
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td1796 // 'ins' and its' 64 bit variants are matched by C++ code.
2453 // scheme because some of this code is shared with Mips32r6InstrInfo.td
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td1017 // variants with the same number of NSA words, and custom code then derives
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td10 /// WebAssembly SIMD operand code-gen constructs.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td938 // immediate shift, i.e. the following code is considered better
H A DX86ScheduleZnver3.td730 defm : Zn3WriteResInt<WriteSETCC, [Zn3ALU03], 1, [2], 1>; // Set register based on condition code.
/llvm-project-15.0.7/llvm/bindings/ocaml/llvm/
H A Dllvm.mli409 (** [enable_pretty_stacktraces ()] enables LLVM's built-in stack trace code.
2699 This type of pipeline is suitable for code generation and JIT compilation
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td475 // when code is emitted.
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1404 // Create SDNodes so they can be used in the DAG code, e.g.
3164 // conditional branch if the target block is the next block so that the code
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td10 /// support code generation for the standard 'V' (Vector) extension, version

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