1 /*
2 ********************************************************************************
3 ** OS : FreeBSD
4 ** FILE NAME : arcmsr.c
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 ** SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
11 **
12 ** SPDX-License-Identifier: BSD-3-Clause
13 **
14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
15 **
16 ** Redistribution and use in source and binary forms, with or without
17 ** modification, are permitted provided that the following conditions
18 ** are met:
19 ** 1. Redistributions of source code must retain the above copyright
20 ** notice, this list of conditions and the following disclaimer.
21 ** 2. Redistributions in binary form must reproduce the above copyright
22 ** notice, this list of conditions and the following disclaimer in the
23 ** documentation and/or other materials provided with the distribution.
24 ** 3. The name of the author may not be used to endorse or promote products
25 ** derived from this software without specific prior written permission.
26 **
27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ********************************************************************************
38 ** History
39 **
40 ** REV# DATE NAME DESCRIPTION
41 ** 1.00.00.00 03/31/2004 Erich Chen First release
42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support
44 ** clean unused function
45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling,
46 ** firmware version check
47 ** and firmware update notify for hardware bug fix
48 ** handling if none zero high part physical address
49 ** of srb resource
50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy
51 ** add iop message xfer
52 ** with scsi pass-through command
53 ** add new device id of sas raid adapters
54 ** code fit for SPARC64 & PPC
55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report
56 ** and cause g_vfs_done() read write error
57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x
58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x
59 ** bus_dmamem_alloc() with BUS_DMA_ZERO
60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880
61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
62 ** prevent cam_periph_error removing all LUN devices of one Target id
63 ** for any one LUN device failed
64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step"
65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function
68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout
69 ** 02/14/2011 Ching Huang Modified pktRequestCount
70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it
71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic
72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller
85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter
86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when
87 ** scatter-gather count large than some number
88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886
89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created
90 ******************************************************************************************
91 */
92
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
95
96 #if 0
97 #define ARCMSR_DEBUG1 1
98 #endif
99 #include <sys/param.h>
100 #include <sys/systm.h>
101 #include <sys/malloc.h>
102 #include <sys/kernel.h>
103 #include <sys/bus.h>
104 #include <sys/queue.h>
105 #include <sys/stat.h>
106 #include <sys/devicestat.h>
107 #include <sys/kthread.h>
108 #include <sys/module.h>
109 #include <sys/proc.h>
110 #include <sys/lock.h>
111 #include <sys/sysctl.h>
112 #include <sys/poll.h>
113 #include <sys/ioccom.h>
114 #include <vm/vm.h>
115 #include <vm/vm_param.h>
116 #include <vm/pmap.h>
117
118 #include <isa/rtc.h>
119
120 #include <machine/bus.h>
121 #include <machine/resource.h>
122 #include <machine/atomic.h>
123 #include <sys/conf.h>
124 #include <sys/rman.h>
125
126 #include <cam/cam.h>
127 #include <cam/cam_ccb.h>
128 #include <cam/cam_sim.h>
129 #include <cam/cam_periph.h>
130 #include <cam/cam_xpt_periph.h>
131 #include <cam/cam_xpt_sim.h>
132 #include <cam/cam_debug.h>
133 #include <cam/scsi/scsi_all.h>
134 #include <cam/scsi/scsi_message.h>
135 /*
136 **************************************************************************
137 **************************************************************************
138 */
139 #include <sys/selinfo.h>
140 #include <sys/mutex.h>
141 #include <sys/endian.h>
142 #include <dev/pci/pcivar.h>
143 #include <dev/pci/pcireg.h>
144
145 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
146
147 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.04 2021-12-08"
148 #include <dev/arcmsr/arcmsr.h>
149 /*
150 **************************************************************************
151 **************************************************************************
152 */
153 static void arcmsr_free_srb(struct CommandControlBlock *srb);
154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
156 static int arcmsr_probe(device_t dev);
157 static int arcmsr_attach(device_t dev);
158 static int arcmsr_detach(device_t dev);
159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
161 static int arcmsr_shutdown(device_t dev);
162 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
164 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
168 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
178 static int arcmsr_resume(device_t dev);
179 static int arcmsr_suspend(device_t dev);
180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
181 static void arcmsr_polling_devmap(void *arg);
182 static void arcmsr_srb_timeout(void *arg);
183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
184 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
185 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb);
186 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
187 #ifdef ARCMSR_DEBUG1
188 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
189 #endif
190 /*
191 **************************************************************************
192 **************************************************************************
193 */
UDELAY(u_int32_t us)194 static void UDELAY(u_int32_t us) { DELAY(us); }
195 /*
196 **************************************************************************
197 **************************************************************************
198 */
199 static bus_dmamap_callback_t arcmsr_map_free_srb;
200 static bus_dmamap_callback_t arcmsr_execute_srb;
201 /*
202 **************************************************************************
203 **************************************************************************
204 */
205 static d_open_t arcmsr_open;
206 static d_close_t arcmsr_close;
207 static d_ioctl_t arcmsr_ioctl;
208
209 static device_method_t arcmsr_methods[]={
210 DEVMETHOD(device_probe, arcmsr_probe),
211 DEVMETHOD(device_attach, arcmsr_attach),
212 DEVMETHOD(device_detach, arcmsr_detach),
213 DEVMETHOD(device_shutdown, arcmsr_shutdown),
214 DEVMETHOD(device_suspend, arcmsr_suspend),
215 DEVMETHOD(device_resume, arcmsr_resume),
216 DEVMETHOD_END
217 };
218
219 static driver_t arcmsr_driver={
220 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
221 };
222
223 static devclass_t arcmsr_devclass;
224 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
225 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
226 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
227 #ifndef BUS_DMA_COHERENT
228 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */
229 #endif
230 static struct cdevsw arcmsr_cdevsw={
231 .d_version = D_VERSION,
232 .d_open = arcmsr_open, /* open */
233 .d_close = arcmsr_close, /* close */
234 .d_ioctl = arcmsr_ioctl, /* ioctl */
235 .d_name = "arcmsr", /* name */
236 };
237 /*
238 **************************************************************************
239 **************************************************************************
240 */
arcmsr_open(struct cdev * dev,int flags,int fmt,struct thread * proc)241 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
242 {
243 int unit = dev2unit(dev);
244 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
245
246 if (acb == NULL) {
247 return ENXIO;
248 }
249 return (0);
250 }
251 /*
252 **************************************************************************
253 **************************************************************************
254 */
arcmsr_close(struct cdev * dev,int flags,int fmt,struct thread * proc)255 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
256 {
257 int unit = dev2unit(dev);
258 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
259
260 if (acb == NULL) {
261 return ENXIO;
262 }
263 return 0;
264 }
265 /*
266 **************************************************************************
267 **************************************************************************
268 */
arcmsr_ioctl(struct cdev * dev,u_long ioctl_cmd,caddr_t arg,int flags,struct thread * proc)269 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
270 {
271 int unit = dev2unit(dev);
272 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
273
274 if (acb == NULL) {
275 return ENXIO;
276 }
277 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
278 }
279 /*
280 **********************************************************************
281 **********************************************************************
282 */
arcmsr_disable_allintr(struct AdapterControlBlock * acb)283 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
284 {
285 u_int32_t intmask_org = 0;
286
287 switch (acb->adapter_type) {
288 case ACB_ADAPTER_TYPE_A: {
289 /* disable all outbound interrupt */
290 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
291 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
292 }
293 break;
294 case ACB_ADAPTER_TYPE_B: {
295 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
296 /* disable all outbound interrupt */
297 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
298 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
299 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
300 }
301 break;
302 case ACB_ADAPTER_TYPE_C: {
303 /* disable all outbound interrupt */
304 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
305 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
306 }
307 break;
308 case ACB_ADAPTER_TYPE_D: {
309 /* disable all outbound interrupt */
310 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */
311 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
312 }
313 break;
314 case ACB_ADAPTER_TYPE_E:
315 case ACB_ADAPTER_TYPE_F: {
316 /* disable all outbound interrupt */
317 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
318 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
319 }
320 break;
321 }
322 return (intmask_org);
323 }
324 /*
325 **********************************************************************
326 **********************************************************************
327 */
arcmsr_enable_allintr(struct AdapterControlBlock * acb,u_int32_t intmask_org)328 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
329 {
330 u_int32_t mask;
331
332 switch (acb->adapter_type) {
333 case ACB_ADAPTER_TYPE_A: {
334 /* enable outbound Post Queue, outbound doorbell Interrupt */
335 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
336 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
337 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
338 }
339 break;
340 case ACB_ADAPTER_TYPE_B: {
341 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
342 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
343 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
344 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
345 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
346 }
347 break;
348 case ACB_ADAPTER_TYPE_C: {
349 /* enable outbound Post Queue, outbound doorbell Interrupt */
350 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
351 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
352 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
353 }
354 break;
355 case ACB_ADAPTER_TYPE_D: {
356 /* enable outbound Post Queue, outbound doorbell Interrupt */
357 mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
358 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
359 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
360 acb->outbound_int_enable = mask;
361 }
362 break;
363 case ACB_ADAPTER_TYPE_E:
364 case ACB_ADAPTER_TYPE_F: {
365 /* enable outbound Post Queue, outbound doorbell Interrupt */
366 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
367 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
368 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
369 }
370 break;
371 }
372 }
373 /*
374 **********************************************************************
375 **********************************************************************
376 */
arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock * acb)377 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
378 {
379 u_int32_t Index;
380 u_int8_t Retries = 0x00;
381
382 do {
383 for(Index=0; Index < 100; Index++) {
384 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
385 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
386 return TRUE;
387 }
388 UDELAY(10000);
389 }/*max 1 seconds*/
390 }while(Retries++ < 20);/*max 20 sec*/
391 return (FALSE);
392 }
393 /*
394 **********************************************************************
395 **********************************************************************
396 */
arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock * acb)397 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
398 {
399 u_int32_t Index;
400 u_int8_t Retries = 0x00;
401 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
402
403 do {
404 for(Index=0; Index < 100; Index++) {
405 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
406 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
407 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
408 return TRUE;
409 }
410 UDELAY(10000);
411 }/*max 1 seconds*/
412 }while(Retries++ < 20);/*max 20 sec*/
413 return (FALSE);
414 }
415 /*
416 **********************************************************************
417 **********************************************************************
418 */
arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock * acb)419 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
420 {
421 u_int32_t Index;
422 u_int8_t Retries = 0x00;
423
424 do {
425 for(Index=0; Index < 100; Index++) {
426 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
427 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
428 return TRUE;
429 }
430 UDELAY(10000);
431 }/*max 1 seconds*/
432 }while(Retries++ < 20);/*max 20 sec*/
433 return (FALSE);
434 }
435 /*
436 **********************************************************************
437 **********************************************************************
438 */
arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock * acb)439 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
440 {
441 u_int32_t Index;
442 u_int8_t Retries = 0x00;
443
444 do {
445 for(Index=0; Index < 100; Index++) {
446 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
447 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
448 return TRUE;
449 }
450 UDELAY(10000);
451 }/*max 1 seconds*/
452 }while(Retries++ < 20);/*max 20 sec*/
453 return (FALSE);
454 }
455 /*
456 **********************************************************************
457 **********************************************************************
458 */
arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock * acb)459 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
460 {
461 u_int32_t Index, read_doorbell;
462 u_int8_t Retries = 0x00;
463
464 do {
465 for(Index=0; Index < 100; Index++) {
466 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
467 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
468 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
469 acb->in_doorbell = read_doorbell;
470 return TRUE;
471 }
472 UDELAY(10000);
473 }/*max 1 seconds*/
474 }while(Retries++ < 20);/*max 20 sec*/
475 return (FALSE);
476 }
477 /*
478 ************************************************************************
479 ************************************************************************
480 */
arcmsr_flush_hba_cache(struct AdapterControlBlock * acb)481 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
482 {
483 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
484
485 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
486 do {
487 if(arcmsr_hba_wait_msgint_ready(acb)) {
488 break;
489 } else {
490 retry_count--;
491 }
492 }while(retry_count != 0);
493 }
494 /*
495 ************************************************************************
496 ************************************************************************
497 */
arcmsr_flush_hbb_cache(struct AdapterControlBlock * acb)498 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
499 {
500 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
501 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
502
503 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
504 do {
505 if(arcmsr_hbb_wait_msgint_ready(acb)) {
506 break;
507 } else {
508 retry_count--;
509 }
510 }while(retry_count != 0);
511 }
512 /*
513 ************************************************************************
514 ************************************************************************
515 */
arcmsr_flush_hbc_cache(struct AdapterControlBlock * acb)516 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
517 {
518 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
519
520 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
521 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
522 do {
523 if(arcmsr_hbc_wait_msgint_ready(acb)) {
524 break;
525 } else {
526 retry_count--;
527 }
528 }while(retry_count != 0);
529 }
530 /*
531 ************************************************************************
532 ************************************************************************
533 */
arcmsr_flush_hbd_cache(struct AdapterControlBlock * acb)534 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
535 {
536 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
537
538 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
539 do {
540 if(arcmsr_hbd_wait_msgint_ready(acb)) {
541 break;
542 } else {
543 retry_count--;
544 }
545 }while(retry_count != 0);
546 }
547 /*
548 ************************************************************************
549 ************************************************************************
550 */
arcmsr_flush_hbe_cache(struct AdapterControlBlock * acb)551 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
552 {
553 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
554
555 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
556 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
557 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
558 do {
559 if(arcmsr_hbe_wait_msgint_ready(acb)) {
560 break;
561 } else {
562 retry_count--;
563 }
564 }while(retry_count != 0);
565 }
566 /*
567 ************************************************************************
568 ************************************************************************
569 */
arcmsr_flush_adapter_cache(struct AdapterControlBlock * acb)570 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
571 {
572 switch (acb->adapter_type) {
573 case ACB_ADAPTER_TYPE_A: {
574 arcmsr_flush_hba_cache(acb);
575 }
576 break;
577 case ACB_ADAPTER_TYPE_B: {
578 arcmsr_flush_hbb_cache(acb);
579 }
580 break;
581 case ACB_ADAPTER_TYPE_C: {
582 arcmsr_flush_hbc_cache(acb);
583 }
584 break;
585 case ACB_ADAPTER_TYPE_D: {
586 arcmsr_flush_hbd_cache(acb);
587 }
588 break;
589 case ACB_ADAPTER_TYPE_E:
590 case ACB_ADAPTER_TYPE_F: {
591 arcmsr_flush_hbe_cache(acb);
592 }
593 break;
594 }
595 }
596 /*
597 *******************************************************************************
598 *******************************************************************************
599 */
arcmsr_suspend(device_t dev)600 static int arcmsr_suspend(device_t dev)
601 {
602 struct AdapterControlBlock *acb = device_get_softc(dev);
603
604 /* flush controller */
605 arcmsr_iop_parking(acb);
606 /* disable all outbound interrupt */
607 arcmsr_disable_allintr(acb);
608 return(0);
609 }
610 /*
611 *******************************************************************************
612 *******************************************************************************
613 */
arcmsr_resume(device_t dev)614 static int arcmsr_resume(device_t dev)
615 {
616 struct AdapterControlBlock *acb = device_get_softc(dev);
617
618 arcmsr_iop_init(acb);
619 return(0);
620 }
621 /*
622 *********************************************************************************
623 *********************************************************************************
624 */
arcmsr_async(void * cb_arg,u_int32_t code,struct cam_path * path,void * arg)625 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
626 {
627 struct AdapterControlBlock *acb;
628 u_int8_t target_id, target_lun;
629 struct cam_sim *sim;
630
631 sim = (struct cam_sim *) cb_arg;
632 acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
633 switch (code) {
634 case AC_LOST_DEVICE:
635 target_id = xpt_path_target_id(path);
636 target_lun = xpt_path_lun_id(path);
637 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
638 break;
639 }
640 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
641 break;
642 default:
643 break;
644 }
645 }
646 /*
647 **********************************************************************
648 **********************************************************************
649 */
arcmsr_report_sense_info(struct CommandControlBlock * srb)650 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
651 {
652 union ccb *pccb = srb->pccb;
653
654 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
655 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
656 if(pccb->csio.sense_len) {
657 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
658 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
659 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
660 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
661 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
662 }
663 }
664 /*
665 *********************************************************************
666 *********************************************************************
667 */
arcmsr_abort_hba_allcmd(struct AdapterControlBlock * acb)668 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
669 {
670 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
671 if(!arcmsr_hba_wait_msgint_ready(acb)) {
672 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
673 }
674 }
675 /*
676 *********************************************************************
677 *********************************************************************
678 */
arcmsr_abort_hbb_allcmd(struct AdapterControlBlock * acb)679 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
680 {
681 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
682 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
683 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
684 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
685 }
686 }
687 /*
688 *********************************************************************
689 *********************************************************************
690 */
arcmsr_abort_hbc_allcmd(struct AdapterControlBlock * acb)691 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
692 {
693 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
694 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
695 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
696 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
697 }
698 }
699 /*
700 *********************************************************************
701 *********************************************************************
702 */
arcmsr_abort_hbd_allcmd(struct AdapterControlBlock * acb)703 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
704 {
705 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
706 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
707 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
708 }
709 }
710 /*
711 *********************************************************************
712 *********************************************************************
713 */
arcmsr_abort_hbe_allcmd(struct AdapterControlBlock * acb)714 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
715 {
716 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
717 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
718 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
719 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
720 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
721 }
722 }
723 /*
724 *********************************************************************
725 *********************************************************************
726 */
arcmsr_abort_allcmd(struct AdapterControlBlock * acb)727 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
728 {
729 switch (acb->adapter_type) {
730 case ACB_ADAPTER_TYPE_A: {
731 arcmsr_abort_hba_allcmd(acb);
732 }
733 break;
734 case ACB_ADAPTER_TYPE_B: {
735 arcmsr_abort_hbb_allcmd(acb);
736 }
737 break;
738 case ACB_ADAPTER_TYPE_C: {
739 arcmsr_abort_hbc_allcmd(acb);
740 }
741 break;
742 case ACB_ADAPTER_TYPE_D: {
743 arcmsr_abort_hbd_allcmd(acb);
744 }
745 break;
746 case ACB_ADAPTER_TYPE_E:
747 case ACB_ADAPTER_TYPE_F: {
748 arcmsr_abort_hbe_allcmd(acb);
749 }
750 break;
751 }
752 }
753 /*
754 **********************************************************************
755 **********************************************************************
756 */
arcmsr_srb_complete(struct CommandControlBlock * srb,int stand_flag)757 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
758 {
759 struct AdapterControlBlock *acb = srb->acb;
760 union ccb *pccb = srb->pccb;
761
762 if(srb->srb_flags & SRB_FLAG_TIMER_START)
763 callout_stop(&srb->ccb_callout);
764 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
765 bus_dmasync_op_t op;
766
767 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
768 op = BUS_DMASYNC_POSTREAD;
769 } else {
770 op = BUS_DMASYNC_POSTWRITE;
771 }
772 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
773 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
774 }
775 if(stand_flag == 1) {
776 atomic_subtract_int(&acb->srboutstandingcount, 1);
777 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
778 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
779 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
780 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
781 }
782 }
783 if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
784 arcmsr_free_srb(srb);
785 acb->pktReturnCount++;
786 xpt_done(pccb);
787 }
788 /*
789 **************************************************************************
790 **************************************************************************
791 */
arcmsr_report_srb_state(struct AdapterControlBlock * acb,struct CommandControlBlock * srb,u_int16_t error)792 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
793 {
794 int target, lun;
795
796 target = srb->pccb->ccb_h.target_id;
797 lun = srb->pccb->ccb_h.target_lun;
798 if(error == FALSE) {
799 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
800 acb->devstate[target][lun] = ARECA_RAID_GOOD;
801 }
802 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
803 arcmsr_srb_complete(srb, 1);
804 } else {
805 switch(srb->arcmsr_cdb.DeviceStatus) {
806 case ARCMSR_DEV_SELECT_TIMEOUT: {
807 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
808 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
809 }
810 acb->devstate[target][lun] = ARECA_RAID_GONE;
811 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
812 arcmsr_srb_complete(srb, 1);
813 }
814 break;
815 case ARCMSR_DEV_ABORTED:
816 case ARCMSR_DEV_INIT_FAIL: {
817 acb->devstate[target][lun] = ARECA_RAID_GONE;
818 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
819 arcmsr_srb_complete(srb, 1);
820 }
821 break;
822 case SCSISTAT_CHECK_CONDITION: {
823 acb->devstate[target][lun] = ARECA_RAID_GOOD;
824 arcmsr_report_sense_info(srb);
825 arcmsr_srb_complete(srb, 1);
826 }
827 break;
828 default:
829 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
830 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
831 acb->devstate[target][lun] = ARECA_RAID_GONE;
832 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
833 /*unknown error or crc error just for retry*/
834 arcmsr_srb_complete(srb, 1);
835 break;
836 }
837 }
838 }
839 /*
840 **************************************************************************
841 **************************************************************************
842 */
arcmsr_drain_donequeue(struct AdapterControlBlock * acb,u_int32_t flag_srb,u_int16_t error)843 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
844 {
845 struct CommandControlBlock *srb;
846
847 /* check if command done with no error*/
848 switch (acb->adapter_type) {
849 case ACB_ADAPTER_TYPE_A:
850 case ACB_ADAPTER_TYPE_B:
851 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
852 break;
853 case ACB_ADAPTER_TYPE_C:
854 case ACB_ADAPTER_TYPE_D:
855 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
856 break;
857 case ACB_ADAPTER_TYPE_E:
858 case ACB_ADAPTER_TYPE_F:
859 srb = acb->psrb_pool[flag_srb];
860 break;
861 default:
862 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
863 break;
864 }
865 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
866 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
867 arcmsr_free_srb(srb);
868 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
869 return;
870 }
871 printf("arcmsr%d: return srb has been completed\n"
872 "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
873 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
874 return;
875 }
876 arcmsr_report_srb_state(acb, srb, error);
877 }
878 /*
879 **************************************************************************
880 **************************************************************************
881 */
arcmsr_srb_timeout(void * arg)882 static void arcmsr_srb_timeout(void *arg)
883 {
884 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
885 struct AdapterControlBlock *acb;
886 int target, lun;
887 u_int8_t cmd;
888
889 target = srb->pccb->ccb_h.target_id;
890 lun = srb->pccb->ccb_h.target_lun;
891 acb = srb->acb;
892 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
893 if(srb->srb_state == ARCMSR_SRB_START)
894 {
895 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
896 srb->srb_state = ARCMSR_SRB_TIMEOUT;
897 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
898 arcmsr_srb_complete(srb, 1);
899 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
900 acb->pci_unit, target, lun, cmd, srb);
901 }
902 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
903 #ifdef ARCMSR_DEBUG1
904 arcmsr_dump_data(acb);
905 #endif
906 }
907
908 /*
909 **********************************************************************
910 **********************************************************************
911 */
arcmsr_done4abort_postqueue(struct AdapterControlBlock * acb)912 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
913 {
914 int i=0;
915 u_int32_t flag_srb;
916 u_int16_t error;
917
918 switch (acb->adapter_type) {
919 case ACB_ADAPTER_TYPE_A: {
920 u_int32_t outbound_intstatus;
921
922 /*clear and abort all outbound posted Q*/
923 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
924 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
925 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
926 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
927 arcmsr_drain_donequeue(acb, flag_srb, error);
928 }
929 }
930 break;
931 case ACB_ADAPTER_TYPE_B: {
932 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
933
934 /*clear all outbound posted Q*/
935 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
936 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
937 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
938 phbbmu->done_qbuffer[i] = 0;
939 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
940 arcmsr_drain_donequeue(acb, flag_srb, error);
941 }
942 phbbmu->post_qbuffer[i] = 0;
943 }/*drain reply FIFO*/
944 phbbmu->doneq_index = 0;
945 phbbmu->postq_index = 0;
946 }
947 break;
948 case ACB_ADAPTER_TYPE_C: {
949 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
950 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
951 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
952 arcmsr_drain_donequeue(acb, flag_srb, error);
953 }
954 }
955 break;
956 case ACB_ADAPTER_TYPE_D:
957 arcmsr_hbd_postqueue_isr(acb);
958 break;
959 case ACB_ADAPTER_TYPE_E:
960 arcmsr_hbe_postqueue_isr(acb);
961 break;
962 case ACB_ADAPTER_TYPE_F:
963 arcmsr_hbf_postqueue_isr(acb);
964 break;
965 }
966 }
967 /*
968 ****************************************************************************
969 ****************************************************************************
970 */
arcmsr_iop_reset(struct AdapterControlBlock * acb)971 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
972 {
973 struct CommandControlBlock *srb;
974 u_int32_t intmask_org;
975 u_int32_t i=0;
976
977 if(acb->srboutstandingcount>0) {
978 /* disable all outbound interrupt */
979 intmask_org = arcmsr_disable_allintr(acb);
980 /*clear and abort all outbound posted Q*/
981 arcmsr_done4abort_postqueue(acb);
982 /* talk to iop 331 outstanding command aborted*/
983 arcmsr_abort_allcmd(acb);
984 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
985 srb = acb->psrb_pool[i];
986 if(srb->srb_state == ARCMSR_SRB_START) {
987 srb->srb_state = ARCMSR_SRB_ABORTED;
988 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
989 arcmsr_srb_complete(srb, 1);
990 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
991 , acb->pci_unit, srb->pccb->ccb_h.target_id
992 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
993 }
994 }
995 /* enable all outbound interrupt */
996 arcmsr_enable_allintr(acb, intmask_org);
997 }
998 acb->srboutstandingcount = 0;
999 acb->workingsrb_doneindex = 0;
1000 acb->workingsrb_startindex = 0;
1001 acb->pktRequestCount = 0;
1002 acb->pktReturnCount = 0;
1003 }
1004 /*
1005 **********************************************************************
1006 **********************************************************************
1007 */
arcmsr_build_srb(struct CommandControlBlock * srb,bus_dma_segment_t * dm_segs,u_int32_t nseg)1008 static void arcmsr_build_srb(struct CommandControlBlock *srb,
1009 bus_dma_segment_t *dm_segs, u_int32_t nseg)
1010 {
1011 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
1012 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
1013 u_int32_t address_lo, address_hi;
1014 union ccb *pccb = srb->pccb;
1015 struct ccb_scsiio *pcsio = &pccb->csio;
1016 u_int32_t arccdbsize = 0x30;
1017
1018 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1019 arcmsr_cdb->Bus = 0;
1020 arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
1021 arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
1022 arcmsr_cdb->Function = 1;
1023 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1024 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1025 if(nseg != 0) {
1026 struct AdapterControlBlock *acb = srb->acb;
1027 bus_dmasync_op_t op;
1028 u_int32_t length, i, cdb_sgcount = 0;
1029
1030 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1031 op = BUS_DMASYNC_PREREAD;
1032 } else {
1033 op = BUS_DMASYNC_PREWRITE;
1034 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1035 srb->srb_flags |= SRB_FLAG_WRITE;
1036 }
1037 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1038 for(i=0; i < nseg; i++) {
1039 /* Get the physical address of the current data pointer */
1040 length = arcmsr_htole32(dm_segs[i].ds_len);
1041 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1042 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1043 if(address_hi == 0) {
1044 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1045 pdma_sg->address = address_lo;
1046 pdma_sg->length = length;
1047 psge += sizeof(struct SG32ENTRY);
1048 arccdbsize += sizeof(struct SG32ENTRY);
1049 } else {
1050 u_int32_t sg64s_size = 0, tmplength = length;
1051
1052 while(1) {
1053 u_int64_t span4G, length0;
1054 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1055
1056 span4G = (u_int64_t)address_lo + tmplength;
1057 pdma_sg->addresshigh = address_hi;
1058 pdma_sg->address = address_lo;
1059 if(span4G > 0x100000000) {
1060 /*see if cross 4G boundary*/
1061 length0 = 0x100000000-address_lo;
1062 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1063 address_hi = address_hi+1;
1064 address_lo = 0;
1065 tmplength = tmplength - (u_int32_t)length0;
1066 sg64s_size += sizeof(struct SG64ENTRY);
1067 psge += sizeof(struct SG64ENTRY);
1068 cdb_sgcount++;
1069 } else {
1070 pdma_sg->length = tmplength | IS_SG64_ADDR;
1071 sg64s_size += sizeof(struct SG64ENTRY);
1072 psge += sizeof(struct SG64ENTRY);
1073 break;
1074 }
1075 }
1076 arccdbsize += sg64s_size;
1077 }
1078 cdb_sgcount++;
1079 }
1080 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1081 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1082 if( arccdbsize > 256) {
1083 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1084 }
1085 } else {
1086 arcmsr_cdb->DataLength = 0;
1087 }
1088 srb->arc_cdb_size = arccdbsize;
1089 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1090 }
1091 /*
1092 **************************************************************************
1093 **************************************************************************
1094 */
arcmsr_post_srb(struct AdapterControlBlock * acb,struct CommandControlBlock * srb)1095 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1096 {
1097 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1098 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1099
1100 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1101 atomic_add_int(&acb->srboutstandingcount, 1);
1102 srb->srb_state = ARCMSR_SRB_START;
1103
1104 switch (acb->adapter_type) {
1105 case ACB_ADAPTER_TYPE_A: {
1106 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1107 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1108 } else {
1109 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1110 }
1111 }
1112 break;
1113 case ACB_ADAPTER_TYPE_B: {
1114 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1115 int ending_index, index;
1116
1117 index = phbbmu->postq_index;
1118 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1119 phbbmu->post_qbuffer[ending_index] = 0;
1120 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1121 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1122 } else {
1123 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1124 }
1125 index++;
1126 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
1127 phbbmu->postq_index = index;
1128 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1129 }
1130 break;
1131 case ACB_ADAPTER_TYPE_C: {
1132 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1133
1134 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1135 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1136 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1137 if(cdb_phyaddr_hi32)
1138 {
1139 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1140 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1141 }
1142 else
1143 {
1144 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1145 }
1146 }
1147 break;
1148 case ACB_ADAPTER_TYPE_D: {
1149 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1150 u_int16_t index_stripped;
1151 u_int16_t postq_index;
1152 struct InBound_SRB *pinbound_srb;
1153
1154 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1155 postq_index = phbdmu->postq_index;
1156 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1157 pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1158 pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1159 pinbound_srb->length = srb->arc_cdb_size >> 2;
1160 arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1161 if (postq_index & 0x4000) {
1162 index_stripped = postq_index & 0xFF;
1163 index_stripped += 1;
1164 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1165 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1166 } else {
1167 index_stripped = postq_index;
1168 index_stripped += 1;
1169 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1170 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1171 }
1172 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1173 ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1174 }
1175 break;
1176 case ACB_ADAPTER_TYPE_E: {
1177 u_int32_t ccb_post_stamp, arc_cdb_size;
1178
1179 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1180 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1181 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1182 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1183 }
1184 break;
1185 case ACB_ADAPTER_TYPE_F: {
1186 u_int32_t ccb_post_stamp, arc_cdb_size;
1187
1188 if (srb->arc_cdb_size <= 0x300)
1189 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1;
1190 else {
1191 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2;
1192 if (arc_cdb_size > 0xF)
1193 arc_cdb_size = 0xF;
1194 arc_cdb_size = (arc_cdb_size << 1) | 1;
1195 }
1196 ccb_post_stamp = (srb->smid | arc_cdb_size);
1197 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);
1198 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1199 }
1200 break;
1201 }
1202 }
1203 /*
1204 ************************************************************************
1205 ************************************************************************
1206 */
arcmsr_get_iop_rqbuffer(struct AdapterControlBlock * acb)1207 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1208 {
1209 struct QBUFFER *qbuffer=NULL;
1210
1211 switch (acb->adapter_type) {
1212 case ACB_ADAPTER_TYPE_A: {
1213 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1214
1215 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1216 }
1217 break;
1218 case ACB_ADAPTER_TYPE_B: {
1219 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1220
1221 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1222 }
1223 break;
1224 case ACB_ADAPTER_TYPE_C: {
1225 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1226
1227 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1228 }
1229 break;
1230 case ACB_ADAPTER_TYPE_D: {
1231 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1232
1233 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1234 }
1235 break;
1236 case ACB_ADAPTER_TYPE_E: {
1237 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1238
1239 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1240 }
1241 break;
1242 case ACB_ADAPTER_TYPE_F:
1243 qbuffer = (struct QBUFFER *)acb->message_rbuffer;
1244 break;
1245 }
1246 return(qbuffer);
1247 }
1248 /*
1249 ************************************************************************
1250 ************************************************************************
1251 */
arcmsr_get_iop_wqbuffer(struct AdapterControlBlock * acb)1252 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1253 {
1254 struct QBUFFER *qbuffer = NULL;
1255
1256 switch (acb->adapter_type) {
1257 case ACB_ADAPTER_TYPE_A: {
1258 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1259
1260 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1261 }
1262 break;
1263 case ACB_ADAPTER_TYPE_B: {
1264 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1265
1266 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1267 }
1268 break;
1269 case ACB_ADAPTER_TYPE_C: {
1270 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1271
1272 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1273 }
1274 break;
1275 case ACB_ADAPTER_TYPE_D: {
1276 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1277
1278 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1279 }
1280 break;
1281 case ACB_ADAPTER_TYPE_E: {
1282 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1283
1284 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1285 }
1286 break;
1287 case ACB_ADAPTER_TYPE_F:
1288 qbuffer = (struct QBUFFER *)acb->message_wbuffer;
1289 break;
1290 }
1291 return(qbuffer);
1292 }
1293 /*
1294 **************************************************************************
1295 **************************************************************************
1296 */
arcmsr_iop_message_read(struct AdapterControlBlock * acb)1297 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1298 {
1299 switch (acb->adapter_type) {
1300 case ACB_ADAPTER_TYPE_A: {
1301 /* let IOP know data has been read */
1302 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1303 }
1304 break;
1305 case ACB_ADAPTER_TYPE_B: {
1306 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1307 /* let IOP know data has been read */
1308 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1309 }
1310 break;
1311 case ACB_ADAPTER_TYPE_C: {
1312 /* let IOP know data has been read */
1313 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1314 }
1315 break;
1316 case ACB_ADAPTER_TYPE_D: {
1317 /* let IOP know data has been read */
1318 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1319 }
1320 break;
1321 case ACB_ADAPTER_TYPE_E:
1322 case ACB_ADAPTER_TYPE_F: {
1323 /* let IOP know data has been read */
1324 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1325 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1326 }
1327 break;
1328 }
1329 }
1330 /*
1331 **************************************************************************
1332 **************************************************************************
1333 */
arcmsr_iop_message_wrote(struct AdapterControlBlock * acb)1334 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1335 {
1336 switch (acb->adapter_type) {
1337 case ACB_ADAPTER_TYPE_A: {
1338 /*
1339 ** push inbound doorbell tell iop, driver data write ok
1340 ** and wait reply on next hwinterrupt for next Qbuffer post
1341 */
1342 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1343 }
1344 break;
1345 case ACB_ADAPTER_TYPE_B: {
1346 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1347 /*
1348 ** push inbound doorbell tell iop, driver data write ok
1349 ** and wait reply on next hwinterrupt for next Qbuffer post
1350 */
1351 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1352 }
1353 break;
1354 case ACB_ADAPTER_TYPE_C: {
1355 /*
1356 ** push inbound doorbell tell iop, driver data write ok
1357 ** and wait reply on next hwinterrupt for next Qbuffer post
1358 */
1359 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1360 }
1361 break;
1362 case ACB_ADAPTER_TYPE_D: {
1363 /*
1364 ** push inbound doorbell tell iop, driver data write ok
1365 ** and wait reply on next hwinterrupt for next Qbuffer post
1366 */
1367 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1368 }
1369 break;
1370 case ACB_ADAPTER_TYPE_E:
1371 case ACB_ADAPTER_TYPE_F: {
1372 /*
1373 ** push inbound doorbell tell iop, driver data write ok
1374 ** and wait reply on next hwinterrupt for next Qbuffer post
1375 */
1376 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1377 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1378 }
1379 break;
1380 }
1381 }
1382 /*
1383 ************************************************************************
1384 ************************************************************************
1385 */
arcmsr_stop_hba_bgrb(struct AdapterControlBlock * acb)1386 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1387 {
1388 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1389 CHIP_REG_WRITE32(HBA_MessageUnit,
1390 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1391 if(!arcmsr_hba_wait_msgint_ready(acb)) {
1392 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1393 , acb->pci_unit);
1394 }
1395 }
1396 /*
1397 ************************************************************************
1398 ************************************************************************
1399 */
arcmsr_stop_hbb_bgrb(struct AdapterControlBlock * acb)1400 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1401 {
1402 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1403 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1404 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1405 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1406 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1407 , acb->pci_unit);
1408 }
1409 }
1410 /*
1411 ************************************************************************
1412 ************************************************************************
1413 */
arcmsr_stop_hbc_bgrb(struct AdapterControlBlock * acb)1414 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1415 {
1416 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1417 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1418 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1419 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1420 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1421 }
1422 }
1423 /*
1424 ************************************************************************
1425 ************************************************************************
1426 */
arcmsr_stop_hbd_bgrb(struct AdapterControlBlock * acb)1427 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1428 {
1429 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1430 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1431 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1432 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1433 }
1434 }
1435 /*
1436 ************************************************************************
1437 ************************************************************************
1438 */
arcmsr_stop_hbe_bgrb(struct AdapterControlBlock * acb)1439 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
1440 {
1441 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1442 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1443 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1444 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1445 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
1446 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1447 }
1448 }
1449 /*
1450 ************************************************************************
1451 ************************************************************************
1452 */
arcmsr_stop_adapter_bgrb(struct AdapterControlBlock * acb)1453 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1454 {
1455 switch (acb->adapter_type) {
1456 case ACB_ADAPTER_TYPE_A: {
1457 arcmsr_stop_hba_bgrb(acb);
1458 }
1459 break;
1460 case ACB_ADAPTER_TYPE_B: {
1461 arcmsr_stop_hbb_bgrb(acb);
1462 }
1463 break;
1464 case ACB_ADAPTER_TYPE_C: {
1465 arcmsr_stop_hbc_bgrb(acb);
1466 }
1467 break;
1468 case ACB_ADAPTER_TYPE_D: {
1469 arcmsr_stop_hbd_bgrb(acb);
1470 }
1471 break;
1472 case ACB_ADAPTER_TYPE_E:
1473 case ACB_ADAPTER_TYPE_F: {
1474 arcmsr_stop_hbe_bgrb(acb);
1475 }
1476 break;
1477 }
1478 }
1479 /*
1480 ************************************************************************
1481 ************************************************************************
1482 */
arcmsr_poll(struct cam_sim * psim)1483 static void arcmsr_poll(struct cam_sim *psim)
1484 {
1485 struct AdapterControlBlock *acb;
1486 int mutex;
1487
1488 acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1489 mutex = mtx_owned(&acb->isr_lock);
1490 if( mutex == 0 )
1491 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1492 arcmsr_interrupt(acb);
1493 if( mutex == 0 )
1494 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1495 }
1496 /*
1497 **************************************************************************
1498 **************************************************************************
1499 */
arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock * acb,struct QBUFFER * prbuffer)1500 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1501 struct QBUFFER *prbuffer) {
1502 u_int8_t *pQbuffer;
1503 u_int8_t *buf1 = NULL;
1504 u_int32_t *iop_data, *buf2 = NULL;
1505 u_int32_t iop_len, data_len;
1506
1507 iop_data = (u_int32_t *)prbuffer->data;
1508 iop_len = (u_int32_t)prbuffer->data_len;
1509 if ( iop_len > 0 )
1510 {
1511 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1512 buf2 = (u_int32_t *)buf1;
1513 if( buf1 == NULL)
1514 return (0);
1515 data_len = iop_len;
1516 while(data_len >= 4)
1517 {
1518 *buf2++ = *iop_data++;
1519 data_len -= 4;
1520 }
1521 if(data_len)
1522 *buf2 = *iop_data;
1523 buf2 = (u_int32_t *)buf1;
1524 }
1525 while (iop_len > 0) {
1526 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1527 *pQbuffer = *buf1;
1528 acb->rqbuf_lastindex++;
1529 /* if last, index number set it to 0 */
1530 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1531 buf1++;
1532 iop_len--;
1533 }
1534 if(buf2)
1535 free( (u_int8_t *)buf2, M_DEVBUF);
1536 /* let IOP know data has been read */
1537 arcmsr_iop_message_read(acb);
1538 return (1);
1539 }
1540 /*
1541 **************************************************************************
1542 **************************************************************************
1543 */
arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock * acb,struct QBUFFER * prbuffer)1544 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1545 struct QBUFFER *prbuffer) {
1546 u_int8_t *pQbuffer;
1547 u_int8_t *iop_data;
1548 u_int32_t iop_len;
1549
1550 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1551 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1552 }
1553 iop_data = (u_int8_t *)prbuffer->data;
1554 iop_len = (u_int32_t)prbuffer->data_len;
1555 while (iop_len > 0) {
1556 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1557 *pQbuffer = *iop_data;
1558 acb->rqbuf_lastindex++;
1559 /* if last, index number set it to 0 */
1560 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1561 iop_data++;
1562 iop_len--;
1563 }
1564 /* let IOP know data has been read */
1565 arcmsr_iop_message_read(acb);
1566 return (1);
1567 }
1568 /*
1569 **************************************************************************
1570 **************************************************************************
1571 */
arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock * acb)1572 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1573 {
1574 struct QBUFFER *prbuffer;
1575 int my_empty_len;
1576
1577 /*check this iop data if overflow my rqbuffer*/
1578 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1579 prbuffer = arcmsr_get_iop_rqbuffer(acb);
1580 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1581 (ARCMSR_MAX_QBUFFER-1);
1582 if(my_empty_len >= prbuffer->data_len) {
1583 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1584 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1585 } else {
1586 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1587 }
1588 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1589 }
1590 /*
1591 **********************************************************************
1592 **********************************************************************
1593 */
arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock * acb)1594 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1595 {
1596 u_int8_t *pQbuffer;
1597 struct QBUFFER *pwbuffer;
1598 u_int8_t *buf1 = NULL;
1599 u_int32_t *iop_data, *buf2 = NULL;
1600 u_int32_t allxfer_len = 0, data_len;
1601
1602 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1603 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1604 buf2 = (u_int32_t *)buf1;
1605 if( buf1 == NULL)
1606 return;
1607
1608 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1609 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1610 iop_data = (u_int32_t *)pwbuffer->data;
1611 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1612 && (allxfer_len < 124)) {
1613 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1614 *buf1 = *pQbuffer;
1615 acb->wqbuf_firstindex++;
1616 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1617 buf1++;
1618 allxfer_len++;
1619 }
1620 pwbuffer->data_len = allxfer_len;
1621 data_len = allxfer_len;
1622 buf1 = (u_int8_t *)buf2;
1623 while(data_len >= 4)
1624 {
1625 *iop_data++ = *buf2++;
1626 data_len -= 4;
1627 }
1628 if(data_len)
1629 *iop_data = *buf2;
1630 free( buf1, M_DEVBUF);
1631 arcmsr_iop_message_wrote(acb);
1632 }
1633 }
1634 /*
1635 **********************************************************************
1636 **********************************************************************
1637 */
arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock * acb)1638 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1639 {
1640 u_int8_t *pQbuffer;
1641 struct QBUFFER *pwbuffer;
1642 u_int8_t *iop_data;
1643 int32_t allxfer_len=0;
1644
1645 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1646 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1647 return;
1648 }
1649 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1650 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1651 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1652 iop_data = (u_int8_t *)pwbuffer->data;
1653 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1654 && (allxfer_len < 124)) {
1655 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1656 *iop_data = *pQbuffer;
1657 acb->wqbuf_firstindex++;
1658 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1659 iop_data++;
1660 allxfer_len++;
1661 }
1662 pwbuffer->data_len = allxfer_len;
1663 arcmsr_iop_message_wrote(acb);
1664 }
1665 }
1666 /*
1667 **************************************************************************
1668 **************************************************************************
1669 */
arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock * acb)1670 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1671 {
1672 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1673 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1674 /*
1675 *****************************************************************
1676 ** check if there are any mail packages from user space program
1677 ** in my post bag, now is the time to send them into Areca's firmware
1678 *****************************************************************
1679 */
1680 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1681 arcmsr_Write_data_2iop_wqbuffer(acb);
1682 }
1683 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1684 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1685 }
1686 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1687 }
1688 /*
1689 **************************************************************************
1690 **************************************************************************
1691 */
arcmsr_rescanLun_cb(struct cam_periph * periph,union ccb * ccb)1692 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1693 {
1694 /*
1695 if (ccb->ccb_h.status != CAM_REQ_CMP)
1696 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1697 "failure status=%x\n", ccb->ccb_h.target_id,
1698 ccb->ccb_h.target_lun, ccb->ccb_h.status);
1699 else
1700 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1701 */
1702 xpt_free_path(ccb->ccb_h.path);
1703 xpt_free_ccb(ccb);
1704 }
1705
arcmsr_rescan_lun(struct AdapterControlBlock * acb,int target,int lun)1706 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1707 {
1708 struct cam_path *path;
1709 union ccb *ccb;
1710
1711 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1712 return;
1713 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1714 {
1715 xpt_free_ccb(ccb);
1716 return;
1717 }
1718 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1719 xpt_setup_ccb(&ccb->ccb_h, path, 5);
1720 ccb->ccb_h.func_code = XPT_SCAN_LUN;
1721 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1722 ccb->crcn.flags = CAM_FLAG_NONE;
1723 xpt_action(ccb);
1724 }
1725
arcmsr_abort_dr_ccbs(struct AdapterControlBlock * acb,int target,int lun)1726 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1727 {
1728 struct CommandControlBlock *srb;
1729 u_int32_t intmask_org;
1730 int i;
1731
1732 /* disable all outbound interrupts */
1733 intmask_org = arcmsr_disable_allintr(acb);
1734 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1735 {
1736 srb = acb->psrb_pool[i];
1737 if (srb->srb_state == ARCMSR_SRB_START)
1738 {
1739 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1740 {
1741 srb->srb_state = ARCMSR_SRB_ABORTED;
1742 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1743 arcmsr_srb_complete(srb, 1);
1744 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1745 }
1746 }
1747 }
1748 /* enable outbound Post Queue, outbound doorbell Interrupt */
1749 arcmsr_enable_allintr(acb, intmask_org);
1750 }
1751 /*
1752 **************************************************************************
1753 **************************************************************************
1754 */
arcmsr_dr_handle(struct AdapterControlBlock * acb)1755 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1756 u_int32_t devicemap;
1757 u_int32_t target, lun;
1758 u_int32_t deviceMapCurrent[4]={0};
1759 u_int8_t *pDevMap;
1760
1761 switch (acb->adapter_type) {
1762 case ACB_ADAPTER_TYPE_A:
1763 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1764 for (target = 0; target < 4; target++)
1765 {
1766 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1767 devicemap += 4;
1768 }
1769 break;
1770
1771 case ACB_ADAPTER_TYPE_B:
1772 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1773 for (target = 0; target < 4; target++)
1774 {
1775 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap);
1776 devicemap += 4;
1777 }
1778 break;
1779
1780 case ACB_ADAPTER_TYPE_C:
1781 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1782 for (target = 0; target < 4; target++)
1783 {
1784 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1785 devicemap += 4;
1786 }
1787 break;
1788 case ACB_ADAPTER_TYPE_D:
1789 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1790 for (target = 0; target < 4; target++)
1791 {
1792 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1793 devicemap += 4;
1794 }
1795 break;
1796 case ACB_ADAPTER_TYPE_E:
1797 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1798 for (target = 0; target < 4; target++)
1799 {
1800 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1801 devicemap += 4;
1802 }
1803 break;
1804 case ACB_ADAPTER_TYPE_F:
1805 devicemap = ARCMSR_FW_DEVMAP_OFFSET;
1806 for (target = 0; target < 4; target++)
1807 {
1808 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap];
1809 devicemap += 1;
1810 }
1811 break;
1812 }
1813
1814 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1815 {
1816 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1817 }
1818 /*
1819 ** adapter posted CONFIG message
1820 ** copy the new map, note if there are differences with the current map
1821 */
1822 pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1823 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1824 {
1825 if (*pDevMap != acb->device_map[target])
1826 {
1827 u_int8_t difference, bit_check;
1828
1829 difference = *pDevMap ^ acb->device_map[target];
1830 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1831 {
1832 bit_check = (1 << lun); /*check bit from 0....31*/
1833 if(difference & bit_check)
1834 {
1835 if(acb->device_map[target] & bit_check)
1836 {/* unit departed */
1837 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1838 arcmsr_abort_dr_ccbs(acb, target, lun);
1839 arcmsr_rescan_lun(acb, target, lun);
1840 acb->devstate[target][lun] = ARECA_RAID_GONE;
1841 }
1842 else
1843 {/* unit arrived */
1844 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1845 arcmsr_rescan_lun(acb, target, lun);
1846 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1847 }
1848 }
1849 }
1850 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1851 acb->device_map[target] = *pDevMap;
1852 }
1853 pDevMap++;
1854 }
1855 }
1856 /*
1857 **************************************************************************
1858 **************************************************************************
1859 */
arcmsr_hba_message_isr(struct AdapterControlBlock * acb)1860 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1861 u_int32_t outbound_message;
1862
1863 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1864 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1865 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1866 arcmsr_dr_handle( acb );
1867 }
1868 /*
1869 **************************************************************************
1870 **************************************************************************
1871 */
arcmsr_hbb_message_isr(struct AdapterControlBlock * acb)1872 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1873 u_int32_t outbound_message;
1874 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1875
1876 /* clear interrupts */
1877 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1878 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1879 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1880 arcmsr_dr_handle( acb );
1881 }
1882 /*
1883 **************************************************************************
1884 **************************************************************************
1885 */
arcmsr_hbc_message_isr(struct AdapterControlBlock * acb)1886 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1887 u_int32_t outbound_message;
1888
1889 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1890 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1891 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1892 arcmsr_dr_handle( acb );
1893 }
1894 /*
1895 **************************************************************************
1896 **************************************************************************
1897 */
arcmsr_hbd_message_isr(struct AdapterControlBlock * acb)1898 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1899 u_int32_t outbound_message;
1900
1901 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1902 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1903 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1904 arcmsr_dr_handle( acb );
1905 }
1906 /*
1907 **************************************************************************
1908 **************************************************************************
1909 */
arcmsr_hbe_message_isr(struct AdapterControlBlock * acb)1910 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
1911 u_int32_t outbound_message;
1912
1913 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
1914 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
1915 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
1916 else
1917 outbound_message = acb->msgcode_rwbuffer[0];
1918 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1919 arcmsr_dr_handle( acb );
1920 }
1921 /*
1922 **************************************************************************
1923 **************************************************************************
1924 */
arcmsr_hba_doorbell_isr(struct AdapterControlBlock * acb)1925 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1926 {
1927 u_int32_t doorbell_status;
1928
1929 /*
1930 *******************************************************************
1931 ** Maybe here we need to check wrqbuffer_lock is lock or not
1932 ** DOORBELL: din! don!
1933 ** check if there are any mail need to pack from firmware
1934 *******************************************************************
1935 */
1936 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1937 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1938 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1939 arcmsr_iop2drv_data_wrote_handle(acb);
1940 }
1941 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1942 arcmsr_iop2drv_data_read_handle(acb);
1943 }
1944 }
1945 /*
1946 **************************************************************************
1947 **************************************************************************
1948 */
arcmsr_hbc_doorbell_isr(struct AdapterControlBlock * acb)1949 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1950 {
1951 u_int32_t doorbell_status;
1952
1953 /*
1954 *******************************************************************
1955 ** Maybe here we need to check wrqbuffer_lock is lock or not
1956 ** DOORBELL: din! don!
1957 ** check if there are any mail need to pack from firmware
1958 *******************************************************************
1959 */
1960 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1961 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1962 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1963 arcmsr_iop2drv_data_wrote_handle(acb);
1964 }
1965 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1966 arcmsr_iop2drv_data_read_handle(acb);
1967 }
1968 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1969 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
1970 }
1971 }
1972 /*
1973 **************************************************************************
1974 **************************************************************************
1975 */
arcmsr_hbd_doorbell_isr(struct AdapterControlBlock * acb)1976 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1977 {
1978 u_int32_t doorbell_status;
1979
1980 /*
1981 *******************************************************************
1982 ** Maybe here we need to check wrqbuffer_lock is lock or not
1983 ** DOORBELL: din! don!
1984 ** check if there are any mail need to pack from firmware
1985 *******************************************************************
1986 */
1987 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1988 if(doorbell_status)
1989 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1990 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1991 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1992 arcmsr_iop2drv_data_wrote_handle(acb);
1993 }
1994 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1995 arcmsr_iop2drv_data_read_handle(acb);
1996 }
1997 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1998 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
1999 }
2000 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
2001 if(doorbell_status)
2002 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
2003 }
2004 }
2005 /*
2006 **************************************************************************
2007 **************************************************************************
2008 */
arcmsr_hbe_doorbell_isr(struct AdapterControlBlock * acb)2009 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
2010 {
2011 u_int32_t doorbell_status, in_doorbell;
2012
2013 /*
2014 *******************************************************************
2015 ** Maybe here we need to check wrqbuffer_lock is lock or not
2016 ** DOORBELL: din! don!
2017 ** check if there are any mail need to pack from firmware
2018 *******************************************************************
2019 */
2020 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2021 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2022 doorbell_status = in_doorbell ^ acb->in_doorbell;
2023 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2024 arcmsr_iop2drv_data_wrote_handle(acb);
2025 }
2026 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2027 arcmsr_iop2drv_data_read_handle(acb);
2028 }
2029 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2030 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
2031 }
2032 acb->in_doorbell = in_doorbell;
2033 }
2034 /*
2035 **************************************************************************
2036 **************************************************************************
2037 */
arcmsr_hbf_doorbell_isr(struct AdapterControlBlock * acb)2038 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb)
2039 {
2040 u_int32_t doorbell_status, in_doorbell;
2041
2042 /*
2043 *******************************************************************
2044 ** Maybe here we need to check wrqbuffer_lock is lock or not
2045 ** DOORBELL: din! don!
2046 ** check if there are any mail need to pack from firmware
2047 *******************************************************************
2048 */
2049 while(1) {
2050 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2051 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF))
2052 break;
2053 }
2054 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2055 doorbell_status = in_doorbell ^ acb->in_doorbell;
2056 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2057 arcmsr_iop2drv_data_wrote_handle(acb);
2058 }
2059 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2060 arcmsr_iop2drv_data_read_handle(acb);
2061 }
2062 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2063 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
2064 }
2065 acb->in_doorbell = in_doorbell;
2066 }
2067 /*
2068 **************************************************************************
2069 **************************************************************************
2070 */
arcmsr_hba_postqueue_isr(struct AdapterControlBlock * acb)2071 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
2072 {
2073 u_int32_t flag_srb;
2074 u_int16_t error;
2075
2076 /*
2077 *****************************************************************************
2078 ** areca cdb command done
2079 *****************************************************************************
2080 */
2081 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2082 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2083 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2084 0, outbound_queueport)) != 0xFFFFFFFF) {
2085 /* check if command done with no error*/
2086 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2087 arcmsr_drain_donequeue(acb, flag_srb, error);
2088 } /*drain reply FIFO*/
2089 }
2090 /*
2091 **************************************************************************
2092 **************************************************************************
2093 */
arcmsr_hbb_postqueue_isr(struct AdapterControlBlock * acb)2094 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
2095 {
2096 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2097 u_int32_t flag_srb;
2098 int index;
2099 u_int16_t error;
2100
2101 /*
2102 *****************************************************************************
2103 ** areca cdb command done
2104 *****************************************************************************
2105 */
2106 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2107 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2108 index = phbbmu->doneq_index;
2109 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2110 phbbmu->done_qbuffer[index] = 0;
2111 index++;
2112 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
2113 phbbmu->doneq_index = index;
2114 /* check if command done with no error*/
2115 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2116 arcmsr_drain_donequeue(acb, flag_srb, error);
2117 } /*drain reply FIFO*/
2118 }
2119 /*
2120 **************************************************************************
2121 **************************************************************************
2122 */
arcmsr_hbc_postqueue_isr(struct AdapterControlBlock * acb)2123 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2124 {
2125 u_int32_t flag_srb,throttling = 0;
2126 u_int16_t error;
2127
2128 /*
2129 *****************************************************************************
2130 ** areca cdb command done
2131 *****************************************************************************
2132 */
2133 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2134 do {
2135 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2136 if (flag_srb == 0xFFFFFFFF)
2137 break;
2138 /* check if command done with no error*/
2139 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2140 arcmsr_drain_donequeue(acb, flag_srb, error);
2141 throttling++;
2142 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2143 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2144 throttling = 0;
2145 }
2146 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2147 }
2148 /*
2149 **********************************************************************
2150 **
2151 **********************************************************************
2152 */
arcmsr_get_doneq_index(struct HBD_MessageUnit0 * phbdmu)2153 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
2154 {
2155 uint16_t doneq_index, index_stripped;
2156
2157 doneq_index = phbdmu->doneq_index;
2158 if (doneq_index & 0x4000) {
2159 index_stripped = doneq_index & 0xFF;
2160 index_stripped += 1;
2161 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2162 phbdmu->doneq_index = index_stripped ?
2163 (index_stripped | 0x4000) : index_stripped;
2164 } else {
2165 index_stripped = doneq_index;
2166 index_stripped += 1;
2167 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2168 phbdmu->doneq_index = index_stripped ?
2169 index_stripped : (index_stripped | 0x4000);
2170 }
2171 return (phbdmu->doneq_index);
2172 }
2173 /*
2174 **************************************************************************
2175 **************************************************************************
2176 */
arcmsr_hbd_postqueue_isr(struct AdapterControlBlock * acb)2177 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
2178 {
2179 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
2180 u_int32_t outbound_write_pointer;
2181 u_int32_t addressLow;
2182 uint16_t doneq_index;
2183 u_int16_t error;
2184 /*
2185 *****************************************************************************
2186 ** areca cdb command done
2187 *****************************************************************************
2188 */
2189 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
2190 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2191 return;
2192 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2193 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2194 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2195 doneq_index = phbdmu->doneq_index;
2196 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2197 doneq_index = arcmsr_get_doneq_index(phbdmu);
2198 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2199 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2200 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2201 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2202 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2203 }
2204 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2205 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2206 }
2207 /*
2208 **************************************************************************
2209 **************************************************************************
2210 */
arcmsr_hbe_postqueue_isr(struct AdapterControlBlock * acb)2211 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
2212 {
2213 u_int16_t error;
2214 uint32_t doneq_index;
2215 uint16_t cmdSMID;
2216
2217 /*
2218 *****************************************************************************
2219 ** areca cdb command done
2220 *****************************************************************************
2221 */
2222 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2223 doneq_index = acb->doneq_index;
2224 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
2225 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2226 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2227 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2228 doneq_index++;
2229 if (doneq_index >= acb->completionQ_entry)
2230 doneq_index = 0;
2231 }
2232 acb->doneq_index = doneq_index;
2233 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2234 }
2235
arcmsr_hbf_postqueue_isr(struct AdapterControlBlock * acb)2236 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb)
2237 {
2238 uint16_t error;
2239 uint32_t doneq_index;
2240 uint16_t cmdSMID;
2241
2242 /*
2243 *****************************************************************************
2244 ** areca cdb command done
2245 *****************************************************************************
2246 */
2247 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2248 doneq_index = acb->doneq_index;
2249 while (1) {
2250 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2251 if (cmdSMID == 0xffff)
2252 break;
2253 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2254 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2255 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2256 doneq_index++;
2257 if (doneq_index >= acb->completionQ_entry)
2258 doneq_index = 0;
2259 }
2260 acb->doneq_index = doneq_index;
2261 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2262 }
2263
2264 /*
2265 **********************************************************************
2266 **********************************************************************
2267 */
arcmsr_handle_hba_isr(struct AdapterControlBlock * acb)2268 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2269 {
2270 u_int32_t outbound_intStatus;
2271 /*
2272 *********************************************
2273 ** check outbound intstatus
2274 *********************************************
2275 */
2276 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2277 if(!outbound_intStatus) {
2278 /*it must be share irq*/
2279 return;
2280 }
2281 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2282 /* MU doorbell interrupts*/
2283 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2284 arcmsr_hba_doorbell_isr(acb);
2285 }
2286 /* MU post queue interrupts*/
2287 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2288 arcmsr_hba_postqueue_isr(acb);
2289 }
2290 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2291 arcmsr_hba_message_isr(acb);
2292 }
2293 }
2294 /*
2295 **********************************************************************
2296 **********************************************************************
2297 */
arcmsr_handle_hbb_isr(struct AdapterControlBlock * acb)2298 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2299 {
2300 u_int32_t outbound_doorbell;
2301 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2302 /*
2303 *********************************************
2304 ** check outbound intstatus
2305 *********************************************
2306 */
2307 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2308 if(!outbound_doorbell) {
2309 /*it must be share irq*/
2310 return;
2311 }
2312 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2313 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2314 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2315 /* MU ioctl transfer doorbell interrupts*/
2316 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2317 arcmsr_iop2drv_data_wrote_handle(acb);
2318 }
2319 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2320 arcmsr_iop2drv_data_read_handle(acb);
2321 }
2322 /* MU post queue interrupts*/
2323 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2324 arcmsr_hbb_postqueue_isr(acb);
2325 }
2326 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2327 arcmsr_hbb_message_isr(acb);
2328 }
2329 }
2330 /*
2331 **********************************************************************
2332 **********************************************************************
2333 */
arcmsr_handle_hbc_isr(struct AdapterControlBlock * acb)2334 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2335 {
2336 u_int32_t host_interrupt_status;
2337 /*
2338 *********************************************
2339 ** check outbound intstatus
2340 *********************************************
2341 */
2342 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2343 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2344 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2345 if(!host_interrupt_status) {
2346 /*it must be share irq*/
2347 return;
2348 }
2349 do {
2350 /* MU doorbell interrupts*/
2351 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2352 arcmsr_hbc_doorbell_isr(acb);
2353 }
2354 /* MU post queue interrupts*/
2355 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2356 arcmsr_hbc_postqueue_isr(acb);
2357 }
2358 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2359 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2360 }
2361 /*
2362 **********************************************************************
2363 **********************************************************************
2364 */
arcmsr_handle_hbd_isr(struct AdapterControlBlock * acb)2365 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2366 {
2367 u_int32_t host_interrupt_status;
2368 u_int32_t intmask_org;
2369 /*
2370 *********************************************
2371 ** check outbound intstatus
2372 *********************************************
2373 */
2374 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2375 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2376 /*it must be share irq*/
2377 return;
2378 }
2379 /* disable outbound interrupt */
2380 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
2381 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2382 /* MU doorbell interrupts*/
2383 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2384 arcmsr_hbd_doorbell_isr(acb);
2385 }
2386 /* MU post queue interrupts*/
2387 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2388 arcmsr_hbd_postqueue_isr(acb);
2389 }
2390 /* enable all outbound interrupt */
2391 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2392 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2393 }
2394 /*
2395 **********************************************************************
2396 **********************************************************************
2397 */
arcmsr_handle_hbe_isr(struct AdapterControlBlock * acb)2398 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
2399 {
2400 u_int32_t host_interrupt_status;
2401 /*
2402 *********************************************
2403 ** check outbound intstatus
2404 *********************************************
2405 */
2406 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
2407 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2408 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2409 if(!host_interrupt_status) {
2410 /*it must be share irq*/
2411 return;
2412 }
2413 do {
2414 /* MU doorbell interrupts*/
2415 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2416 arcmsr_hbe_doorbell_isr(acb);
2417 }
2418 /* MU post queue interrupts*/
2419 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2420 arcmsr_hbe_postqueue_isr(acb);
2421 }
2422 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2423 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2424 }
2425
arcmsr_handle_hbf_isr(struct AdapterControlBlock * acb)2426 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb)
2427 {
2428 u_int32_t host_interrupt_status;
2429 /*
2430 *********************************************
2431 ** check outbound intstatus
2432 *********************************************
2433 */
2434 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &
2435 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2436 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2437 if(!host_interrupt_status) {
2438 /*it must be share irq*/
2439 return;
2440 }
2441 do {
2442 /* MU doorbell interrupts*/
2443 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2444 arcmsr_hbf_doorbell_isr(acb);
2445 }
2446 /* MU post queue interrupts*/
2447 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2448 arcmsr_hbf_postqueue_isr(acb);
2449 }
2450 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);
2451 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2452 }
2453 /*
2454 ******************************************************************************
2455 ******************************************************************************
2456 */
arcmsr_interrupt(struct AdapterControlBlock * acb)2457 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2458 {
2459 switch (acb->adapter_type) {
2460 case ACB_ADAPTER_TYPE_A:
2461 arcmsr_handle_hba_isr(acb);
2462 break;
2463 case ACB_ADAPTER_TYPE_B:
2464 arcmsr_handle_hbb_isr(acb);
2465 break;
2466 case ACB_ADAPTER_TYPE_C:
2467 arcmsr_handle_hbc_isr(acb);
2468 break;
2469 case ACB_ADAPTER_TYPE_D:
2470 arcmsr_handle_hbd_isr(acb);
2471 break;
2472 case ACB_ADAPTER_TYPE_E:
2473 arcmsr_handle_hbe_isr(acb);
2474 break;
2475 case ACB_ADAPTER_TYPE_F:
2476 arcmsr_handle_hbf_isr(acb);
2477 break;
2478 default:
2479 printf("arcmsr%d: interrupt service,"
2480 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2481 break;
2482 }
2483 }
2484 /*
2485 **********************************************************************
2486 **********************************************************************
2487 */
arcmsr_intr_handler(void * arg)2488 static void arcmsr_intr_handler(void *arg)
2489 {
2490 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2491
2492 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2493 arcmsr_interrupt(acb);
2494 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2495 }
2496 /*
2497 ******************************************************************************
2498 ******************************************************************************
2499 */
arcmsr_polling_devmap(void * arg)2500 static void arcmsr_polling_devmap(void *arg)
2501 {
2502 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2503 switch (acb->adapter_type) {
2504 case ACB_ADAPTER_TYPE_A:
2505 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2506 break;
2507
2508 case ACB_ADAPTER_TYPE_B: {
2509 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2510 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2511 }
2512 break;
2513
2514 case ACB_ADAPTER_TYPE_C:
2515 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2516 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2517 break;
2518
2519 case ACB_ADAPTER_TYPE_D:
2520 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2521 break;
2522
2523 case ACB_ADAPTER_TYPE_E:
2524 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2525 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2526 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2527 break;
2528
2529 case ACB_ADAPTER_TYPE_F: {
2530 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);
2531 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
2532 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
2533 goto nxt6s;
2534 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2535 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2536 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2537 break;
2538 }
2539 }
2540 nxt6s:
2541 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2542 {
2543 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
2544 }
2545 }
2546
2547 /*
2548 *******************************************************************************
2549 **
2550 *******************************************************************************
2551 */
arcmsr_iop_parking(struct AdapterControlBlock * acb)2552 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2553 {
2554 u_int32_t intmask_org;
2555
2556 if(acb != NULL) {
2557 /* stop adapter background rebuild */
2558 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2559 intmask_org = arcmsr_disable_allintr(acb);
2560 arcmsr_stop_adapter_bgrb(acb);
2561 arcmsr_flush_adapter_cache(acb);
2562 arcmsr_enable_allintr(acb, intmask_org);
2563 }
2564 }
2565 }
2566 /*
2567 ***********************************************************************
2568 **
2569 ************************************************************************
2570 */
arcmsr_iop_ioctlcmd(struct AdapterControlBlock * acb,u_int32_t ioctl_cmd,caddr_t arg)2571 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2572 {
2573 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2574 u_int32_t retvalue = EINVAL;
2575
2576 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2577 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2578 return retvalue;
2579 }
2580 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2581 switch(ioctl_cmd) {
2582 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2583 u_int8_t *pQbuffer;
2584 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2585 u_int32_t allxfer_len=0;
2586
2587 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2588 && (allxfer_len < 1031)) {
2589 /*copy READ QBUFFER to srb*/
2590 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2591 *ptmpQbuffer = *pQbuffer;
2592 acb->rqbuf_firstindex++;
2593 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2594 /*if last index number set it to 0 */
2595 ptmpQbuffer++;
2596 allxfer_len++;
2597 }
2598 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2599 struct QBUFFER *prbuffer;
2600
2601 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2602 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2603 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2604 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2605 }
2606 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2607 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2608 retvalue = ARCMSR_MESSAGE_SUCCESS;
2609 }
2610 break;
2611 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2612 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2613 u_int8_t *pQbuffer;
2614 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2615
2616 user_len = pcmdmessagefld->cmdmessage.Length;
2617 /*check if data xfer length of this request will overflow my array qbuffer */
2618 wqbuf_lastindex = acb->wqbuf_lastindex;
2619 wqbuf_firstindex = acb->wqbuf_firstindex;
2620 if(wqbuf_lastindex != wqbuf_firstindex) {
2621 arcmsr_Write_data_2iop_wqbuffer(acb);
2622 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2623 } else {
2624 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2625 (ARCMSR_MAX_QBUFFER - 1);
2626 if(my_empty_len >= user_len) {
2627 while(user_len > 0) {
2628 /*copy srb data to wqbuffer*/
2629 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2630 *pQbuffer = *ptmpuserbuffer;
2631 acb->wqbuf_lastindex++;
2632 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2633 /*if last index number set it to 0 */
2634 ptmpuserbuffer++;
2635 user_len--;
2636 }
2637 /*post fist Qbuffer*/
2638 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2639 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2640 arcmsr_Write_data_2iop_wqbuffer(acb);
2641 }
2642 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2643 } else {
2644 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2645 }
2646 }
2647 retvalue = ARCMSR_MESSAGE_SUCCESS;
2648 }
2649 break;
2650 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2651 u_int8_t *pQbuffer = acb->rqbuffer;
2652
2653 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2654 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2655 arcmsr_iop_message_read(acb);
2656 /*signature, let IOP know data has been readed */
2657 }
2658 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2659 acb->rqbuf_firstindex = 0;
2660 acb->rqbuf_lastindex = 0;
2661 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2662 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2663 retvalue = ARCMSR_MESSAGE_SUCCESS;
2664 }
2665 break;
2666 case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2667 {
2668 u_int8_t *pQbuffer = acb->wqbuffer;
2669
2670 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2671 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2672 arcmsr_iop_message_read(acb);
2673 /*signature, let IOP know data has been readed */
2674 }
2675 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2676 acb->wqbuf_firstindex = 0;
2677 acb->wqbuf_lastindex = 0;
2678 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2679 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2680 retvalue = ARCMSR_MESSAGE_SUCCESS;
2681 }
2682 break;
2683 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2684 u_int8_t *pQbuffer;
2685
2686 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2687 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2688 arcmsr_iop_message_read(acb);
2689 /*signature, let IOP know data has been readed */
2690 }
2691 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2692 |ACB_F_MESSAGE_RQBUFFER_CLEARED
2693 |ACB_F_MESSAGE_WQBUFFER_READ);
2694 acb->rqbuf_firstindex = 0;
2695 acb->rqbuf_lastindex = 0;
2696 acb->wqbuf_firstindex = 0;
2697 acb->wqbuf_lastindex = 0;
2698 pQbuffer = acb->rqbuffer;
2699 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2700 pQbuffer = acb->wqbuffer;
2701 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2702 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2703 retvalue = ARCMSR_MESSAGE_SUCCESS;
2704 }
2705 break;
2706 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2707 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2708 retvalue = ARCMSR_MESSAGE_SUCCESS;
2709 }
2710 break;
2711 case ARCMSR_MESSAGE_SAY_HELLO: {
2712 u_int8_t *hello_string = "Hello! I am ARCMSR";
2713 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2714
2715 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2716 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2717 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2718 return ENOIOCTL;
2719 }
2720 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2721 retvalue = ARCMSR_MESSAGE_SUCCESS;
2722 }
2723 break;
2724 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2725 arcmsr_iop_parking(acb);
2726 retvalue = ARCMSR_MESSAGE_SUCCESS;
2727 }
2728 break;
2729 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2730 arcmsr_flush_adapter_cache(acb);
2731 retvalue = ARCMSR_MESSAGE_SUCCESS;
2732 }
2733 break;
2734 }
2735 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2736 return (retvalue);
2737 }
2738 /*
2739 **************************************************************************
2740 **************************************************************************
2741 */
arcmsr_free_srb(struct CommandControlBlock * srb)2742 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2743 {
2744 struct AdapterControlBlock *acb;
2745
2746 acb = srb->acb;
2747 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2748 srb->srb_state = ARCMSR_SRB_DONE;
2749 srb->srb_flags = 0;
2750 acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2751 acb->workingsrb_doneindex++;
2752 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2753 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2754 }
2755 /*
2756 **************************************************************************
2757 **************************************************************************
2758 */
arcmsr_get_freesrb(struct AdapterControlBlock * acb)2759 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2760 {
2761 struct CommandControlBlock *srb = NULL;
2762 u_int32_t workingsrb_startindex, workingsrb_doneindex;
2763
2764 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2765 workingsrb_doneindex = acb->workingsrb_doneindex;
2766 workingsrb_startindex = acb->workingsrb_startindex;
2767 srb = acb->srbworkingQ[workingsrb_startindex];
2768 workingsrb_startindex++;
2769 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2770 if(workingsrb_doneindex != workingsrb_startindex) {
2771 acb->workingsrb_startindex = workingsrb_startindex;
2772 } else {
2773 srb = NULL;
2774 }
2775 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2776 return(srb);
2777 }
2778 /*
2779 **************************************************************************
2780 **************************************************************************
2781 */
arcmsr_iop_message_xfer(struct AdapterControlBlock * acb,union ccb * pccb)2782 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2783 {
2784 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2785 int retvalue = 0, transfer_len = 0;
2786 char *buffer;
2787 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2788 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2789 (u_int32_t ) ptr[6] << 16 |
2790 (u_int32_t ) ptr[7] << 8 |
2791 (u_int32_t ) ptr[8];
2792 /* 4 bytes: Areca io control code */
2793 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2794 buffer = pccb->csio.data_ptr;
2795 transfer_len = pccb->csio.dxfer_len;
2796 } else {
2797 retvalue = ARCMSR_MESSAGE_FAIL;
2798 goto message_out;
2799 }
2800 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2801 retvalue = ARCMSR_MESSAGE_FAIL;
2802 goto message_out;
2803 }
2804 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2805 switch(controlcode) {
2806 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2807 u_int8_t *pQbuffer;
2808 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2809 int32_t allxfer_len = 0;
2810
2811 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2812 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2813 && (allxfer_len < 1031)) {
2814 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2815 *ptmpQbuffer = *pQbuffer;
2816 acb->rqbuf_firstindex++;
2817 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2818 ptmpQbuffer++;
2819 allxfer_len++;
2820 }
2821 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2822 struct QBUFFER *prbuffer;
2823
2824 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2825 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2826 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2827 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2828 }
2829 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2830 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2831 retvalue = ARCMSR_MESSAGE_SUCCESS;
2832 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2833 }
2834 break;
2835 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2836 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2837 u_int8_t *pQbuffer;
2838 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2839
2840 user_len = pcmdmessagefld->cmdmessage.Length;
2841 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2842 wqbuf_lastindex = acb->wqbuf_lastindex;
2843 wqbuf_firstindex = acb->wqbuf_firstindex;
2844 if (wqbuf_lastindex != wqbuf_firstindex) {
2845 arcmsr_Write_data_2iop_wqbuffer(acb);
2846 /* has error report sensedata */
2847 if(pccb->csio.sense_len) {
2848 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2849 /* Valid,ErrorCode */
2850 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2851 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2852 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2853 /* AdditionalSenseLength */
2854 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2855 /* AdditionalSenseCode */
2856 }
2857 retvalue = ARCMSR_MESSAGE_FAIL;
2858 } else {
2859 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2860 &(ARCMSR_MAX_QBUFFER - 1);
2861 if (my_empty_len >= user_len) {
2862 while (user_len > 0) {
2863 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2864 *pQbuffer = *ptmpuserbuffer;
2865 acb->wqbuf_lastindex++;
2866 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2867 ptmpuserbuffer++;
2868 user_len--;
2869 }
2870 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2871 acb->acb_flags &=
2872 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2873 arcmsr_Write_data_2iop_wqbuffer(acb);
2874 }
2875 } else {
2876 /* has error report sensedata */
2877 if(pccb->csio.sense_len) {
2878 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2879 /* Valid,ErrorCode */
2880 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2881 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2882 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2883 /* AdditionalSenseLength */
2884 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2885 /* AdditionalSenseCode */
2886 }
2887 retvalue = ARCMSR_MESSAGE_FAIL;
2888 }
2889 }
2890 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2891 }
2892 break;
2893 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2894 u_int8_t *pQbuffer = acb->rqbuffer;
2895
2896 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2897 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2898 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2899 arcmsr_iop_message_read(acb);
2900 }
2901 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2902 acb->rqbuf_firstindex = 0;
2903 acb->rqbuf_lastindex = 0;
2904 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2905 pcmdmessagefld->cmdmessage.ReturnCode =
2906 ARCMSR_MESSAGE_RETURNCODE_OK;
2907 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2908 }
2909 break;
2910 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2911 u_int8_t *pQbuffer = acb->wqbuffer;
2912
2913 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2914 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2915 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2916 arcmsr_iop_message_read(acb);
2917 }
2918 acb->acb_flags |=
2919 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2920 ACB_F_MESSAGE_WQBUFFER_READ);
2921 acb->wqbuf_firstindex = 0;
2922 acb->wqbuf_lastindex = 0;
2923 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2924 pcmdmessagefld->cmdmessage.ReturnCode =
2925 ARCMSR_MESSAGE_RETURNCODE_OK;
2926 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2927 }
2928 break;
2929 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2930 u_int8_t *pQbuffer;
2931
2932 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2933 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2934 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2935 arcmsr_iop_message_read(acb);
2936 }
2937 acb->acb_flags |=
2938 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2939 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2940 | ACB_F_MESSAGE_WQBUFFER_READ);
2941 acb->rqbuf_firstindex = 0;
2942 acb->rqbuf_lastindex = 0;
2943 acb->wqbuf_firstindex = 0;
2944 acb->wqbuf_lastindex = 0;
2945 pQbuffer = acb->rqbuffer;
2946 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2947 pQbuffer = acb->wqbuffer;
2948 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2949 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2950 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2951 }
2952 break;
2953 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2954 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2955 }
2956 break;
2957 case ARCMSR_MESSAGE_SAY_HELLO: {
2958 int8_t *hello_string = "Hello! I am ARCMSR";
2959
2960 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2961 , (int16_t)strlen(hello_string));
2962 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2963 }
2964 break;
2965 case ARCMSR_MESSAGE_SAY_GOODBYE:
2966 arcmsr_iop_parking(acb);
2967 break;
2968 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2969 arcmsr_flush_adapter_cache(acb);
2970 break;
2971 default:
2972 retvalue = ARCMSR_MESSAGE_FAIL;
2973 }
2974 message_out:
2975 return (retvalue);
2976 }
2977 /*
2978 *********************************************************************
2979 *********************************************************************
2980 */
arcmsr_execute_srb(void * arg,bus_dma_segment_t * dm_segs,int nseg,int error)2981 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2982 {
2983 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2984 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2985 union ccb *pccb;
2986 int target, lun;
2987
2988 pccb = srb->pccb;
2989 target = pccb->ccb_h.target_id;
2990 lun = pccb->ccb_h.target_lun;
2991 acb->pktRequestCount++;
2992 if(error != 0) {
2993 if(error != EFBIG) {
2994 printf("arcmsr%d: unexpected error %x"
2995 " returned from 'bus_dmamap_load' \n"
2996 , acb->pci_unit, error);
2997 }
2998 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2999 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
3000 }
3001 arcmsr_srb_complete(srb, 0);
3002 return;
3003 }
3004 if(nseg > ARCMSR_MAX_SG_ENTRIES) {
3005 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
3006 arcmsr_srb_complete(srb, 0);
3007 return;
3008 }
3009 if(acb->acb_flags & ACB_F_BUS_RESET) {
3010 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
3011 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
3012 arcmsr_srb_complete(srb, 0);
3013 return;
3014 }
3015 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
3016 u_int8_t block_cmd, cmd;
3017
3018 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
3019 block_cmd = cmd & 0x0f;
3020 if(block_cmd == 0x08 || block_cmd == 0x0a) {
3021 printf("arcmsr%d:block 'read/write' command "
3022 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
3023 , acb->pci_unit, cmd, target, lun);
3024 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3025 arcmsr_srb_complete(srb, 0);
3026 return;
3027 }
3028 }
3029 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
3030 if(nseg != 0) {
3031 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
3032 }
3033 arcmsr_srb_complete(srb, 0);
3034 return;
3035 }
3036 if(acb->srboutstandingcount >= acb->maxOutstanding) {
3037 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
3038 {
3039 xpt_freeze_simq(acb->psim, 1);
3040 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
3041 }
3042 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
3043 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
3044 arcmsr_srb_complete(srb, 0);
3045 return;
3046 }
3047 pccb->ccb_h.status |= CAM_SIM_QUEUED;
3048 arcmsr_build_srb(srb, dm_segs, nseg);
3049 arcmsr_post_srb(acb, srb);
3050 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
3051 {
3052 arcmsr_callout_init(&srb->ccb_callout);
3053 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
3054 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
3055 arcmsr_srb_timeout, srb, 0);
3056 srb->srb_flags |= SRB_FLAG_TIMER_START;
3057 }
3058 }
3059 /*
3060 *****************************************************************************************
3061 *****************************************************************************************
3062 */
arcmsr_seek_cmd2abort(union ccb * abortccb)3063 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
3064 {
3065 struct CommandControlBlock *srb;
3066 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
3067 u_int32_t intmask_org;
3068 int i = 0;
3069
3070 acb->num_aborts++;
3071 /*
3072 ***************************************************************************
3073 ** It is the upper layer do abort command this lock just prior to calling us.
3074 ** First determine if we currently own this command.
3075 ** Start by searching the device queue. If not found
3076 ** at all, and the system wanted us to just abort the
3077 ** command return success.
3078 ***************************************************************************
3079 */
3080 if(acb->srboutstandingcount != 0) {
3081 /* disable all outbound interrupt */
3082 intmask_org = arcmsr_disable_allintr(acb);
3083 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3084 srb = acb->psrb_pool[i];
3085 if(srb->srb_state == ARCMSR_SRB_START) {
3086 if(srb->pccb == abortccb) {
3087 srb->srb_state = ARCMSR_SRB_ABORTED;
3088 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
3089 "outstanding command \n"
3090 , acb->pci_unit, abortccb->ccb_h.target_id
3091 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
3092 arcmsr_polling_srbdone(acb, srb);
3093 /* enable outbound Post Queue, outbound doorbell Interrupt */
3094 arcmsr_enable_allintr(acb, intmask_org);
3095 return (TRUE);
3096 }
3097 }
3098 }
3099 /* enable outbound Post Queue, outbound doorbell Interrupt */
3100 arcmsr_enable_allintr(acb, intmask_org);
3101 }
3102 return(FALSE);
3103 }
3104 /*
3105 ****************************************************************************
3106 ****************************************************************************
3107 */
arcmsr_bus_reset(struct AdapterControlBlock * acb)3108 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
3109 {
3110 int retry = 0;
3111
3112 acb->num_resets++;
3113 acb->acb_flags |= ACB_F_BUS_RESET;
3114 while(acb->srboutstandingcount != 0 && retry < 400) {
3115 arcmsr_interrupt(acb);
3116 UDELAY(25000);
3117 retry++;
3118 }
3119 arcmsr_iop_reset(acb);
3120 acb->acb_flags &= ~ACB_F_BUS_RESET;
3121 }
3122 /*
3123 **************************************************************************
3124 **************************************************************************
3125 */
arcmsr_handle_virtual_command(struct AdapterControlBlock * acb,union ccb * pccb)3126 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3127 union ccb *pccb)
3128 {
3129 if (pccb->ccb_h.target_lun) {
3130 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3131 xpt_done(pccb);
3132 return;
3133 }
3134 pccb->ccb_h.status |= CAM_REQ_CMP;
3135 switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
3136 case INQUIRY: {
3137 unsigned char inqdata[36];
3138 char *buffer = pccb->csio.data_ptr;
3139
3140 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */
3141 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */
3142 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */
3143 inqdata[3] = 0;
3144 inqdata[4] = 31; /* length of additional data */
3145 inqdata[5] = 0;
3146 inqdata[6] = 0;
3147 inqdata[7] = 0;
3148 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */
3149 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */
3150 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
3151 memcpy(buffer, inqdata, sizeof(inqdata));
3152 xpt_done(pccb);
3153 }
3154 break;
3155 case WRITE_BUFFER:
3156 case READ_BUFFER: {
3157 if (arcmsr_iop_message_xfer(acb, pccb)) {
3158 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
3159 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
3160 }
3161 xpt_done(pccb);
3162 }
3163 break;
3164 default:
3165 xpt_done(pccb);
3166 }
3167 }
3168 /*
3169 *********************************************************************
3170 *********************************************************************
3171 */
arcmsr_action(struct cam_sim * psim,union ccb * pccb)3172 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
3173 {
3174 struct AdapterControlBlock *acb;
3175
3176 acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
3177 if(acb == NULL) {
3178 pccb->ccb_h.status |= CAM_REQ_INVALID;
3179 xpt_done(pccb);
3180 return;
3181 }
3182 switch (pccb->ccb_h.func_code) {
3183 case XPT_SCSI_IO: {
3184 struct CommandControlBlock *srb;
3185 int target = pccb->ccb_h.target_id;
3186 int error;
3187
3188 if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
3189 pccb->ccb_h.status = CAM_REQ_INVALID;
3190 xpt_done(pccb);
3191 return;
3192 }
3193
3194 if(target == 16) {
3195 /* virtual device for iop message transfer */
3196 arcmsr_handle_virtual_command(acb, pccb);
3197 return;
3198 }
3199 if((srb = arcmsr_get_freesrb(acb)) == NULL) {
3200 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
3201 xpt_done(pccb);
3202 return;
3203 }
3204 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
3205 pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
3206 srb->pccb = pccb;
3207 error = bus_dmamap_load_ccb(acb->dm_segs_dmat
3208 , srb->dm_segs_dmamap
3209 , pccb
3210 , arcmsr_execute_srb, srb, /*flags*/0);
3211 if(error == EINPROGRESS) {
3212 xpt_freeze_simq(acb->psim, 1);
3213 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
3214 }
3215 break;
3216 }
3217 case XPT_PATH_INQ: {
3218 struct ccb_pathinq *cpi = &pccb->cpi;
3219
3220 cpi->version_num = 1;
3221 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
3222 cpi->target_sprt = 0;
3223 cpi->hba_misc = 0;
3224 cpi->hba_eng_cnt = 0;
3225 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */
3226 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
3227 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
3228 cpi->bus_id = cam_sim_bus(psim);
3229 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3230 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
3231 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
3232 cpi->unit_number = cam_sim_unit(psim);
3233 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3234 cpi->base_transfer_speed = 1200000;
3235 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3236 cpi->base_transfer_speed = 600000;
3237 else
3238 cpi->base_transfer_speed = 300000;
3239 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3240 (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3241 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3242 (acb->vendor_device_id == PCIDevVenIDARC1214))
3243 {
3244 cpi->transport = XPORT_SAS;
3245 cpi->transport_version = 0;
3246 cpi->protocol_version = SCSI_REV_SPC2;
3247 }
3248 else
3249 {
3250 cpi->transport = XPORT_SPI;
3251 cpi->transport_version = 2;
3252 cpi->protocol_version = SCSI_REV_2;
3253 }
3254 cpi->protocol = PROTO_SCSI;
3255 cpi->ccb_h.status |= CAM_REQ_CMP;
3256 xpt_done(pccb);
3257 break;
3258 }
3259 case XPT_ABORT: {
3260 union ccb *pabort_ccb;
3261
3262 pabort_ccb = pccb->cab.abort_ccb;
3263 switch (pabort_ccb->ccb_h.func_code) {
3264 case XPT_ACCEPT_TARGET_IO:
3265 case XPT_CONT_TARGET_IO:
3266 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
3267 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
3268 xpt_done(pabort_ccb);
3269 pccb->ccb_h.status |= CAM_REQ_CMP;
3270 } else {
3271 xpt_print_path(pabort_ccb->ccb_h.path);
3272 printf("Not found\n");
3273 pccb->ccb_h.status |= CAM_PATH_INVALID;
3274 }
3275 break;
3276 case XPT_SCSI_IO:
3277 pccb->ccb_h.status |= CAM_UA_ABORT;
3278 break;
3279 default:
3280 pccb->ccb_h.status |= CAM_REQ_INVALID;
3281 break;
3282 }
3283 xpt_done(pccb);
3284 break;
3285 }
3286 case XPT_RESET_BUS:
3287 case XPT_RESET_DEV: {
3288 u_int32_t i;
3289
3290 arcmsr_bus_reset(acb);
3291 for (i=0; i < 500; i++) {
3292 DELAY(1000);
3293 }
3294 pccb->ccb_h.status |= CAM_REQ_CMP;
3295 xpt_done(pccb);
3296 break;
3297 }
3298 case XPT_TERM_IO: {
3299 pccb->ccb_h.status |= CAM_REQ_INVALID;
3300 xpt_done(pccb);
3301 break;
3302 }
3303 case XPT_GET_TRAN_SETTINGS: {
3304 struct ccb_trans_settings *cts;
3305
3306 if(pccb->ccb_h.target_id == 16) {
3307 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3308 xpt_done(pccb);
3309 break;
3310 }
3311 cts = &pccb->cts;
3312 {
3313 struct ccb_trans_settings_scsi *scsi;
3314 struct ccb_trans_settings_spi *spi;
3315 struct ccb_trans_settings_sas *sas;
3316
3317 scsi = &cts->proto_specific.scsi;
3318 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
3319 scsi->valid = CTS_SCSI_VALID_TQ;
3320 cts->protocol = PROTO_SCSI;
3321
3322 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3323 (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3324 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3325 (acb->vendor_device_id == PCIDevVenIDARC1214))
3326 {
3327 cts->protocol_version = SCSI_REV_SPC2;
3328 cts->transport_version = 0;
3329 cts->transport = XPORT_SAS;
3330 sas = &cts->xport_specific.sas;
3331 sas->valid = CTS_SAS_VALID_SPEED;
3332 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3333 sas->bitrate = 1200000;
3334 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3335 sas->bitrate = 600000;
3336 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3337 sas->bitrate = 300000;
3338 }
3339 else
3340 {
3341 cts->protocol_version = SCSI_REV_2;
3342 cts->transport_version = 2;
3343 cts->transport = XPORT_SPI;
3344 spi = &cts->xport_specific.spi;
3345 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3346 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3347 spi->sync_period = 1;
3348 else
3349 spi->sync_period = 2;
3350 spi->sync_offset = 32;
3351 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3352 spi->valid = CTS_SPI_VALID_DISC
3353 | CTS_SPI_VALID_SYNC_RATE
3354 | CTS_SPI_VALID_SYNC_OFFSET
3355 | CTS_SPI_VALID_BUS_WIDTH;
3356 }
3357 }
3358 pccb->ccb_h.status |= CAM_REQ_CMP;
3359 xpt_done(pccb);
3360 break;
3361 }
3362 case XPT_SET_TRAN_SETTINGS: {
3363 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3364 xpt_done(pccb);
3365 break;
3366 }
3367 case XPT_CALC_GEOMETRY:
3368 if(pccb->ccb_h.target_id == 16) {
3369 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3370 xpt_done(pccb);
3371 break;
3372 }
3373 cam_calc_geometry(&pccb->ccg, 1);
3374 xpt_done(pccb);
3375 break;
3376 default:
3377 pccb->ccb_h.status |= CAM_REQ_INVALID;
3378 xpt_done(pccb);
3379 break;
3380 }
3381 }
3382 /*
3383 **********************************************************************
3384 **********************************************************************
3385 */
arcmsr_start_hba_bgrb(struct AdapterControlBlock * acb)3386 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3387 {
3388 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3389 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3390 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3391 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3392 }
3393 }
3394 /*
3395 **********************************************************************
3396 **********************************************************************
3397 */
arcmsr_start_hbb_bgrb(struct AdapterControlBlock * acb)3398 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3399 {
3400 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3401 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3402 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3403 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3404 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3405 }
3406 }
3407 /*
3408 **********************************************************************
3409 **********************************************************************
3410 */
arcmsr_start_hbc_bgrb(struct AdapterControlBlock * acb)3411 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3412 {
3413 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3414 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3415 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3416 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3417 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3418 }
3419 }
3420 /*
3421 **********************************************************************
3422 **********************************************************************
3423 */
arcmsr_start_hbd_bgrb(struct AdapterControlBlock * acb)3424 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3425 {
3426 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3427 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3428 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3429 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3430 }
3431 }
3432 /*
3433 **********************************************************************
3434 **********************************************************************
3435 */
arcmsr_start_hbe_bgrb(struct AdapterControlBlock * acb)3436 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
3437 {
3438 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3439 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3440 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3441 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3442 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3443 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3444 }
3445 }
3446 /*
3447 **********************************************************************
3448 **********************************************************************
3449 */
arcmsr_start_adapter_bgrb(struct AdapterControlBlock * acb)3450 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3451 {
3452 switch (acb->adapter_type) {
3453 case ACB_ADAPTER_TYPE_A:
3454 arcmsr_start_hba_bgrb(acb);
3455 break;
3456 case ACB_ADAPTER_TYPE_B:
3457 arcmsr_start_hbb_bgrb(acb);
3458 break;
3459 case ACB_ADAPTER_TYPE_C:
3460 arcmsr_start_hbc_bgrb(acb);
3461 break;
3462 case ACB_ADAPTER_TYPE_D:
3463 arcmsr_start_hbd_bgrb(acb);
3464 break;
3465 case ACB_ADAPTER_TYPE_E:
3466 case ACB_ADAPTER_TYPE_F:
3467 arcmsr_start_hbe_bgrb(acb);
3468 break;
3469 }
3470 }
3471 /*
3472 **********************************************************************
3473 **
3474 **********************************************************************
3475 */
arcmsr_polling_hba_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3476 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3477 {
3478 struct CommandControlBlock *srb;
3479 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3480 u_int16_t error;
3481
3482 polling_ccb_retry:
3483 poll_count++;
3484 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3485 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/
3486 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3487 while(1) {
3488 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3489 0, outbound_queueport)) == 0xFFFFFFFF) {
3490 if(poll_srb_done) {
3491 break;/*chip FIFO no ccb for completion already*/
3492 } else {
3493 UDELAY(25000);
3494 if ((poll_count > 100) && (poll_srb != NULL)) {
3495 break;
3496 }
3497 goto polling_ccb_retry;
3498 }
3499 }
3500 /* check if command done with no error*/
3501 srb = (struct CommandControlBlock *)
3502 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3503 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3504 poll_srb_done = (srb == poll_srb) ? 1:0;
3505 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3506 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3507 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3508 "poll command abort successfully \n"
3509 , acb->pci_unit
3510 , srb->pccb->ccb_h.target_id
3511 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3512 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3513 arcmsr_srb_complete(srb, 1);
3514 continue;
3515 }
3516 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3517 "srboutstandingcount=%d \n"
3518 , acb->pci_unit
3519 , srb, acb->srboutstandingcount);
3520 continue;
3521 }
3522 arcmsr_report_srb_state(acb, srb, error);
3523 } /*drain reply FIFO*/
3524 }
3525 /*
3526 **********************************************************************
3527 **
3528 **********************************************************************
3529 */
arcmsr_polling_hbb_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3530 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3531 {
3532 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3533 struct CommandControlBlock *srb;
3534 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3535 int index;
3536 u_int16_t error;
3537
3538 polling_ccb_retry:
3539 poll_count++;
3540 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3541 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3542 while(1) {
3543 index = phbbmu->doneq_index;
3544 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3545 if(poll_srb_done) {
3546 break;/*chip FIFO no ccb for completion already*/
3547 } else {
3548 UDELAY(25000);
3549 if ((poll_count > 100) && (poll_srb != NULL)) {
3550 break;
3551 }
3552 goto polling_ccb_retry;
3553 }
3554 }
3555 phbbmu->done_qbuffer[index] = 0;
3556 index++;
3557 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
3558 phbbmu->doneq_index = index;
3559 /* check if command done with no error*/
3560 srb = (struct CommandControlBlock *)
3561 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3562 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3563 poll_srb_done = (srb == poll_srb) ? 1:0;
3564 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3565 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3566 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3567 "poll command abort successfully \n"
3568 , acb->pci_unit
3569 , srb->pccb->ccb_h.target_id
3570 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3571 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3572 arcmsr_srb_complete(srb, 1);
3573 continue;
3574 }
3575 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3576 "srboutstandingcount=%d \n"
3577 , acb->pci_unit
3578 , srb, acb->srboutstandingcount);
3579 continue;
3580 }
3581 arcmsr_report_srb_state(acb, srb, error);
3582 } /*drain reply FIFO*/
3583 }
3584 /*
3585 **********************************************************************
3586 **
3587 **********************************************************************
3588 */
arcmsr_polling_hbc_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3589 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3590 {
3591 struct CommandControlBlock *srb;
3592 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3593 u_int16_t error;
3594
3595 polling_ccb_retry:
3596 poll_count++;
3597 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3598 while(1) {
3599 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3600 if(poll_srb_done) {
3601 break;/*chip FIFO no ccb for completion already*/
3602 } else {
3603 UDELAY(25000);
3604 if ((poll_count > 100) && (poll_srb != NULL)) {
3605 break;
3606 }
3607 if (acb->srboutstandingcount == 0) {
3608 break;
3609 }
3610 goto polling_ccb_retry;
3611 }
3612 }
3613 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3614 /* check if command done with no error*/
3615 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3616 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3617 if (poll_srb != NULL)
3618 poll_srb_done = (srb == poll_srb) ? 1:0;
3619 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3620 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3621 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3622 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3623 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3624 arcmsr_srb_complete(srb, 1);
3625 continue;
3626 }
3627 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3628 , acb->pci_unit, srb, acb->srboutstandingcount);
3629 continue;
3630 }
3631 arcmsr_report_srb_state(acb, srb, error);
3632 } /*drain reply FIFO*/
3633 }
3634 /*
3635 **********************************************************************
3636 **
3637 **********************************************************************
3638 */
arcmsr_polling_hbd_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3639 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3640 {
3641 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3642 struct CommandControlBlock *srb;
3643 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3644 u_int32_t outbound_write_pointer;
3645 u_int16_t error, doneq_index;
3646
3647 polling_ccb_retry:
3648 poll_count++;
3649 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3650 while(1) {
3651 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3652 doneq_index = phbdmu->doneq_index;
3653 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3654 if(poll_srb_done) {
3655 break;/*chip FIFO no ccb for completion already*/
3656 } else {
3657 UDELAY(25000);
3658 if ((poll_count > 100) && (poll_srb != NULL)) {
3659 break;
3660 }
3661 if (acb->srboutstandingcount == 0) {
3662 break;
3663 }
3664 goto polling_ccb_retry;
3665 }
3666 }
3667 doneq_index = arcmsr_get_doneq_index(phbdmu);
3668 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3669 /* check if command done with no error*/
3670 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3671 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3672 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3673 if (poll_srb != NULL)
3674 poll_srb_done = (srb == poll_srb) ? 1:0;
3675 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3676 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3677 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3678 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3679 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3680 arcmsr_srb_complete(srb, 1);
3681 continue;
3682 }
3683 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3684 , acb->pci_unit, srb, acb->srboutstandingcount);
3685 continue;
3686 }
3687 arcmsr_report_srb_state(acb, srb, error);
3688 } /*drain reply FIFO*/
3689 }
3690 /*
3691 **********************************************************************
3692 **
3693 **********************************************************************
3694 */
arcmsr_polling_hbe_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3695 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3696 {
3697 struct CommandControlBlock *srb;
3698 u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
3699 u_int16_t error, cmdSMID;
3700
3701 polling_ccb_retry:
3702 poll_count++;
3703 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3704 while(1) {
3705 doneq_index = acb->doneq_index;
3706 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3707 if(poll_srb_done) {
3708 break;/*chip FIFO no ccb for completion already*/
3709 } else {
3710 UDELAY(25000);
3711 if ((poll_count > 100) && (poll_srb != NULL)) {
3712 break;
3713 }
3714 if (acb->srboutstandingcount == 0) {
3715 break;
3716 }
3717 goto polling_ccb_retry;
3718 }
3719 }
3720 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3721 doneq_index++;
3722 if (doneq_index >= acb->completionQ_entry)
3723 doneq_index = 0;
3724 acb->doneq_index = doneq_index;
3725 srb = acb->psrb_pool[cmdSMID];
3726 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3727 if (poll_srb != NULL)
3728 poll_srb_done = (srb == poll_srb) ? 1:0;
3729 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3730 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3731 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3732 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3733 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3734 arcmsr_srb_complete(srb, 1);
3735 continue;
3736 }
3737 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3738 , acb->pci_unit, srb, acb->srboutstandingcount);
3739 continue;
3740 }
3741 arcmsr_report_srb_state(acb, srb, error);
3742 } /*drain reply FIFO*/
3743 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
3744 }
3745 /*
3746 **********************************************************************
3747 **********************************************************************
3748 */
arcmsr_polling_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3749 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3750 {
3751 switch (acb->adapter_type) {
3752 case ACB_ADAPTER_TYPE_A:
3753 arcmsr_polling_hba_srbdone(acb, poll_srb);
3754 break;
3755 case ACB_ADAPTER_TYPE_B:
3756 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3757 break;
3758 case ACB_ADAPTER_TYPE_C:
3759 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3760 break;
3761 case ACB_ADAPTER_TYPE_D:
3762 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3763 break;
3764 case ACB_ADAPTER_TYPE_E:
3765 case ACB_ADAPTER_TYPE_F:
3766 arcmsr_polling_hbe_srbdone(acb, poll_srb);
3767 break;
3768 }
3769 }
3770 /*
3771 **********************************************************************
3772 **********************************************************************
3773 */
arcmsr_get_hba_config(struct AdapterControlBlock * acb)3774 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3775 {
3776 char *acb_firm_model = acb->firm_model;
3777 char *acb_firm_version = acb->firm_version;
3778 char *acb_device_map = acb->device_map;
3779 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3780 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3781 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3782 int i;
3783
3784 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3785 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3786 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3787 }
3788 i = 0;
3789 while(i < 8) {
3790 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3791 /* 8 bytes firm_model, 15, 60-67*/
3792 acb_firm_model++;
3793 i++;
3794 }
3795 i=0;
3796 while(i < 16) {
3797 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3798 /* 16 bytes firm_version, 17, 68-83*/
3799 acb_firm_version++;
3800 i++;
3801 }
3802 i=0;
3803 while(i < 16) {
3804 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3805 acb_device_map++;
3806 i++;
3807 }
3808 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3809 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3810 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3811 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3812 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3813 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3814 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3815 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3816 else
3817 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3818 }
3819 /*
3820 **********************************************************************
3821 **********************************************************************
3822 */
arcmsr_get_hbb_config(struct AdapterControlBlock * acb)3823 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3824 {
3825 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3826 char *acb_firm_model = acb->firm_model;
3827 char *acb_firm_version = acb->firm_version;
3828 char *acb_device_map = acb->device_map;
3829 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3830 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3831 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3832 int i;
3833
3834 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3835 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3836 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3837 }
3838 i = 0;
3839 while(i < 8) {
3840 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3841 /* 8 bytes firm_model, 15, 60-67*/
3842 acb_firm_model++;
3843 i++;
3844 }
3845 i = 0;
3846 while(i < 16) {
3847 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3848 /* 16 bytes firm_version, 17, 68-83*/
3849 acb_firm_version++;
3850 i++;
3851 }
3852 i = 0;
3853 while(i < 16) {
3854 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3855 acb_device_map++;
3856 i++;
3857 }
3858 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3859 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3860 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3861 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3862 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3863 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3864 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3865 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3866 else
3867 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3868 }
3869 /*
3870 **********************************************************************
3871 **********************************************************************
3872 */
arcmsr_get_hbc_config(struct AdapterControlBlock * acb)3873 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3874 {
3875 char *acb_firm_model = acb->firm_model;
3876 char *acb_firm_version = acb->firm_version;
3877 char *acb_device_map = acb->device_map;
3878 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3879 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3880 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3881 int i;
3882
3883 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3884 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3885 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3886 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3887 }
3888 i = 0;
3889 while(i < 8) {
3890 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3891 /* 8 bytes firm_model, 15, 60-67*/
3892 acb_firm_model++;
3893 i++;
3894 }
3895 i = 0;
3896 while(i < 16) {
3897 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3898 /* 16 bytes firm_version, 17, 68-83*/
3899 acb_firm_version++;
3900 i++;
3901 }
3902 i = 0;
3903 while(i < 16) {
3904 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3905 acb_device_map++;
3906 i++;
3907 }
3908 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3909 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3910 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3911 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3912 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3913 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3914 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3915 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3916 else
3917 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3918 }
3919 /*
3920 **********************************************************************
3921 **********************************************************************
3922 */
arcmsr_get_hbd_config(struct AdapterControlBlock * acb)3923 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3924 {
3925 char *acb_firm_model = acb->firm_model;
3926 char *acb_firm_version = acb->firm_version;
3927 char *acb_device_map = acb->device_map;
3928 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3929 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3930 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3931 int i;
3932
3933 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3934 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3935 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3936 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3937 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3938 }
3939 i = 0;
3940 while(i < 8) {
3941 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3942 /* 8 bytes firm_model, 15, 60-67*/
3943 acb_firm_model++;
3944 i++;
3945 }
3946 i = 0;
3947 while(i < 16) {
3948 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3949 /* 16 bytes firm_version, 17, 68-83*/
3950 acb_firm_version++;
3951 i++;
3952 }
3953 i = 0;
3954 while(i < 16) {
3955 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3956 acb_device_map++;
3957 i++;
3958 }
3959 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3960 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3961 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3962 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3963 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3964 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3965 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3966 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3967 else
3968 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3969 }
3970 /*
3971 **********************************************************************
3972 **********************************************************************
3973 */
arcmsr_get_hbe_config(struct AdapterControlBlock * acb)3974 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
3975 {
3976 char *acb_firm_model = acb->firm_model;
3977 char *acb_firm_version = acb->firm_version;
3978 char *acb_device_map = acb->device_map;
3979 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3980 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3981 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3982 int i;
3983
3984 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3985 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3986 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3987 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3988 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3989 }
3990
3991 i = 0;
3992 while(i < 8) {
3993 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3994 /* 8 bytes firm_model, 15, 60-67*/
3995 acb_firm_model++;
3996 i++;
3997 }
3998 i = 0;
3999 while(i < 16) {
4000 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
4001 /* 16 bytes firm_version, 17, 68-83*/
4002 acb_firm_version++;
4003 i++;
4004 }
4005 i = 0;
4006 while(i < 16) {
4007 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
4008 acb_device_map++;
4009 i++;
4010 }
4011 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4012 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
4013 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
4014 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
4015 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
4016 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
4017 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4018 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4019 else
4020 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4021 }
4022 /*
4023 **********************************************************************
4024 **********************************************************************
4025 */
arcmsr_get_hbf_config(struct AdapterControlBlock * acb)4026 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb)
4027 {
4028 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model;
4029 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version;
4030 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map;
4031 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/
4032 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/
4033 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET;
4034 int i;
4035
4036 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
4037 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4038 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4039 if(!arcmsr_hbe_wait_msgint_ready(acb))
4040 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
4041
4042 i = 0;
4043 while(i < 2) {
4044 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model];
4045 /* 8 bytes firm_model, 15, 60-67*/
4046 acb_firm_model++;
4047 iop_firm_model++;
4048 i++;
4049 }
4050 i = 0;
4051 while(i < 4) {
4052 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version];
4053 /* 16 bytes firm_version, 17, 68-83*/
4054 acb_firm_version++;
4055 iop_firm_version++;
4056 i++;
4057 }
4058 i = 0;
4059 while(i < 4) {
4060 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map];
4061 acb_device_map++;
4062 iop_device_map++;
4063 i++;
4064 }
4065 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4066 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/
4067 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/
4068 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/
4069 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/
4070 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/
4071 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4072 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4073 else
4074 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4075 }
4076 /*
4077 **********************************************************************
4078 **********************************************************************
4079 */
arcmsr_get_firmware_spec(struct AdapterControlBlock * acb)4080 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
4081 {
4082 switch (acb->adapter_type) {
4083 case ACB_ADAPTER_TYPE_A:
4084 arcmsr_get_hba_config(acb);
4085 break;
4086 case ACB_ADAPTER_TYPE_B:
4087 arcmsr_get_hbb_config(acb);
4088 break;
4089 case ACB_ADAPTER_TYPE_C:
4090 arcmsr_get_hbc_config(acb);
4091 break;
4092 case ACB_ADAPTER_TYPE_D:
4093 arcmsr_get_hbd_config(acb);
4094 break;
4095 case ACB_ADAPTER_TYPE_E:
4096 arcmsr_get_hbe_config(acb);
4097 break;
4098 case ACB_ADAPTER_TYPE_F:
4099 arcmsr_get_hbf_config(acb);
4100 break;
4101 }
4102 }
4103 /*
4104 **********************************************************************
4105 **********************************************************************
4106 */
arcmsr_wait_firmware_ready(struct AdapterControlBlock * acb)4107 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
4108 {
4109 int timeout=0;
4110
4111 switch (acb->adapter_type) {
4112 case ACB_ADAPTER_TYPE_A: {
4113 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
4114 {
4115 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4116 {
4117 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
4118 return;
4119 }
4120 UDELAY(15000); /* wait 15 milli-seconds */
4121 }
4122 }
4123 break;
4124 case ACB_ADAPTER_TYPE_B: {
4125 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4126 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
4127 {
4128 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4129 {
4130 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
4131 return;
4132 }
4133 UDELAY(15000); /* wait 15 milli-seconds */
4134 }
4135 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
4136 }
4137 break;
4138 case ACB_ADAPTER_TYPE_C: {
4139 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
4140 {
4141 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4142 {
4143 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4144 return;
4145 }
4146 UDELAY(15000); /* wait 15 milli-seconds */
4147 }
4148 }
4149 break;
4150 case ACB_ADAPTER_TYPE_D: {
4151 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
4152 {
4153 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4154 {
4155 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4156 return;
4157 }
4158 UDELAY(15000); /* wait 15 milli-seconds */
4159 }
4160 }
4161 break;
4162 case ACB_ADAPTER_TYPE_E:
4163 case ACB_ADAPTER_TYPE_F: {
4164 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
4165 {
4166 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
4167 {
4168 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4169 return;
4170 }
4171 UDELAY(15000); /* wait 15 milli-seconds */
4172 }
4173 }
4174 break;
4175 }
4176 }
4177 /*
4178 **********************************************************************
4179 **********************************************************************
4180 */
arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock * acb)4181 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
4182 {
4183 u_int32_t outbound_doorbell;
4184
4185 switch (acb->adapter_type) {
4186 case ACB_ADAPTER_TYPE_A: {
4187 /* empty doorbell Qbuffer if door bell ringed */
4188 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
4189 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4190 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
4191 }
4192 break;
4193 case ACB_ADAPTER_TYPE_B: {
4194 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4195 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
4196 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
4197 /* let IOP know data has been read */
4198 }
4199 break;
4200 case ACB_ADAPTER_TYPE_C: {
4201 /* empty doorbell Qbuffer if door bell ringed */
4202 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
4203 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */
4204 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
4205 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
4206 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
4207 }
4208 break;
4209 case ACB_ADAPTER_TYPE_D: {
4210 /* empty doorbell Qbuffer if door bell ringed */
4211 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4212 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4213 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4214 }
4215 break;
4216 case ACB_ADAPTER_TYPE_E:
4217 case ACB_ADAPTER_TYPE_F: {
4218 /* empty doorbell Qbuffer if door bell ringed */
4219 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4220 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
4221 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4222 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4223 }
4224 break;
4225 }
4226 }
4227 /*
4228 ************************************************************************
4229 ************************************************************************
4230 */
arcmsr_iop_confirm(struct AdapterControlBlock * acb)4231 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
4232 {
4233 unsigned long srb_phyaddr;
4234 u_int32_t srb_phyaddr_hi32;
4235 u_int32_t srb_phyaddr_lo32;
4236
4237 /*
4238 ********************************************************************
4239 ** here we need to tell iop 331 our freesrb.HighPart
4240 ** if freesrb.HighPart is not zero
4241 ********************************************************************
4242 */
4243 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
4244 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
4245 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
4246 switch (acb->adapter_type) {
4247 case ACB_ADAPTER_TYPE_A: {
4248 if(srb_phyaddr_hi32 != 0) {
4249 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4250 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4251 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4252 if(!arcmsr_hba_wait_msgint_ready(acb)) {
4253 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4254 return FALSE;
4255 }
4256 }
4257 }
4258 break;
4259 /*
4260 ***********************************************************************
4261 ** if adapter type B, set window of "post command Q"
4262 ***********************************************************************
4263 */
4264 case ACB_ADAPTER_TYPE_B: {
4265 u_int32_t post_queue_phyaddr;
4266 struct HBB_MessageUnit *phbbmu;
4267
4268 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4269 phbbmu->postq_index = 0;
4270 phbbmu->doneq_index = 0;
4271 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
4272 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4273 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
4274 return FALSE;
4275 }
4276 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
4277 + offsetof(struct HBB_MessageUnit, post_qbuffer);
4278 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4279 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
4280 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
4281 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
4282 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
4283 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
4284 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4285 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
4286 return FALSE;
4287 }
4288 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
4289 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4290 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
4291 return FALSE;
4292 }
4293 }
4294 break;
4295 case ACB_ADAPTER_TYPE_C: {
4296 if(srb_phyaddr_hi32 != 0) {
4297 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4298 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4299 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4300 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
4301 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
4302 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4303 return FALSE;
4304 }
4305 }
4306 }
4307 break;
4308 case ACB_ADAPTER_TYPE_D: {
4309 u_int32_t post_queue_phyaddr, done_queue_phyaddr;
4310 struct HBD_MessageUnit0 *phbdmu;
4311
4312 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4313 phbdmu->postq_index = 0;
4314 phbdmu->doneq_index = 0x40FF;
4315 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4316 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
4317 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4318 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
4319 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4320 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4321 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
4322 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
4323 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
4324 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4325 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
4326 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4327 return FALSE;
4328 }
4329 }
4330 break;
4331 case ACB_ADAPTER_TYPE_E: {
4332 u_int32_t cdb_phyaddr_lo32;
4333 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4334 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4335 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
4336 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
4337 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
4338 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
4339 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4340 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
4341 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
4342 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
4343 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4344 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4345 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4346 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4347 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4348 return FALSE;
4349 }
4350 }
4351 break;
4352 case ACB_ADAPTER_TYPE_F: {
4353 u_int32_t cdb_phyaddr_lo32;
4354 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4355 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4356 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4357 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32;
4358 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32;
4359 acb->msgcode_rwbuffer[4] = SRB_SIZE;
4360 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4361 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32;
4362 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32;
4363 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE;
4364 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4365 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4366 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4367 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4368 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4369 return FALSE;
4370 }
4371 }
4372 break;
4373 }
4374 return (TRUE);
4375 }
4376 /*
4377 ************************************************************************
4378 ************************************************************************
4379 */
arcmsr_enable_eoi_mode(struct AdapterControlBlock * acb)4380 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4381 {
4382 if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
4383 {
4384 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4385 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
4386 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4387 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
4388 return;
4389 }
4390 }
4391 }
4392 /*
4393 **********************************************************************
4394 **********************************************************************
4395 */
arcmsr_iop_init(struct AdapterControlBlock * acb)4396 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4397 {
4398 u_int32_t intmask_org;
4399
4400 /* disable all outbound interrupt */
4401 intmask_org = arcmsr_disable_allintr(acb);
4402 arcmsr_wait_firmware_ready(acb);
4403 arcmsr_iop_confirm(acb);
4404 arcmsr_get_firmware_spec(acb);
4405 /*start background rebuild*/
4406 arcmsr_start_adapter_bgrb(acb);
4407 /* empty doorbell Qbuffer if door bell ringed */
4408 arcmsr_clear_doorbell_queue_buffer(acb);
4409 arcmsr_enable_eoi_mode(acb);
4410 /* enable outbound Post Queue, outbound doorbell Interrupt */
4411 arcmsr_enable_allintr(acb, intmask_org);
4412 acb->acb_flags |= ACB_F_IOP_INITED;
4413 }
4414 /*
4415 **********************************************************************
4416 **********************************************************************
4417 */
arcmsr_map_free_srb(void * arg,bus_dma_segment_t * segs,int nseg,int error)4418 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4419 {
4420 struct AdapterControlBlock *acb = arg;
4421 struct CommandControlBlock *srb_tmp;
4422 u_int32_t i;
4423 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
4424
4425 acb->srb_phyaddr.phyaddr = srb_phyaddr;
4426 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
4427 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4428 if(bus_dmamap_create(acb->dm_segs_dmat,
4429 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4430 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4431 printf("arcmsr%d:"
4432 " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4433 return;
4434 }
4435 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4436 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F))
4437 {
4438 srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4439 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4440 }
4441 else
4442 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4443 srb_tmp->acb = acb;
4444 srb_tmp->smid = i << 16;
4445 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4446 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4447 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4448 }
4449 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4450 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4451 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) {
4452 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4453 acb->completeQ_phys = srb_phyaddr;
4454 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE);
4455 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE);
4456 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100);
4457 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200);
4458 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
4459 }
4460 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4461 }
4462 /*
4463 ************************************************************************
4464 ************************************************************************
4465 */
arcmsr_free_resource(struct AdapterControlBlock * acb)4466 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4467 {
4468 /* remove the control device */
4469 if(acb->ioctl_dev != NULL) {
4470 destroy_dev(acb->ioctl_dev);
4471 }
4472 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
4473 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
4474 bus_dma_tag_destroy(acb->srb_dmat);
4475 bus_dma_tag_destroy(acb->dm_segs_dmat);
4476 bus_dma_tag_destroy(acb->parent_dmat);
4477 }
4478 /*
4479 ************************************************************************
4480 ************************************************************************
4481 */
arcmsr_mutex_init(struct AdapterControlBlock * acb)4482 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
4483 {
4484 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
4485 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
4486 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
4487 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
4488 }
4489 /*
4490 ************************************************************************
4491 ************************************************************************
4492 */
arcmsr_mutex_destroy(struct AdapterControlBlock * acb)4493 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
4494 {
4495 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
4496 ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
4497 ARCMSR_LOCK_DESTROY(&acb->srb_lock);
4498 ARCMSR_LOCK_DESTROY(&acb->isr_lock);
4499 }
4500 /*
4501 ************************************************************************
4502 ************************************************************************
4503 */
arcmsr_initialize(device_t dev)4504 static u_int32_t arcmsr_initialize(device_t dev)
4505 {
4506 struct AdapterControlBlock *acb = device_get_softc(dev);
4507 u_int16_t pci_command;
4508 int i, j,max_coherent_size;
4509 u_int32_t vendor_dev_id;
4510
4511 vendor_dev_id = pci_get_devid(dev);
4512 acb->vendor_device_id = vendor_dev_id;
4513 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4514 switch (vendor_dev_id) {
4515 case PCIDevVenIDARC1880:
4516 case PCIDevVenIDARC1882:
4517 case PCIDevVenIDARC1213:
4518 case PCIDevVenIDARC1223: {
4519 acb->adapter_type = ACB_ADAPTER_TYPE_C;
4520 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4521 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4522 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
4523 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4524 else
4525 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4526 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4527 }
4528 break;
4529 case PCIDevVenIDARC1884:
4530 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4531 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4532 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4533 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4534 break;
4535 case PCIDevVenIDARC1886_:
4536 case PCIDevVenIDARC1886:
4537 acb->adapter_type = ACB_ADAPTER_TYPE_F;
4538 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4539 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE;
4540 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4541 break;
4542 case PCIDevVenIDARC1214: {
4543 acb->adapter_type = ACB_ADAPTER_TYPE_D;
4544 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4545 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4546 }
4547 break;
4548 case PCIDevVenIDARC1200:
4549 case PCIDevVenIDARC1201: {
4550 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4551 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4552 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4553 }
4554 break;
4555 case PCIDevVenIDARC1203: {
4556 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4557 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4558 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4559 }
4560 break;
4561 case PCIDevVenIDARC1110:
4562 case PCIDevVenIDARC1120:
4563 case PCIDevVenIDARC1130:
4564 case PCIDevVenIDARC1160:
4565 case PCIDevVenIDARC1170:
4566 case PCIDevVenIDARC1210:
4567 case PCIDevVenIDARC1220:
4568 case PCIDevVenIDARC1230:
4569 case PCIDevVenIDARC1231:
4570 case PCIDevVenIDARC1260:
4571 case PCIDevVenIDARC1261:
4572 case PCIDevVenIDARC1270:
4573 case PCIDevVenIDARC1280:
4574 case PCIDevVenIDARC1212:
4575 case PCIDevVenIDARC1222:
4576 case PCIDevVenIDARC1380:
4577 case PCIDevVenIDARC1381:
4578 case PCIDevVenIDARC1680:
4579 case PCIDevVenIDARC1681: {
4580 acb->adapter_type = ACB_ADAPTER_TYPE_A;
4581 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4582 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4583 }
4584 break;
4585 default: {
4586 printf("arcmsr%d:"
4587 " unknown RAID adapter type \n", device_get_unit(dev));
4588 return ENOMEM;
4589 }
4590 }
4591 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev),
4592 /*alignemnt*/ 1,
4593 /*boundary*/ 0,
4594 /*lowaddr*/ BUS_SPACE_MAXADDR,
4595 /*highaddr*/ BUS_SPACE_MAXADDR,
4596 /*filter*/ NULL,
4597 /*filterarg*/ NULL,
4598 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
4599 /*nsegments*/ BUS_SPACE_UNRESTRICTED,
4600 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4601 /*flags*/ 0,
4602 /*lockfunc*/ NULL,
4603 /*lockarg*/ NULL,
4604 &acb->parent_dmat) != 0)
4605 {
4606 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4607 return ENOMEM;
4608 }
4609
4610 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4611 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4612 /*alignment*/ 1,
4613 /*boundary*/ 0,
4614 #ifdef PAE
4615 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4616 #else
4617 /*lowaddr*/ BUS_SPACE_MAXADDR,
4618 #endif
4619 /*highaddr*/ BUS_SPACE_MAXADDR,
4620 /*filter*/ NULL,
4621 /*filterarg*/ NULL,
4622 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4623 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES,
4624 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4625 /*flags*/ 0,
4626 /*lockfunc*/ busdma_lock_mutex,
4627 /*lockarg*/ &acb->isr_lock,
4628 &acb->dm_segs_dmat) != 0)
4629 {
4630 bus_dma_tag_destroy(acb->parent_dmat);
4631 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4632 return ENOMEM;
4633 }
4634
4635 /* DMA tag for our srb structures.... Allocate the freesrb memory */
4636 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4637 /*alignment*/ 0x20,
4638 /*boundary*/ 0,
4639 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4640 /*highaddr*/ BUS_SPACE_MAXADDR,
4641 /*filter*/ NULL,
4642 /*filterarg*/ NULL,
4643 /*maxsize*/ max_coherent_size,
4644 /*nsegments*/ 1,
4645 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4646 /*flags*/ 0,
4647 /*lockfunc*/ NULL,
4648 /*lockarg*/ NULL,
4649 &acb->srb_dmat) != 0)
4650 {
4651 bus_dma_tag_destroy(acb->dm_segs_dmat);
4652 bus_dma_tag_destroy(acb->parent_dmat);
4653 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4654 return ENXIO;
4655 }
4656 /* Allocation for our srbs */
4657 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4658 bus_dma_tag_destroy(acb->srb_dmat);
4659 bus_dma_tag_destroy(acb->dm_segs_dmat);
4660 bus_dma_tag_destroy(acb->parent_dmat);
4661 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4662 return ENXIO;
4663 }
4664 /* And permanently map them */
4665 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4666 bus_dma_tag_destroy(acb->srb_dmat);
4667 bus_dma_tag_destroy(acb->dm_segs_dmat);
4668 bus_dma_tag_destroy(acb->parent_dmat);
4669 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4670 return ENXIO;
4671 }
4672 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4673 pci_command |= PCIM_CMD_BUSMASTEREN;
4674 pci_command |= PCIM_CMD_PERRESPEN;
4675 pci_command |= PCIM_CMD_MWRICEN;
4676 /* Enable Busmaster */
4677 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4678 switch(acb->adapter_type) {
4679 case ACB_ADAPTER_TYPE_A: {
4680 u_int32_t rid0 = PCIR_BAR(0);
4681 vm_offset_t mem_base0;
4682
4683 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4684 if(acb->sys_res_arcmsr[0] == NULL) {
4685 arcmsr_free_resource(acb);
4686 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4687 return ENOMEM;
4688 }
4689 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4690 arcmsr_free_resource(acb);
4691 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4692 return ENXIO;
4693 }
4694 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4695 if(mem_base0 == 0) {
4696 arcmsr_free_resource(acb);
4697 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4698 return ENXIO;
4699 }
4700 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4701 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4702 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4703 acb->rid[0] = rid0;
4704 }
4705 break;
4706 case ACB_ADAPTER_TYPE_B: {
4707 struct HBB_MessageUnit *phbbmu;
4708 struct CommandControlBlock *freesrb;
4709 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4710 vm_offset_t mem_base[]={0,0};
4711 for(i=0; i < 2; i++) {
4712 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
4713 if(acb->sys_res_arcmsr[i] == NULL) {
4714 arcmsr_free_resource(acb);
4715 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4716 return ENOMEM;
4717 }
4718 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4719 arcmsr_free_resource(acb);
4720 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4721 return ENXIO;
4722 }
4723 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4724 if(mem_base[i] == 0) {
4725 arcmsr_free_resource(acb);
4726 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4727 return ENXIO;
4728 }
4729 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4730 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4731 }
4732 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4733 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4734 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4735 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4736 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4737 if (vendor_dev_id == PCIDevVenIDARC1203) {
4738 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4739 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4740 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4741 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4742 } else {
4743 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4744 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4745 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4746 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4747 }
4748 acb->rid[0] = rid[0];
4749 acb->rid[1] = rid[1];
4750 }
4751 break;
4752 case ACB_ADAPTER_TYPE_C: {
4753 u_int32_t rid0 = PCIR_BAR(1);
4754 vm_offset_t mem_base0;
4755
4756 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4757 if(acb->sys_res_arcmsr[0] == NULL) {
4758 arcmsr_free_resource(acb);
4759 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4760 return ENOMEM;
4761 }
4762 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4763 arcmsr_free_resource(acb);
4764 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4765 return ENXIO;
4766 }
4767 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4768 if(mem_base0 == 0) {
4769 arcmsr_free_resource(acb);
4770 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4771 return ENXIO;
4772 }
4773 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4774 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4775 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4776 acb->rid[0] = rid0;
4777 }
4778 break;
4779 case ACB_ADAPTER_TYPE_D: {
4780 struct HBD_MessageUnit0 *phbdmu;
4781 u_int32_t rid0 = PCIR_BAR(0);
4782 vm_offset_t mem_base0;
4783
4784 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4785 if(acb->sys_res_arcmsr[0] == NULL) {
4786 arcmsr_free_resource(acb);
4787 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4788 return ENOMEM;
4789 }
4790 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4791 arcmsr_free_resource(acb);
4792 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4793 return ENXIO;
4794 }
4795 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4796 if(mem_base0 == 0) {
4797 arcmsr_free_resource(acb);
4798 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4799 return ENXIO;
4800 }
4801 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4802 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4803 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4804 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4805 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4806 acb->rid[0] = rid0;
4807 }
4808 break;
4809 case ACB_ADAPTER_TYPE_E: {
4810 u_int32_t rid0 = PCIR_BAR(1);
4811 vm_offset_t mem_base0;
4812
4813 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4814 if(acb->sys_res_arcmsr[0] == NULL) {
4815 arcmsr_free_resource(acb);
4816 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4817 return ENOMEM;
4818 }
4819 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4820 arcmsr_free_resource(acb);
4821 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4822 return ENXIO;
4823 }
4824 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4825 if(mem_base0 == 0) {
4826 arcmsr_free_resource(acb);
4827 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4828 return ENXIO;
4829 }
4830 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4831 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4832 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4833 acb->doneq_index = 0;
4834 acb->in_doorbell = 0;
4835 acb->out_doorbell = 0;
4836 acb->rid[0] = rid0;
4837 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4838 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4839 }
4840 break;
4841 case ACB_ADAPTER_TYPE_F: {
4842 u_int32_t rid0 = PCIR_BAR(0);
4843 vm_offset_t mem_base0;
4844 unsigned long host_buffer_dma;
4845
4846 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4847 if(acb->sys_res_arcmsr[0] == NULL) {
4848 arcmsr_free_resource(acb);
4849 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4850 return ENOMEM;
4851 }
4852 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4853 arcmsr_free_resource(acb);
4854 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4855 return ENXIO;
4856 }
4857 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4858 if(mem_base0 == 0) {
4859 arcmsr_free_resource(acb);
4860 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4861 return ENXIO;
4862 }
4863 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4864 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4865 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4866 acb->doneq_index = 0;
4867 acb->in_doorbell = 0;
4868 acb->out_doorbell = 0;
4869 acb->rid[0] = rid0;
4870 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4871 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4872 arcmsr_wait_firmware_ready(acb);
4873 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE;
4874 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */
4875 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */
4876 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */
4877 }
4878 break;
4879 }
4880 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4881 arcmsr_free_resource(acb);
4882 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4883 return ENXIO;
4884 }
4885 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4886 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4887 /*
4888 ********************************************************************
4889 ** init raid volume state
4890 ********************************************************************
4891 */
4892 for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4893 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4894 acb->devstate[i][j] = ARECA_RAID_GONE;
4895 }
4896 }
4897 arcmsr_iop_init(acb);
4898 return(0);
4899 }
4900
arcmsr_setup_msix(struct AdapterControlBlock * acb)4901 static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
4902 {
4903 int i;
4904
4905 for (i = 0; i < acb->msix_vectors; i++) {
4906 acb->irq_id[i] = 1 + i;
4907 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
4908 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
4909 if (acb->irqres[i] == NULL) {
4910 printf("arcmsr: Can't allocate MSI-X resource\n");
4911 goto irq_alloc_failed;
4912 }
4913 if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
4914 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
4915 acb, &acb->ih[i])) {
4916 printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
4917 goto irq_alloc_failed;
4918 }
4919 }
4920 printf("arcmsr: MSI-X INT enabled\n");
4921 acb->acb_flags |= ACB_F_MSIX_ENABLED;
4922 return TRUE;
4923
4924 irq_alloc_failed:
4925 arcmsr_teardown_intr(acb->pci_dev, acb);
4926 return FALSE;
4927 }
4928
4929 /*
4930 ************************************************************************
4931 ************************************************************************
4932 */
arcmsr_attach(device_t dev)4933 static int arcmsr_attach(device_t dev)
4934 {
4935 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4936 u_int32_t unit=device_get_unit(dev);
4937 struct ccb_setasync csa;
4938 struct cam_devq *devq; /* Device Queue to use for this SIM */
4939 struct resource *irqres;
4940
4941 if(acb == NULL) {
4942 printf("arcmsr%d: cannot allocate softc\n", unit);
4943 return (ENOMEM);
4944 }
4945 arcmsr_mutex_init(acb);
4946 acb->pci_dev = dev;
4947 acb->pci_unit = unit;
4948 if(arcmsr_initialize(dev)) {
4949 printf("arcmsr%d: initialize failure!\n", unit);
4950 goto initialize_failed;
4951 }
4952 /* After setting up the adapter, map our interrupt */
4953 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
4954 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
4955 if (arcmsr_setup_msix(acb) == TRUE)
4956 goto irqx;
4957 }
4958 acb->irq_id[0] = 0;
4959 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
4960 if(irqres == NULL ||
4961 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
4962 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4963 goto setup_intr_failed;
4964 }
4965 acb->irqres[0] = irqres;
4966 irqx:
4967 /*
4968 * Now let the CAM generic SCSI layer find the SCSI devices on
4969 * the bus * start queue to reset to the idle loop. *
4970 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
4971 * max_sim_transactions
4972 */
4973 devq = cam_simq_alloc(acb->maxOutstanding);
4974 if(devq == NULL) {
4975 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4976 goto simq_alloc_failed;
4977 }
4978 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4979 if(acb->psim == NULL) {
4980 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4981 goto sim_alloc_failed;
4982 }
4983 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4984 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4985 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4986 goto xpt_bus_failed;
4987 }
4988 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4989 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4990 goto xpt_path_failed;
4991 }
4992 /*
4993 ****************************************************
4994 */
4995 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4996 csa.ccb_h.func_code = XPT_SASYNC_CB;
4997 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4998 csa.callback = arcmsr_async;
4999 csa.callback_arg = acb->psim;
5000 xpt_action((union ccb *)&csa);
5001 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5002 /* Create the control device. */
5003 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
5004
5005 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
5006 arcmsr_callout_init(&acb->devmap_callout);
5007 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
5008 return (0);
5009 xpt_path_failed:
5010 xpt_bus_deregister(cam_sim_path(acb->psim));
5011 xpt_bus_failed:
5012 cam_sim_free(acb->psim, /* free_simq */ TRUE);
5013 sim_alloc_failed:
5014 cam_simq_free(devq);
5015 simq_alloc_failed:
5016 arcmsr_teardown_intr(dev, acb);
5017 setup_intr_failed:
5018 arcmsr_free_resource(acb);
5019 initialize_failed:
5020 arcmsr_mutex_destroy(acb);
5021 return ENXIO;
5022 }
5023
5024 /*
5025 ************************************************************************
5026 ************************************************************************
5027 */
arcmsr_probe(device_t dev)5028 static int arcmsr_probe(device_t dev)
5029 {
5030 u_int32_t id;
5031 u_int16_t sub_device_id;
5032 static char buf[256];
5033 char x_type[]={"unknown"};
5034 char *type;
5035 int raid6 = 1;
5036
5037 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
5038 return (ENXIO);
5039 }
5040 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
5041 switch(id = pci_get_devid(dev)) {
5042 case PCIDevVenIDARC1110:
5043 case PCIDevVenIDARC1200:
5044 case PCIDevVenIDARC1201:
5045 case PCIDevVenIDARC1210:
5046 raid6 = 0;
5047 /*FALLTHRU*/
5048 case PCIDevVenIDARC1120:
5049 case PCIDevVenIDARC1130:
5050 case PCIDevVenIDARC1160:
5051 case PCIDevVenIDARC1170:
5052 case PCIDevVenIDARC1220:
5053 case PCIDevVenIDARC1230:
5054 case PCIDevVenIDARC1231:
5055 case PCIDevVenIDARC1260:
5056 case PCIDevVenIDARC1261:
5057 case PCIDevVenIDARC1270:
5058 case PCIDevVenIDARC1280:
5059 type = "SATA 3G";
5060 break;
5061 case PCIDevVenIDARC1212:
5062 case PCIDevVenIDARC1222:
5063 case PCIDevVenIDARC1380:
5064 case PCIDevVenIDARC1381:
5065 case PCIDevVenIDARC1680:
5066 case PCIDevVenIDARC1681:
5067 type = "SAS 3G";
5068 break;
5069 case PCIDevVenIDARC1880:
5070 case PCIDevVenIDARC1882:
5071 case PCIDevVenIDARC1213:
5072 case PCIDevVenIDARC1223:
5073 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
5074 (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
5075 (sub_device_id == ARECA_SUB_DEV_ID_1226))
5076 type = "SAS 12G";
5077 else
5078 type = "SAS 6G";
5079 break;
5080 case PCIDevVenIDARC1884:
5081 type = "SAS 12G";
5082 break;
5083 case PCIDevVenIDARC1886_:
5084 case PCIDevVenIDARC1886:
5085 type = "NVME,SAS-12G,SATA-6G";
5086 break;
5087 case PCIDevVenIDARC1214:
5088 case PCIDevVenIDARC1203:
5089 type = "SATA 6G";
5090 break;
5091 default:
5092 type = x_type;
5093 raid6 = 0;
5094 break;
5095 }
5096 if(type == x_type)
5097 return(ENXIO);
5098 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
5099 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
5100 device_set_desc_copy(dev, buf);
5101 return (BUS_PROBE_DEFAULT);
5102 }
5103 /*
5104 ************************************************************************
5105 ************************************************************************
5106 */
arcmsr_shutdown(device_t dev)5107 static int arcmsr_shutdown(device_t dev)
5108 {
5109 u_int32_t i;
5110 u_int32_t intmask_org;
5111 struct CommandControlBlock *srb;
5112 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5113
5114 /* stop adapter background rebuild */
5115 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5116 /* disable all outbound interrupt */
5117 intmask_org = arcmsr_disable_allintr(acb);
5118 arcmsr_stop_adapter_bgrb(acb);
5119 arcmsr_flush_adapter_cache(acb);
5120 /* abort all outstanding command */
5121 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
5122 acb->acb_flags &= ~ACB_F_IOP_INITED;
5123 if(acb->srboutstandingcount != 0) {
5124 /*clear and abort all outbound posted Q*/
5125 arcmsr_done4abort_postqueue(acb);
5126 /* talk to iop 331 outstanding command aborted*/
5127 arcmsr_abort_allcmd(acb);
5128 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
5129 srb = acb->psrb_pool[i];
5130 if(srb->srb_state == ARCMSR_SRB_START) {
5131 srb->srb_state = ARCMSR_SRB_ABORTED;
5132 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
5133 arcmsr_srb_complete(srb, 1);
5134 }
5135 }
5136 }
5137 acb->srboutstandingcount = 0;
5138 acb->workingsrb_doneindex = 0;
5139 acb->workingsrb_startindex = 0;
5140 acb->pktRequestCount = 0;
5141 acb->pktReturnCount = 0;
5142 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5143 return (0);
5144 }
5145 /*
5146 ************************************************************************
5147 ************************************************************************
5148 */
arcmsr_teardown_intr(device_t dev,struct AdapterControlBlock * acb)5149 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
5150 {
5151 int i;
5152
5153 if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
5154 for (i = 0; i < acb->msix_vectors; i++) {
5155 if (acb->ih[i])
5156 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
5157 if (acb->irqres[i] != NULL)
5158 bus_release_resource(dev, SYS_RES_IRQ,
5159 acb->irq_id[i], acb->irqres[i]);
5160
5161 acb->ih[i] = NULL;
5162 }
5163 pci_release_msi(dev);
5164 } else {
5165 if (acb->ih[0])
5166 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
5167 if (acb->irqres[0] != NULL)
5168 bus_release_resource(dev, SYS_RES_IRQ,
5169 acb->irq_id[0], acb->irqres[0]);
5170 acb->ih[0] = NULL;
5171 }
5172
5173 }
5174 /*
5175 ************************************************************************
5176 ************************************************************************
5177 */
arcmsr_detach(device_t dev)5178 static int arcmsr_detach(device_t dev)
5179 {
5180 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5181 int i;
5182
5183 callout_stop(&acb->devmap_callout);
5184 arcmsr_teardown_intr(dev, acb);
5185 arcmsr_shutdown(dev);
5186 arcmsr_free_resource(acb);
5187 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
5188 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
5189 }
5190 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5191 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
5192 xpt_free_path(acb->ppath);
5193 xpt_bus_deregister(cam_sim_path(acb->psim));
5194 cam_sim_free(acb->psim, TRUE);
5195 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5196 arcmsr_mutex_destroy(acb);
5197 return (0);
5198 }
5199
5200 #ifdef ARCMSR_DEBUG1
arcmsr_dump_data(struct AdapterControlBlock * acb)5201 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
5202 {
5203 if((acb->pktRequestCount - acb->pktReturnCount) == 0)
5204 return;
5205 printf("Command Request Count =0x%x\n",acb->pktRequestCount);
5206 printf("Command Return Count =0x%x\n",acb->pktReturnCount);
5207 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
5208 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount);
5209 }
5210 #endif
5211