1 /*-
2 * Copyright 1996 Massachusetts Institute of Technology
3 *
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
7 * permission notice appear in all copies, that both the above
8 * copyright notice and this permission notice appear in all
9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
12 * no representations about the suitability of this software for any
13 * purpose. It is provided "as is" without express or implied
14 * warranty.
15 *
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/conf.h>
34 #include <sys/fcntl.h>
35 #include <sys/kernel.h>
36
37 #ifndef SMP
38 #include <machine/cputypes.h>
39 #endif
40 #include <machine/clock.h>
41 #include <machine/perfmon.h>
42 #include <machine/specialreg.h>
43
44 static int perfmon_inuse;
45 static int perfmon_cpuok;
46 #ifndef SMP
47 static int msr_ctl[NPMC];
48 #endif
49 static int msr_pmc[NPMC];
50 static unsigned int ctl_shadow[NPMC];
51 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
52 static int (*writectl)(int);
53 #ifndef SMP
54 static int writectl5(int);
55 static int writectl6(int);
56 #endif
57
58 static d_close_t perfmon_close;
59 static d_open_t perfmon_open;
60 static d_ioctl_t perfmon_ioctl;
61
62 /*
63 * XXX perfmon_init_dev(void *) is a split from the perfmon_init() function.
64 * This solves a problem for DEVFS users. It loads the "perfmon" driver after
65 * the DEVFS subsystem has been kicked into action. The SI_ORDER_ANY is to
66 * assure that it is the most lowest priority task which, guarantees the
67 * above.
68 */
69 static void perfmon_init_dev(void *);
70 SYSINIT(cpu, SI_SUB_DRIVERS, SI_ORDER_ANY, perfmon_init_dev, NULL);
71
72 static struct cdevsw perfmon_cdevsw = {
73 .d_version = D_VERSION,
74 .d_flags = D_NEEDGIANT,
75 .d_open = perfmon_open,
76 .d_close = perfmon_close,
77 .d_ioctl = perfmon_ioctl,
78 .d_name = "perfmon",
79 };
80
81 /*
82 * Must be called after cpu_class is set up.
83 */
84 void
perfmon_init(void)85 perfmon_init(void)
86 {
87 #ifndef SMP
88 switch(cpu_class) {
89 case CPUCLASS_586:
90 perfmon_cpuok = 1;
91 msr_ctl[0] = MSR_P5_CESR;
92 msr_ctl[1] = MSR_P5_CESR;
93 msr_pmc[0] = MSR_P5_CTR0;
94 msr_pmc[1] = MSR_P5_CTR1;
95 writectl = writectl5;
96 break;
97 case CPUCLASS_686:
98 perfmon_cpuok = 1;
99 msr_ctl[0] = MSR_EVNTSEL0;
100 msr_ctl[1] = MSR_EVNTSEL1;
101 msr_pmc[0] = MSR_PERFCTR0;
102 msr_pmc[1] = MSR_PERFCTR1;
103 writectl = writectl6;
104 break;
105
106 default:
107 perfmon_cpuok = 0;
108 break;
109 }
110 #endif /* SMP */
111 }
112
113 static void
perfmon_init_dev(void * dummy)114 perfmon_init_dev(void *dummy)
115 {
116 make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
117 }
118
119 int
perfmon_avail(void)120 perfmon_avail(void)
121 {
122 return perfmon_cpuok;
123 }
124
125 int
perfmon_setup(int pmc,unsigned int control)126 perfmon_setup(int pmc, unsigned int control)
127 {
128 register_t saveintr;
129
130 if (pmc < 0 || pmc >= NPMC)
131 return EINVAL;
132
133 perfmon_inuse |= (1 << pmc);
134 control &= ~(PMCF_SYS_FLAGS << 16);
135 saveintr = intr_disable();
136 ctl_shadow[pmc] = control;
137 writectl(pmc);
138 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
139 intr_restore(saveintr);
140 return 0;
141 }
142
143 int
perfmon_get(int pmc,unsigned int * control)144 perfmon_get(int pmc, unsigned int *control)
145 {
146 if (pmc < 0 || pmc >= NPMC)
147 return EINVAL;
148
149 if (perfmon_inuse & (1 << pmc)) {
150 *control = ctl_shadow[pmc];
151 return 0;
152 }
153 return EBUSY; /* XXX reversed sense */
154 }
155
156 int
perfmon_fini(int pmc)157 perfmon_fini(int pmc)
158 {
159 if (pmc < 0 || pmc >= NPMC)
160 return EINVAL;
161
162 if (perfmon_inuse & (1 << pmc)) {
163 perfmon_stop(pmc);
164 ctl_shadow[pmc] = 0;
165 perfmon_inuse &= ~(1 << pmc);
166 return 0;
167 }
168 return EBUSY; /* XXX reversed sense */
169 }
170
171 int
perfmon_start(int pmc)172 perfmon_start(int pmc)
173 {
174 register_t saveintr;
175
176 if (pmc < 0 || pmc >= NPMC)
177 return EINVAL;
178
179 if (perfmon_inuse & (1 << pmc)) {
180 saveintr = intr_disable();
181 ctl_shadow[pmc] |= (PMCF_EN << 16);
182 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
183 writectl(pmc);
184 intr_restore(saveintr);
185 return 0;
186 }
187 return EBUSY;
188 }
189
190 int
perfmon_stop(int pmc)191 perfmon_stop(int pmc)
192 {
193 register_t saveintr;
194
195 if (pmc < 0 || pmc >= NPMC)
196 return EINVAL;
197
198 if (perfmon_inuse & (1 << pmc)) {
199 saveintr = intr_disable();
200 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
201 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
202 writectl(pmc);
203 intr_restore(saveintr);
204 return 0;
205 }
206 return EBUSY;
207 }
208
209 int
perfmon_read(int pmc,quad_t * val)210 perfmon_read(int pmc, quad_t *val)
211 {
212 if (pmc < 0 || pmc >= NPMC)
213 return EINVAL;
214
215 if (perfmon_inuse & (1 << pmc)) {
216 if (ctl_shadow[pmc] & (PMCF_EN << 16))
217 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
218 else
219 *val = pmc_shadow[pmc];
220 return 0;
221 }
222
223 return EBUSY;
224 }
225
226 int
perfmon_reset(int pmc)227 perfmon_reset(int pmc)
228 {
229 if (pmc < 0 || pmc >= NPMC)
230 return EINVAL;
231
232 if (perfmon_inuse & (1 << pmc)) {
233 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
234 return 0;
235 }
236 return EBUSY;
237 }
238
239 #ifndef SMP
240 /*
241 * Unfortunately, the performance-monitoring registers are laid out
242 * differently in the P5 and P6. We keep everything in P6 format
243 * internally (except for the event code), and convert to P5
244 * format as needed on those CPUs. The writectl function pointer
245 * is set up to point to one of these functions by perfmon_init().
246 */
247 int
writectl6(int pmc)248 writectl6(int pmc)
249 {
250 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
251 wrmsr(msr_ctl[pmc], 0);
252 } else {
253 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
254 }
255 return 0;
256 }
257
258 #define P5FLAG_P 0x200
259 #define P5FLAG_E 0x100
260 #define P5FLAG_USR 0x80
261 #define P5FLAG_OS 0x40
262
263 int
writectl5(int pmc)264 writectl5(int pmc)
265 {
266 quad_t newval = 0;
267
268 if (ctl_shadow[1] & (PMCF_EN << 16)) {
269 if (ctl_shadow[1] & (PMCF_USR << 16))
270 newval |= P5FLAG_USR << 16;
271 if (ctl_shadow[1] & (PMCF_OS << 16))
272 newval |= P5FLAG_OS << 16;
273 if (!(ctl_shadow[1] & (PMCF_E << 16)))
274 newval |= P5FLAG_E << 16;
275 newval |= (ctl_shadow[1] & 0x3f) << 16;
276 }
277 if (ctl_shadow[0] & (PMCF_EN << 16)) {
278 if (ctl_shadow[0] & (PMCF_USR << 16))
279 newval |= P5FLAG_USR;
280 if (ctl_shadow[0] & (PMCF_OS << 16))
281 newval |= P5FLAG_OS;
282 if (!(ctl_shadow[0] & (PMCF_E << 16)))
283 newval |= P5FLAG_E;
284 newval |= ctl_shadow[0] & 0x3f;
285 }
286
287 wrmsr(msr_ctl[0], newval);
288 return 0; /* XXX should check for unimplemented bits */
289 }
290 #endif /* !SMP */
291
292 /*
293 * Now the user-mode interface, called from a subdevice of mem.c.
294 */
295 static int writer;
296 static int writerpmc;
297
298 static int
perfmon_open(struct cdev * dev,int flags,int fmt,struct thread * td)299 perfmon_open(struct cdev *dev, int flags, int fmt, struct thread *td)
300 {
301 if (!perfmon_cpuok)
302 return ENXIO;
303
304 if (flags & FWRITE) {
305 if (writer) {
306 return EBUSY;
307 } else {
308 writer = 1;
309 writerpmc = 0;
310 }
311 }
312 return 0;
313 }
314
315 static int
perfmon_close(struct cdev * dev,int flags,int fmt,struct thread * td)316 perfmon_close(struct cdev *dev, int flags, int fmt, struct thread *td)
317 {
318 if (flags & FWRITE) {
319 int i;
320
321 for (i = 0; i < NPMC; i++) {
322 if (writerpmc & (1 << i))
323 perfmon_fini(i);
324 }
325 writer = 0;
326 }
327 return 0;
328 }
329
330 static int
perfmon_ioctl(struct cdev * dev,u_long cmd,caddr_t param,int flags,struct thread * td)331 perfmon_ioctl(struct cdev *dev, u_long cmd, caddr_t param, int flags, struct thread *td)
332 {
333 struct pmc *pmc;
334 struct pmc_data *pmcd;
335 struct pmc_tstamp *pmct;
336 uint64_t freq;
337 int *ip;
338 int rv;
339
340 switch(cmd) {
341 case PMIOSETUP:
342 if (!(flags & FWRITE))
343 return EPERM;
344 pmc = (struct pmc *)param;
345
346 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
347 if (!rv) {
348 writerpmc |= (1 << pmc->pmc_num);
349 }
350 break;
351
352 case PMIOGET:
353 pmc = (struct pmc *)param;
354 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
355 break;
356
357 case PMIOSTART:
358 if (!(flags & FWRITE))
359 return EPERM;
360
361 ip = (int *)param;
362 rv = perfmon_start(*ip);
363 break;
364
365 case PMIOSTOP:
366 if (!(flags & FWRITE))
367 return EPERM;
368
369 ip = (int *)param;
370 rv = perfmon_stop(*ip);
371 break;
372
373 case PMIORESET:
374 if (!(flags & FWRITE))
375 return EPERM;
376
377 ip = (int *)param;
378 rv = perfmon_reset(*ip);
379 break;
380
381 case PMIOREAD:
382 pmcd = (struct pmc_data *)param;
383 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
384 break;
385
386 case PMIOTSTAMP:
387 freq = atomic_load_acq_64(&tsc_freq);
388 if (freq == 0) {
389 rv = ENOTTY;
390 break;
391 }
392 pmct = (struct pmc_tstamp *)param;
393 /* XXX interface loses precision. */
394 pmct->pmct_rate = freq / 1000000;
395 pmct->pmct_value = rdtsc();
396 rv = 0;
397 break;
398 default:
399 rv = ENOTTY;
400 }
401
402 return rv;
403 }
404