1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019 Intel Corporation 3 */ 4 5 #ifndef _OPAE_INTEL_MAX10_H_ 6 #define _OPAE_INTEL_MAX10_H_ 7 8 #include "opae_osdep.h" 9 #include "opae_spi.h" 10 11 struct max10_compatible_id { 12 char compatible[128]; 13 }; 14 15 #define MAX10_PAC "intel,max10" 16 #define MAX10_PAC_N3000 "intel,max10-pac-n3000" 17 #define MAX10_PAC_END "intel,end" 18 19 /* max10 capability flags */ 20 #define MAX10_FLAGS_NO_I2C2 BIT(0) 21 #define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1) 22 #define MAX10_FLAGS_DEVICE_TABLE BIT(2) 23 #define MAX10_FLAGS_SPI BIT(3) 24 #define MAX10_FLGAS_NIOS_SPI BIT(4) 25 #define MAX10_FLAGS_PKVL BIT(5) 26 #define MAX10_FLAGS_SECURE BIT(6) 27 #define MAX10_FLAGS_MAC_CACHE BIT(7) 28 29 /** List of opae sensors */ 30 TAILQ_HEAD(opae_sensor_list, opae_sensor_info); 31 32 struct intel_max10_device { 33 unsigned int flags; /*max10 hardware capability*/ 34 struct altera_spi_device *spi_master; 35 struct spi_transaction_dev *spi_tran_dev; 36 struct max10_compatible_id *id; /*max10 compatible*/ 37 char *fdt_root; 38 unsigned int base; /* max10 base address */ 39 u16 bus; 40 struct opae_sensor_list opae_sensor_list; 41 u32 staging_area_base; 42 u32 staging_area_size; 43 }; 44 45 /* retimer speed */ 46 enum retimer_speed { 47 MXD_1GB = 1, 48 MXD_2_5GB = 2, 49 MXD_5GB = 5, 50 MXD_10GB = 10, 51 MXD_25GB = 25, 52 MXD_40GB = 40, 53 MXD_100GB = 100, 54 MXD_SPEED_UNKNOWN, 55 }; 56 57 /* retimer info */ 58 struct opae_retimer_info { 59 unsigned int nums_retimer; 60 unsigned int ports_per_retimer; 61 unsigned int nums_fvl; 62 unsigned int ports_per_fvl; 63 enum retimer_speed support_speed; 64 }; 65 66 /* retimer status*/ 67 struct opae_retimer_status { 68 enum retimer_speed speed; 69 /* 70 * retimer line link status bitmap: 71 * bit 0: Retimer0 Port0 link status 72 * bit 1: Retimer0 Port1 link status 73 * bit 2: Retimer0 Port2 link status 74 * bit 3: Retimer0 Port3 link status 75 * 76 * bit 4: Retimer1 Port0 link status 77 * bit 5: Retimer1 Port1 link status 78 * bit 6: Retimer1 Port2 link status 79 * bit 7: Retimer1 Port3 link status 80 */ 81 unsigned int line_link_bitmap; 82 }; 83 84 #define FLASH_BASE 0x10000000 85 #define FLASH_OPTION_BITS 0x10000 86 87 /* System Registers */ 88 #define MAX10_BASE_ADDR 0x300400 89 #define MAX10_SEC_BASE_ADDR 0x300800 90 /* Register offset of system registers */ 91 #define NIOS2_FW_VERSION 0x0 92 #define MAX10_MACADDR1 0x10 93 #define MAX10_MAC_BYTE4 GENMASK(7, 0) 94 #define MAX10_MAC_BYTE3 GENMASK(15, 8) 95 #define MAX10_MAC_BYTE2 GENMASK(23, 16) 96 #define MAX10_MAC_BYTE1 GENMASK(31, 24) 97 #define MAX10_MACADDR2 0x14 98 #define MAX10_MAC_BYTE6 GENMASK(7, 0) 99 #define MAX10_MAC_BYTE5 GENMASK(15, 8) 100 #define MAX10_MAC_COUNT GENMASK(23, 16) 101 #define RSU_REG 0x2c 102 #define FPGA_RECONF_PAGE GENMASK(2, 0) 103 #define FPGA_PAGE(p) ((p) & 0x1) 104 #define FPGA_RP_LOAD BIT(3) 105 #define NIOS2_PRERESET BIT(4) 106 #define NIOS2_HANG BIT(5) 107 #define RSU_ENABLE BIT(6) 108 #define NIOS2_RESET BIT(7) 109 #define NIOS2_I2C2_POLL_STOP BIT(13) 110 #define PKVL_EEPROM_LOAD BIT(31) 111 #define FPGA_RECONF_REG 0x30 112 #define SFPGA_RECONF_PAGE GENMASK(22, 20) 113 #define SFPGA_PAGE(p) (((p) & 0x1) << 20) 114 #define SFPGA_RP_LOAD BIT(23) 115 #define MAX10_TEST_REG 0x3c 116 #define COUNTDOWN_START BIT(18) 117 #define MAX10_BUILD_VER 0x68 118 #define MAX10_VERSION_MAJOR GENMASK(23, 16) 119 #define PCB_INFO GENMASK(31, 24) 120 #define FPGA_PAGE_INFO 0x6c 121 #define DT_AVAIL_REG 0x90 122 #define DT_AVAIL BIT(0) 123 #define DT_BASE_ADDR_REG 0x94 124 #define MAX10_DOORBELL 0x400 125 #define RSU_REQUEST BIT(0) 126 #define SEC_PROGRESS GENMASK(7, 4) 127 #define SEC_PROGRESS_G(v) (((v) >> 4) & 0xf) 128 #define SEC_PROGRESS_IDLE 0x0 129 #define SEC_PROGRESS_PREPARE 0x1 130 #define SEC_PROGRESS_SLEEP 0x2 131 #define SEC_PROGRESS_READY 0x3 132 #define SEC_PROGRESS_AUTHENTICATING 0x4 133 #define SEC_PROGRESS_COPYING 0x5 134 #define SEC_PROGRESS_UPDATE_CANCEL 0x6 135 #define SEC_PROGRESS_PROGRAM_KEY_HASH 0x7 136 #define SEC_PROGRESS_RSU_DONE 0x8 137 #define SEC_PROGRESS_PKVL_PROM_DONE 0x9 138 #define HOST_STATUS GENMASK(11, 8) 139 #define HOST_STATUS_S(v) (((v) << 8) & 0xf00) 140 #define HOST_STATUS_IDLE 0x0 141 #define HOST_STATUS_WRITE_DONE 0x1 142 #define HOST_STATUS_ABORT_RSU 0x2 143 #define SEC_STATUS GENMASK(23, 16) 144 #define SEC_STATUS_G(v) (((v) >> 16) & 0xff) 145 #define SEC_STATUS_NORMAL 0x0 146 #define SEC_STATUS_TIMEOUT 0x1 147 #define SEC_STATUS_AUTH_FAIL 0x2 148 #define SEC_STATUS_COPY_FAIL 0x3 149 #define SEC_STATUS_FATAL 0x4 150 #define SEC_STATUS_PKVL_REJECT 0x5 151 #define SEC_STATUS_NON_INC 0x6 152 #define SEC_STATUS_ERASE_FAIL 0x7 153 #define SEC_STATUS_WEAROUT 0x8 154 #define SEC_STATUS_NIOS_OK 0x80 155 #define SEC_STATUS_USER_OK 0x81 156 #define SEC_STATUS_FACTORY_OK 0x82 157 #define SEC_STATUS_USER_FAIL 0x83 158 #define SEC_STATUS_FACTORY_FAIL 0x84 159 #define SEC_STATUS_NIOS_FLASH_ERR 0x85 160 #define SEC_STATUS_FPGA_FLASH_ERR 0x86 161 #define CONFIG_SEL BIT(28) 162 #define CONFIG_SEL_S(v) (((v) & 0x1) << 28) 163 #define REBOOT_REQ BIT(29) 164 #define MAX10_AUTH_RESULT 0x404 165 166 /* PKVL related registers, in system register region */ 167 #define PKVL_POLLING_CTRL 0x80 168 #define POLLING_MODE GENMASK(15, 0) 169 #define PKVL_A_PRELOAD BIT(16) 170 #define PKVL_A_PRELOAD_TIMEOUT BIT(17) 171 #define PKVL_A_DATA_TOO_BIG BIT(18) 172 #define PKVL_A_HDR_CHECKSUM BIT(20) 173 #define PKVL_B_PRELOAD BIT(24) 174 #define PKVL_B_PRELOAD_TIMEOUT BIT(25) 175 #define PKVL_B_DATA_TOO_BIG BIT(26) 176 #define PKVL_B_HDR_CHECKSUM BIT(28) 177 #define PKVL_EEPROM_UPG_STATUS GENMASK(31, 16) 178 #define PKVL_LINK_STATUS 0x164 179 #define PKVL_A_VERSION 0x254 180 #define PKVL_B_VERSION 0x258 181 #define SERDES_VERSION GENMASK(15, 0) 182 #define SBUS_VERSION GENMASK(31, 16) 183 184 #define DFT_MAX_SIZE 0x7e0000 185 #define MAX_STAGING_AREA_BASE 0xffffffff 186 #define MAX_STAGING_AREA_SIZE 0x3800000 187 188 int max10_reg_read(struct intel_max10_device *dev, 189 unsigned int reg, unsigned int *val); 190 int max10_reg_write(struct intel_max10_device *dev, 191 unsigned int reg, unsigned int val); 192 int max10_sys_read(struct intel_max10_device *dev, 193 unsigned int offset, unsigned int *val); 194 int max10_sys_write(struct intel_max10_device *dev, 195 unsigned int offset, unsigned int val); 196 int max10_sys_update_bits(struct intel_max10_device *dev, 197 unsigned int offset, unsigned int msk, unsigned int val); 198 struct intel_max10_device * 199 intel_max10_device_probe(struct altera_spi_device *spi, 200 int chipselect); 201 int intel_max10_device_remove(struct intel_max10_device *dev); 202 203 204 #define SENSOR_REG_VALUE 0x0 205 #define SENSOR_REG_HIGH_WARN 0x1 206 #define SENSOR_REG_HIGH_FATAL 0x2 207 #define SENSOR_REG_LOW_WARN 0x3 208 #define SENSOR_REG_LOW_FATAL 0x4 209 #define SENSOR_REG_HYSTERESIS 0x5 210 #define SENSOR_REG_MAX 0x6 211 212 static const char * const sensor_reg_name[] = { 213 "value", 214 "high_warn", 215 "high_fatal", 216 "low_warn", 217 "low_fatal", 218 "hysteresis", 219 }; 220 221 struct sensor_reg { 222 unsigned int regoff; 223 size_t size; 224 }; 225 226 struct raw_sensor_info { 227 const char *name; 228 const char *type; 229 unsigned int id; 230 unsigned int multiplier; 231 struct sensor_reg regs[SENSOR_REG_MAX]; 232 }; 233 234 #define OPAE_SENSOR_VALID 0x1 235 #define OPAE_SENSOR_HIGH_WARN_VALID 0x2 236 #define OPAE_SENSOR_HIGH_FATAL_VALID 0x4 237 #define OPAE_SENSOR_LOW_WARN_VALID 0x8 238 #define OPAE_SENSOR_LOW_FATAL_VALID 0x10 239 #define OPAE_SENSOR_HYSTERESIS_VALID 0x20 240 241 struct opae_sensor_info { 242 TAILQ_ENTRY(opae_sensor_info) node; 243 const char *name; 244 const char *type; 245 unsigned int id; 246 unsigned int high_fatal; 247 unsigned int high_warn; 248 unsigned int low_fatal; 249 unsigned int low_warn; 250 unsigned int hysteresis; 251 unsigned int multiplier; 252 unsigned int flags; 253 unsigned int value; 254 unsigned int value_reg; 255 }; 256 257 #endif 258