1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Oleksandr Tymoshenko <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/rman.h>
37 #include <sys/resource.h>
38 #include <machine/bus.h>
39
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42
43 #include <dev/spibus/spi.h>
44 #include <dev/spibus/spibusvar.h>
45
46 #include <dev/extres/clk/clk.h>
47 #include <dev/extres/hwreset/hwreset.h>
48
49 #include "spibus_if.h"
50
51 #define RK_SPI_CTRLR0 0x0000
52 #define CTRLR0_OPM_MASTER (0 << 20)
53 #define CTRLR0_XFM_TR (0 << 18)
54 #define CTRLR0_FRF_MOTO (0 << 16)
55 #define CTRLR0_BHT_8BIT (1 << 13)
56 #define CTRLR0_EM_BIG (1 << 11)
57 #define CTRLR0_SSD_ONE (1 << 10)
58 #define CTRLR0_SCPOL (1 << 7)
59 #define CTRLR0_SCPH (1 << 6)
60 #define CTRLR0_DFS_8BIT (1 << 0)
61 #define RK_SPI_CTRLR1 0x0004
62 #define RK_SPI_ENR 0x0008
63 #define RK_SPI_SER 0x000c
64 #define RK_SPI_BAUDR 0x0010
65 #define RK_SPI_TXFTLR 0x0014
66 #define RK_SPI_RXFTLR 0x0018
67 #define RK_SPI_TXFLR 0x001c
68 #define RK_SPI_RXFLR 0x0020
69 #define RK_SPI_SR 0x0024
70 #define SR_BUSY (1 << 0)
71 #define RK_SPI_IPR 0x0028
72 #define RK_SPI_IMR 0x002c
73 #define IMR_RFFIM (1 << 4)
74 #define IMR_TFEIM (1 << 0)
75 #define RK_SPI_ISR 0x0030
76 #define ISR_RFFIS (1 << 4)
77 #define ISR_TFEIS (1 << 0)
78 #define RK_SPI_RISR 0x0034
79 #define RK_SPI_ICR 0x0038
80 #define RK_SPI_DMACR 0x003c
81 #define RK_SPI_DMATDLR 0x0040
82 #define RK_SPI_DMARDLR 0x0044
83 #define RK_SPI_TXDR 0x0400
84 #define RK_SPI_RXDR 0x0800
85
86 #define CS_MAX 1
87
88 static struct ofw_compat_data compat_data[] = {
89 { "rockchip,rk3328-spi", 1 },
90 { "rockchip,rk3399-spi", 1 },
91 { "rockchip,rk3568-spi", 1 },
92 { NULL, 0 }
93 };
94
95 static struct resource_spec rk_spi_spec[] = {
96 { SYS_RES_MEMORY, 0, RF_ACTIVE },
97 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
98 { -1, 0 }
99 };
100
101 struct rk_spi_softc {
102 device_t dev;
103 device_t spibus;
104 struct resource *res[2];
105 struct mtx mtx;
106 clk_t clk_apb;
107 clk_t clk_spi;
108 void * intrhand;
109 int transfer;
110 uint32_t fifo_size;
111 uint64_t max_freq;
112
113 uint32_t intreg;
114 uint8_t *rxbuf;
115 uint32_t rxidx;
116 uint8_t *txbuf;
117 uint32_t txidx;
118 uint32_t txlen;
119 uint32_t rxlen;
120 };
121
122 #define RK_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
123 #define RK_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
124 #define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
125 #define RK_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
126
127 static int rk_spi_probe(device_t dev);
128 static int rk_spi_attach(device_t dev);
129 static int rk_spi_detach(device_t dev);
130 static void rk_spi_intr(void *arg);
131
132 static void
rk_spi_enable_chip(struct rk_spi_softc * sc,int enable)133 rk_spi_enable_chip(struct rk_spi_softc *sc, int enable)
134 {
135
136 RK_SPI_WRITE_4(sc, RK_SPI_ENR, enable ? 1 : 0);
137 }
138
139 static int
rk_spi_set_cs(struct rk_spi_softc * sc,uint32_t cs,bool active)140 rk_spi_set_cs(struct rk_spi_softc *sc, uint32_t cs, bool active)
141 {
142 uint32_t reg;
143
144 if (cs & SPIBUS_CS_HIGH) {
145 device_printf(sc->dev, "SPIBUS_CS_HIGH is not supported\n");
146 return (EINVAL);
147 }
148
149 if (cs > CS_MAX)
150 return (EINVAL);
151
152 reg = RK_SPI_READ_4(sc, RK_SPI_SER);
153 if (active)
154 reg |= (1 << cs);
155 else
156 reg &= ~(1 << cs);
157 RK_SPI_WRITE_4(sc, RK_SPI_SER, reg);
158
159 return (0);
160 }
161
162 static void
rk_spi_hw_setup(struct rk_spi_softc * sc,uint32_t mode,uint32_t freq)163 rk_spi_hw_setup(struct rk_spi_softc *sc, uint32_t mode, uint32_t freq)
164 {
165 uint32_t cr0;
166 uint32_t div;
167
168 cr0 = CTRLR0_OPM_MASTER | CTRLR0_XFM_TR | CTRLR0_FRF_MOTO |
169 CTRLR0_BHT_8BIT | CTRLR0_EM_BIG | CTRLR0_SSD_ONE |
170 CTRLR0_DFS_8BIT;
171
172 if (mode & SPIBUS_MODE_CPHA)
173 cr0 |= CTRLR0_SCPH;
174 if (mode & SPIBUS_MODE_CPOL)
175 cr0 |= CTRLR0_SCPOL;
176
177 /* minimum divider is 2 */
178 if (sc->max_freq < freq*2) {
179 clk_set_freq(sc->clk_spi, 2 * freq, CLK_SET_ROUND_DOWN);
180 clk_get_freq(sc->clk_spi, &sc->max_freq);
181 }
182
183 div = ((sc->max_freq + freq - 1) / freq);
184 div = (div + 1) & 0xfffe;
185 RK_SPI_WRITE_4(sc, RK_SPI_BAUDR, div);
186
187 RK_SPI_WRITE_4(sc, RK_SPI_CTRLR0, cr0);
188 }
189
190 static uint32_t
rk_spi_fifo_size(struct rk_spi_softc * sc)191 rk_spi_fifo_size(struct rk_spi_softc *sc)
192 {
193 uint32_t txftlr, reg;
194
195 for (txftlr = 2; txftlr < 32; txftlr++) {
196 RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, txftlr);
197 reg = RK_SPI_READ_4(sc, RK_SPI_TXFTLR);
198 if (reg != txftlr)
199 break;
200 }
201 RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, 0);
202
203 if (txftlr == 31)
204 return 0;
205
206 return txftlr;
207 }
208
209 static void
rk_spi_empty_rxfifo(struct rk_spi_softc * sc)210 rk_spi_empty_rxfifo(struct rk_spi_softc *sc)
211 {
212 uint32_t rxlevel;
213 rxlevel = RK_SPI_READ_4(sc, RK_SPI_RXFLR);
214 while (sc->rxidx < sc->rxlen &&
215 (rxlevel-- > 0)) {
216 sc->rxbuf[sc->rxidx++] = (uint8_t)RK_SPI_READ_4(sc, RK_SPI_RXDR);
217 }
218 }
219
220 static void
rk_spi_fill_txfifo(struct rk_spi_softc * sc)221 rk_spi_fill_txfifo(struct rk_spi_softc *sc)
222 {
223 uint32_t txlevel;
224 txlevel = RK_SPI_READ_4(sc, RK_SPI_TXFLR);
225
226 while (sc->txidx < sc->txlen && txlevel < sc->fifo_size) {
227 RK_SPI_WRITE_4(sc, RK_SPI_TXDR, sc->txbuf[sc->txidx++]);
228 txlevel++;
229 }
230
231 if (sc->txidx != sc->txlen)
232 sc->intreg |= (IMR_TFEIM | IMR_RFFIM);
233 }
234
235 static int
rk_spi_xfer_buf(struct rk_spi_softc * sc,void * rxbuf,void * txbuf,uint32_t len)236 rk_spi_xfer_buf(struct rk_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len)
237 {
238 int err;
239
240 if (len == 0)
241 return (0);
242
243 sc->rxbuf = rxbuf;
244 sc->rxlen = len;
245 sc->rxidx = 0;
246 sc->txbuf = txbuf;
247 sc->txlen = len;
248 sc->txidx = 0;
249 sc->intreg = 0;
250 rk_spi_fill_txfifo(sc);
251
252 RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
253
254 err = 0;
255 while (err == 0 && sc->intreg != 0)
256 err = msleep(sc, &sc->mtx, 0, "rk_spi", 10 * hz);
257
258 while (err == 0 && sc->rxidx != sc->txidx) {
259 /* read residual data from RX fifo */
260 rk_spi_empty_rxfifo(sc);
261 }
262
263 if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen)
264 err = EIO;
265
266 return (err);
267 }
268
269 static int
rk_spi_probe(device_t dev)270 rk_spi_probe(device_t dev)
271 {
272 if (!ofw_bus_status_okay(dev))
273 return (ENXIO);
274
275 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
276 return (ENXIO);
277
278 device_set_desc(dev, "Rockchip SPI");
279 return (BUS_PROBE_DEFAULT);
280 }
281
282 static int
rk_spi_attach(device_t dev)283 rk_spi_attach(device_t dev)
284 {
285 struct rk_spi_softc *sc;
286 int error;
287
288 sc = device_get_softc(dev);
289 sc->dev = dev;
290
291 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
292
293 if (bus_alloc_resources(dev, rk_spi_spec, sc->res) != 0) {
294 device_printf(dev, "cannot allocate resources for device\n");
295 error = ENXIO;
296 goto fail;
297 }
298
299 if (bus_setup_intr(dev, sc->res[1],
300 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_spi_intr, sc,
301 &sc->intrhand)) {
302 bus_release_resources(dev, rk_spi_spec, sc->res);
303 device_printf(dev, "cannot setup interrupt handler\n");
304 return (ENXIO);
305 }
306
307 /* Activate the module clock. */
308 error = clk_get_by_ofw_name(dev, 0, "apb_pclk", &sc->clk_apb);
309 if (error != 0) {
310 device_printf(dev, "cannot get apb_pclk clock\n");
311 goto fail;
312 }
313 error = clk_get_by_ofw_name(dev, 0, "spiclk", &sc->clk_spi);
314 if (error != 0) {
315 device_printf(dev, "cannot get spiclk clock\n");
316 goto fail;
317 }
318 error = clk_enable(sc->clk_apb);
319 if (error != 0) {
320 device_printf(dev, "cannot enable ahb clock\n");
321 goto fail;
322 }
323 error = clk_enable(sc->clk_spi);
324 if (error != 0) {
325 device_printf(dev, "cannot enable spiclk clock\n");
326 goto fail;
327 }
328 clk_get_freq(sc->clk_spi, &sc->max_freq);
329
330 sc->fifo_size = rk_spi_fifo_size(sc);
331 if (sc->fifo_size == 0) {
332 device_printf(dev, "failed to get fifo size\n");
333 goto fail;
334 }
335
336 sc->spibus = device_add_child(dev, "spibus", -1);
337
338 RK_SPI_WRITE_4(sc, RK_SPI_IMR, 0);
339 RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, sc->fifo_size/2 - 1);
340 RK_SPI_WRITE_4(sc, RK_SPI_RXFTLR, sc->fifo_size/2 - 1);
341
342 return (bus_generic_attach(dev));
343
344 fail:
345 rk_spi_detach(dev);
346 return (error);
347 }
348
349 static int
rk_spi_detach(device_t dev)350 rk_spi_detach(device_t dev)
351 {
352 struct rk_spi_softc *sc;
353
354 sc = device_get_softc(dev);
355
356 bus_generic_detach(sc->dev);
357 if (sc->spibus != NULL)
358 device_delete_child(dev, sc->spibus);
359
360 if (sc->clk_spi != NULL)
361 clk_release(sc->clk_spi);
362 if (sc->clk_apb)
363 clk_release(sc->clk_apb);
364
365 if (sc->intrhand != NULL)
366 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
367
368 bus_release_resources(dev, rk_spi_spec, sc->res);
369 mtx_destroy(&sc->mtx);
370
371 return (0);
372 }
373
374 static void
rk_spi_intr(void * arg)375 rk_spi_intr(void *arg)
376 {
377 struct rk_spi_softc *sc;
378 uint32_t intreg, isr;
379
380 sc = arg;
381
382 RK_SPI_LOCK(sc);
383 intreg = RK_SPI_READ_4(sc, RK_SPI_IMR);
384 isr = RK_SPI_READ_4(sc, RK_SPI_ISR);
385 RK_SPI_WRITE_4(sc, RK_SPI_ICR, isr);
386
387 if (isr & ISR_RFFIS)
388 rk_spi_empty_rxfifo(sc);
389
390 if (isr & ISR_TFEIS)
391 rk_spi_fill_txfifo(sc);
392
393 /* no bytes left, disable interrupt */
394 if (sc->txidx == sc->txlen) {
395 sc->intreg = 0;
396 wakeup(sc);
397 }
398
399 if (sc->intreg != intreg) {
400 (void)RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
401 (void)RK_SPI_READ_4(sc, RK_SPI_IMR);
402 }
403
404 RK_SPI_UNLOCK(sc);
405 }
406
407 static phandle_t
rk_spi_get_node(device_t bus,device_t dev)408 rk_spi_get_node(device_t bus, device_t dev)
409 {
410
411 return ofw_bus_get_node(bus);
412 }
413
414 static int
rk_spi_transfer(device_t dev,device_t child,struct spi_command * cmd)415 rk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
416 {
417 struct rk_spi_softc *sc;
418 uint32_t cs, mode, clock;
419 int err = 0;
420
421 sc = device_get_softc(dev);
422
423 spibus_get_cs(child, &cs);
424 spibus_get_clock(child, &clock);
425 spibus_get_mode(child, &mode);
426
427 RK_SPI_LOCK(sc);
428 rk_spi_hw_setup(sc, mode, clock);
429 rk_spi_enable_chip(sc, 1);
430 err = rk_spi_set_cs(sc, cs, true);
431 if (err != 0) {
432 rk_spi_enable_chip(sc, 0);
433 RK_SPI_UNLOCK(sc);
434 return (err);
435 }
436
437 /* Transfer command then data bytes. */
438 err = 0;
439 if (cmd->tx_cmd_sz > 0)
440 err = rk_spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
441 cmd->tx_cmd_sz);
442 if (cmd->tx_data_sz > 0 && err == 0)
443 err = rk_spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
444 cmd->tx_data_sz);
445
446 rk_spi_set_cs(sc, cs, false);
447 rk_spi_enable_chip(sc, 0);
448 RK_SPI_UNLOCK(sc);
449
450 return (err);
451 }
452
453 static device_method_t rk_spi_methods[] = {
454 /* Device interface */
455 DEVMETHOD(device_probe, rk_spi_probe),
456 DEVMETHOD(device_attach, rk_spi_attach),
457 DEVMETHOD(device_detach, rk_spi_detach),
458
459 /* spibus_if */
460 DEVMETHOD(spibus_transfer, rk_spi_transfer),
461
462 /* ofw_bus_if */
463 DEVMETHOD(ofw_bus_get_node, rk_spi_get_node),
464
465 DEVMETHOD_END
466 };
467
468 static driver_t rk_spi_driver = {
469 "spi",
470 rk_spi_methods,
471 sizeof(struct rk_spi_softc),
472 };
473
474 DRIVER_MODULE(rk_spi, simplebus, rk_spi_driver, 0, 0);
475 DRIVER_MODULE(ofw_spibus, rk_spi, ofw_spibus_driver, 0, 0);
476 MODULE_DEPEND(rk_spi, ofw_spibus, 1, 1, 1);
477 OFWBUS_PNP_INFO(compat_data);
478