1 /*-
2 * Copyright (c) 2016 Jared McNeill <[email protected]>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Allwinner thermal sensor controller
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/eventhandler.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <sys/reboot.h>
39 #include <sys/module.h>
40 #include <sys/cpu.h>
41 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <dev/extres/clk/clk.h>
48 #include <dev/extres/hwreset/hwreset.h>
49 #include <dev/extres/nvmem/nvmem.h>
50
51 #include <arm/allwinner/aw_sid.h>
52
53 #include "cpufreq_if.h"
54 #include "nvmem_if.h"
55
56 #define THS_CTRL0 0x00
57 #define THS_CTRL1 0x04
58 #define ADC_CALI_EN (1 << 17)
59 #define THS_CTRL2 0x40
60 #define SENSOR_ACQ1_SHIFT 16
61 #define SENSOR2_EN (1 << 2)
62 #define SENSOR1_EN (1 << 1)
63 #define SENSOR0_EN (1 << 0)
64 #define THS_INTC 0x44
65 #define THS_THERMAL_PER_SHIFT 12
66 #define THS_INTS 0x48
67 #define THS2_DATA_IRQ_STS (1 << 10)
68 #define THS1_DATA_IRQ_STS (1 << 9)
69 #define THS0_DATA_IRQ_STS (1 << 8)
70 #define SHUT_INT2_STS (1 << 6)
71 #define SHUT_INT1_STS (1 << 5)
72 #define SHUT_INT0_STS (1 << 4)
73 #define ALARM_INT2_STS (1 << 2)
74 #define ALARM_INT1_STS (1 << 1)
75 #define ALARM_INT0_STS (1 << 0)
76 #define THS_ALARM0_CTRL 0x50
77 #define ALARM_T_HOT_MASK 0xfff
78 #define ALARM_T_HOT_SHIFT 16
79 #define ALARM_T_HYST_MASK 0xfff
80 #define ALARM_T_HYST_SHIFT 0
81 #define THS_SHUTDOWN0_CTRL 0x60
82 #define SHUT_T_HOT_MASK 0xfff
83 #define SHUT_T_HOT_SHIFT 16
84 #define THS_FILTER 0x70
85 #define THS_CALIB0 0x74
86 #define THS_CALIB1 0x78
87 #define THS_DATA0 0x80
88 #define THS_DATA1 0x84
89 #define THS_DATA2 0x88
90 #define DATA_MASK 0xfff
91
92 #define A83T_CLK_RATE 24000000
93 #define A83T_ADC_ACQUIRE_TIME 23 /* 24Mhz/(23 + 1) = 1us */
94 #define A83T_THERMAL_PER 1 /* 4096 * (1 + 1) / 24Mhz = 341 us */
95 #define A83T_FILTER 0x5 /* Filter enabled, avg of 4 */
96 #define A83T_TEMP_BASE 2719000
97 #define A83T_TEMP_MUL 1000
98 #define A83T_TEMP_DIV 14186
99
100 #define A64_CLK_RATE 4000000
101 #define A64_ADC_ACQUIRE_TIME 400 /* 4Mhz/(400 + 1) = 100 us */
102 #define A64_THERMAL_PER 24 /* 4096 * (24 + 1) / 4Mhz = 25.6 ms */
103 #define A64_FILTER 0x6 /* Filter enabled, avg of 8 */
104 #define A64_TEMP_BASE 2170000
105 #define A64_TEMP_MUL 1000
106 #define A64_TEMP_DIV 8560
107
108 #define H3_CLK_RATE 4000000
109 #define H3_ADC_ACQUIRE_TIME 0x3f
110 #define H3_THERMAL_PER 401
111 #define H3_FILTER 0x6 /* Filter enabled, avg of 8 */
112 #define H3_TEMP_BASE 217
113 #define H3_TEMP_MUL 1000
114 #define H3_TEMP_DIV 8253
115 #define H3_TEMP_MINUS 1794000
116 #define H3_INIT_ALARM 90 /* degC */
117 #define H3_INIT_SHUT 105 /* degC */
118
119 #define H5_CLK_RATE 24000000
120 #define H5_ADC_ACQUIRE_TIME 479 /* 24Mhz/479 = 20us */
121 #define H5_THERMAL_PER 58 /* 4096 * (58 + 1) / 24Mhz = 10ms */
122 #define H5_FILTER 0x6 /* Filter enabled, avg of 8 */
123 #define H5_TEMP_BASE 233832448
124 #define H5_TEMP_MUL 124885
125 #define H5_TEMP_DIV 20
126 #define H5_TEMP_BASE_CPU 271581184
127 #define H5_TEMP_MUL_CPU 152253
128 #define H5_TEMP_BASE_GPU 289406976
129 #define H5_TEMP_MUL_GPU 166724
130 #define H5_INIT_CPU_ALARM 80 /* degC */
131 #define H5_INIT_CPU_SHUT 96 /* degC */
132 #define H5_INIT_GPU_ALARM 84 /* degC */
133 #define H5_INIT_GPU_SHUT 100 /* degC */
134
135 #define TEMP_C_TO_K 273
136 #define SENSOR_ENABLE_ALL (SENSOR0_EN|SENSOR1_EN|SENSOR2_EN)
137 #define SHUT_INT_ALL (SHUT_INT0_STS|SHUT_INT1_STS|SHUT_INT2_STS)
138 #define ALARM_INT_ALL (ALARM_INT0_STS)
139
140 #define MAX_SENSORS 3
141 #define MAX_CF_LEVELS 64
142
143 #define THROTTLE_ENABLE_DEFAULT 1
144
145 /* Enable thermal throttling */
146 static int aw_thermal_throttle_enable = THROTTLE_ENABLE_DEFAULT;
147 TUNABLE_INT("hw.aw_thermal.throttle_enable", &aw_thermal_throttle_enable);
148
149 struct aw_thermal_sensor {
150 const char *name;
151 const char *desc;
152 int init_alarm;
153 int init_shut;
154 };
155
156 struct aw_thermal_config {
157 struct aw_thermal_sensor sensors[MAX_SENSORS];
158 int nsensors;
159 uint64_t clk_rate;
160 uint32_t adc_acquire_time;
161 int adc_cali_en;
162 uint32_t filter;
163 uint32_t thermal_per;
164 int (*to_temp)(uint32_t, int);
165 uint32_t (*to_reg)(int, int);
166 int temp_base;
167 int temp_mul;
168 int temp_div;
169 int calib0, calib1;
170 uint32_t calib0_mask, calib1_mask;
171 };
172
173 static int
a83t_to_temp(uint32_t val,int sensor)174 a83t_to_temp(uint32_t val, int sensor)
175 {
176 return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV);
177 }
178
179 static const struct aw_thermal_config a83t_config = {
180 .nsensors = 3,
181 .sensors = {
182 [0] = {
183 .name = "cluster0",
184 .desc = "CPU cluster 0 temperature",
185 },
186 [1] = {
187 .name = "cluster1",
188 .desc = "CPU cluster 1 temperature",
189 },
190 [2] = {
191 .name = "gpu",
192 .desc = "GPU temperature",
193 },
194 },
195 .clk_rate = A83T_CLK_RATE,
196 .adc_acquire_time = A83T_ADC_ACQUIRE_TIME,
197 .adc_cali_en = 1,
198 .filter = A83T_FILTER,
199 .thermal_per = A83T_THERMAL_PER,
200 .to_temp = a83t_to_temp,
201 .calib0_mask = 0xffffffff,
202 .calib1_mask = 0xffff,
203 };
204
205 static int
a64_to_temp(uint32_t val,int sensor)206 a64_to_temp(uint32_t val, int sensor)
207 {
208 return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV);
209 }
210
211 static const struct aw_thermal_config a64_config = {
212 .nsensors = 3,
213 .sensors = {
214 [0] = {
215 .name = "cpu",
216 .desc = "CPU temperature",
217 },
218 [1] = {
219 .name = "gpu1",
220 .desc = "GPU temperature 1",
221 },
222 [2] = {
223 .name = "gpu2",
224 .desc = "GPU temperature 2",
225 },
226 },
227 .clk_rate = A64_CLK_RATE,
228 .adc_acquire_time = A64_ADC_ACQUIRE_TIME,
229 .adc_cali_en = 1,
230 .filter = A64_FILTER,
231 .thermal_per = A64_THERMAL_PER,
232 .to_temp = a64_to_temp,
233 .calib0_mask = 0xffffffff,
234 .calib1_mask = 0xffff,
235 };
236
237 static int
h3_to_temp(uint32_t val,int sensor)238 h3_to_temp(uint32_t val, int sensor)
239 {
240 return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV));
241 }
242
243 static uint32_t
h3_to_reg(int val,int sensor)244 h3_to_reg(int val, int sensor)
245 {
246 return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL);
247 }
248
249 static const struct aw_thermal_config h3_config = {
250 .nsensors = 1,
251 .sensors = {
252 [0] = {
253 .name = "cpu",
254 .desc = "CPU temperature",
255 .init_alarm = H3_INIT_ALARM,
256 .init_shut = H3_INIT_SHUT,
257 },
258 },
259 .clk_rate = H3_CLK_RATE,
260 .adc_acquire_time = H3_ADC_ACQUIRE_TIME,
261 .adc_cali_en = 1,
262 .filter = H3_FILTER,
263 .thermal_per = H3_THERMAL_PER,
264 .to_temp = h3_to_temp,
265 .to_reg = h3_to_reg,
266 .calib0_mask = 0xffffffff,
267 };
268
269 static int
h5_to_temp(uint32_t val,int sensor)270 h5_to_temp(uint32_t val, int sensor)
271 {
272 int tmp;
273
274 /* Temp is lower than 70 degrees */
275 if (val > 0x500) {
276 tmp = H5_TEMP_BASE - (val * H5_TEMP_MUL);
277 tmp >>= H5_TEMP_DIV;
278 return (tmp);
279 }
280
281 if (sensor == 0)
282 tmp = H5_TEMP_BASE_CPU - (val * H5_TEMP_MUL_CPU);
283 else if (sensor == 1)
284 tmp = H5_TEMP_BASE_GPU - (val * H5_TEMP_MUL_GPU);
285 else {
286 printf("Unknown sensor %d\n", sensor);
287 return (val);
288 }
289
290 tmp >>= H5_TEMP_DIV;
291 return (tmp);
292 }
293
294 static uint32_t
h5_to_reg(int val,int sensor)295 h5_to_reg(int val, int sensor)
296 {
297 int tmp;
298
299 if (val < 70) {
300 tmp = H5_TEMP_BASE - (val << H5_TEMP_DIV);
301 tmp /= H5_TEMP_MUL;
302 } else {
303 if (sensor == 0) {
304 tmp = H5_TEMP_BASE_CPU - (val << H5_TEMP_DIV);
305 tmp /= H5_TEMP_MUL_CPU;
306 } else if (sensor == 1) {
307 tmp = H5_TEMP_BASE_GPU - (val << H5_TEMP_DIV);
308 tmp /= H5_TEMP_MUL_GPU;
309 } else {
310 printf("Unknown sensor %d\n", sensor);
311 return (val);
312 }
313 }
314
315 return ((uint32_t)tmp);
316 }
317
318 static const struct aw_thermal_config h5_config = {
319 .nsensors = 2,
320 .sensors = {
321 [0] = {
322 .name = "cpu",
323 .desc = "CPU temperature",
324 .init_alarm = H5_INIT_CPU_ALARM,
325 .init_shut = H5_INIT_CPU_SHUT,
326 },
327 [1] = {
328 .name = "gpu",
329 .desc = "GPU temperature",
330 .init_alarm = H5_INIT_GPU_ALARM,
331 .init_shut = H5_INIT_GPU_SHUT,
332 },
333 },
334 .clk_rate = H5_CLK_RATE,
335 .adc_acquire_time = H5_ADC_ACQUIRE_TIME,
336 .filter = H5_FILTER,
337 .thermal_per = H5_THERMAL_PER,
338 .to_temp = h5_to_temp,
339 .to_reg = h5_to_reg,
340 .calib0_mask = 0xffffffff,
341 };
342
343 static struct ofw_compat_data compat_data[] = {
344 { "allwinner,sun8i-a83t-ths", (uintptr_t)&a83t_config },
345 { "allwinner,sun8i-h3-ths", (uintptr_t)&h3_config },
346 { "allwinner,sun50i-a64-ths", (uintptr_t)&a64_config },
347 { "allwinner,sun50i-h5-ths", (uintptr_t)&h5_config },
348 { NULL, (uintptr_t)NULL }
349 };
350
351 #define THS_CONF(d) \
352 (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
353
354 struct aw_thermal_softc {
355 device_t dev;
356 struct resource *res[2];
357 struct aw_thermal_config *conf;
358
359 struct task cf_task;
360 int throttle;
361 int min_freq;
362 struct cf_level levels[MAX_CF_LEVELS];
363 eventhandler_tag cf_pre_tag;
364
365 clk_t clk_apb;
366 clk_t clk_ths;
367 };
368
369 static struct resource_spec aw_thermal_spec[] = {
370 { SYS_RES_MEMORY, 0, RF_ACTIVE },
371 { SYS_RES_IRQ, 0, RF_ACTIVE },
372 { -1, 0 }
373 };
374
375 #define RD4(sc, reg) bus_read_4((sc)->res[0], (reg))
376 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
377
378 static int
aw_thermal_init(struct aw_thermal_softc * sc)379 aw_thermal_init(struct aw_thermal_softc *sc)
380 {
381 phandle_t node;
382 uint32_t calib[2];
383 int error;
384
385 node = ofw_bus_get_node(sc->dev);
386 if (nvmem_get_cell_len(node, "calibration") > sizeof(calib)) {
387 device_printf(sc->dev, "calibration nvmem cell is too large\n");
388 return (ENXIO);
389 }
390 error = nvmem_read_cell_by_name(node, "calibration",
391 (void *)&calib, nvmem_get_cell_len(node, "calibration"));
392 /* Read calibration settings from EFUSE */
393 if (error != 0) {
394 device_printf(sc->dev, "Cannot read THS efuse\n");
395 return (error);
396 }
397
398 calib[0] &= sc->conf->calib0_mask;
399 calib[1] &= sc->conf->calib1_mask;
400
401 /* Write calibration settings to thermal controller */
402 if (calib[0] != 0)
403 WR4(sc, THS_CALIB0, calib[0]);
404 if (calib[1] != 0)
405 WR4(sc, THS_CALIB1, calib[1]);
406
407 /* Configure ADC acquire time (CLK_IN/(N+1)) and enable sensors */
408 WR4(sc, THS_CTRL1, ADC_CALI_EN);
409 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time);
410 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT);
411
412 /* Set thermal period */
413 WR4(sc, THS_INTC, sc->conf->thermal_per << THS_THERMAL_PER_SHIFT);
414
415 /* Enable average filter */
416 WR4(sc, THS_FILTER, sc->conf->filter);
417
418 /* Enable interrupts */
419 WR4(sc, THS_INTS, RD4(sc, THS_INTS));
420 WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL);
421
422 /* Enable sensors */
423 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);
424
425 return (0);
426 }
427
428 static int
aw_thermal_gettemp(struct aw_thermal_softc * sc,int sensor)429 aw_thermal_gettemp(struct aw_thermal_softc *sc, int sensor)
430 {
431 uint32_t val;
432
433 val = RD4(sc, THS_DATA0 + (sensor * 4));
434
435 return (sc->conf->to_temp(val, sensor));
436 }
437
438 static int
aw_thermal_getshut(struct aw_thermal_softc * sc,int sensor)439 aw_thermal_getshut(struct aw_thermal_softc *sc, int sensor)
440 {
441 uint32_t val;
442
443 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
444 val = (val >> SHUT_T_HOT_SHIFT) & SHUT_T_HOT_MASK;
445
446 return (sc->conf->to_temp(val, sensor));
447 }
448
449 static void
aw_thermal_setshut(struct aw_thermal_softc * sc,int sensor,int temp)450 aw_thermal_setshut(struct aw_thermal_softc *sc, int sensor, int temp)
451 {
452 uint32_t val;
453
454 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
455 val &= ~(SHUT_T_HOT_MASK << SHUT_T_HOT_SHIFT);
456 val |= (sc->conf->to_reg(temp, sensor) << SHUT_T_HOT_SHIFT);
457 WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val);
458 }
459
460 static int
aw_thermal_gethyst(struct aw_thermal_softc * sc,int sensor)461 aw_thermal_gethyst(struct aw_thermal_softc *sc, int sensor)
462 {
463 uint32_t val;
464
465 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
466 val = (val >> ALARM_T_HYST_SHIFT) & ALARM_T_HYST_MASK;
467
468 return (sc->conf->to_temp(val, sensor));
469 }
470
471 static int
aw_thermal_getalarm(struct aw_thermal_softc * sc,int sensor)472 aw_thermal_getalarm(struct aw_thermal_softc *sc, int sensor)
473 {
474 uint32_t val;
475
476 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
477 val = (val >> ALARM_T_HOT_SHIFT) & ALARM_T_HOT_MASK;
478
479 return (sc->conf->to_temp(val, sensor));
480 }
481
482 static void
aw_thermal_setalarm(struct aw_thermal_softc * sc,int sensor,int temp)483 aw_thermal_setalarm(struct aw_thermal_softc *sc, int sensor, int temp)
484 {
485 uint32_t val;
486
487 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
488 val &= ~(ALARM_T_HOT_MASK << ALARM_T_HOT_SHIFT);
489 val |= (sc->conf->to_reg(temp, sensor) << ALARM_T_HOT_SHIFT);
490 WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val);
491 }
492
493 static int
aw_thermal_sysctl(SYSCTL_HANDLER_ARGS)494 aw_thermal_sysctl(SYSCTL_HANDLER_ARGS)
495 {
496 struct aw_thermal_softc *sc;
497 int sensor, val;
498
499 sc = arg1;
500 sensor = arg2;
501
502 val = aw_thermal_gettemp(sc, sensor) + TEMP_C_TO_K;
503
504 return sysctl_handle_opaque(oidp, &val, sizeof(val), req);
505 }
506
507 static void
aw_thermal_throttle(struct aw_thermal_softc * sc,int enable)508 aw_thermal_throttle(struct aw_thermal_softc *sc, int enable)
509 {
510 device_t cf_dev;
511 int count, error;
512
513 if (enable == sc->throttle)
514 return;
515
516 if (enable != 0) {
517 /* Set the lowest available frequency */
518 cf_dev = devclass_get_device(devclass_find("cpufreq"), 0);
519 if (cf_dev == NULL)
520 return;
521 count = MAX_CF_LEVELS;
522 error = CPUFREQ_LEVELS(cf_dev, sc->levels, &count);
523 if (error != 0 || count == 0)
524 return;
525 sc->min_freq = sc->levels[count - 1].total_set.freq;
526 error = CPUFREQ_SET(cf_dev, &sc->levels[count - 1],
527 CPUFREQ_PRIO_USER);
528 if (error != 0)
529 return;
530 }
531
532 sc->throttle = enable;
533 }
534
535 static void
aw_thermal_cf_task(void * arg,int pending)536 aw_thermal_cf_task(void *arg, int pending)
537 {
538 struct aw_thermal_softc *sc;
539
540 sc = arg;
541
542 aw_thermal_throttle(sc, 1);
543 }
544
545 static void
aw_thermal_cf_pre_change(void * arg,const struct cf_level * level,int * status)546 aw_thermal_cf_pre_change(void *arg, const struct cf_level *level, int *status)
547 {
548 struct aw_thermal_softc *sc;
549 int temp_cur, temp_alarm;
550
551 sc = arg;
552
553 if (aw_thermal_throttle_enable == 0 || sc->throttle == 0 ||
554 level->total_set.freq == sc->min_freq)
555 return;
556
557 temp_cur = aw_thermal_gettemp(sc, 0);
558 temp_alarm = aw_thermal_getalarm(sc, 0);
559
560 if (temp_cur < temp_alarm)
561 aw_thermal_throttle(sc, 0);
562 else
563 *status = ENXIO;
564 }
565
566 static void
aw_thermal_intr(void * arg)567 aw_thermal_intr(void *arg)
568 {
569 struct aw_thermal_softc *sc;
570 device_t dev;
571 uint32_t ints;
572
573 dev = arg;
574 sc = device_get_softc(dev);
575
576 ints = RD4(sc, THS_INTS);
577 WR4(sc, THS_INTS, ints);
578
579 if ((ints & SHUT_INT_ALL) != 0) {
580 device_printf(dev,
581 "WARNING - current temperature exceeds safe limits\n");
582 shutdown_nice(RB_POWEROFF);
583 }
584
585 if ((ints & ALARM_INT_ALL) != 0)
586 taskqueue_enqueue(taskqueue_thread, &sc->cf_task);
587 }
588
589 static int
aw_thermal_probe(device_t dev)590 aw_thermal_probe(device_t dev)
591 {
592 if (!ofw_bus_status_okay(dev))
593 return (ENXIO);
594
595 if (THS_CONF(dev) == NULL)
596 return (ENXIO);
597
598 device_set_desc(dev, "Allwinner Thermal Sensor Controller");
599 return (BUS_PROBE_DEFAULT);
600 }
601
602 static int
aw_thermal_attach(device_t dev)603 aw_thermal_attach(device_t dev)
604 {
605 struct aw_thermal_softc *sc;
606 hwreset_t rst;
607 int i, error;
608 void *ih;
609
610 sc = device_get_softc(dev);
611 sc->dev = dev;
612 rst = NULL;
613 ih = NULL;
614
615 sc->conf = THS_CONF(dev);
616 TASK_INIT(&sc->cf_task, 0, aw_thermal_cf_task, sc);
617
618 if (bus_alloc_resources(dev, aw_thermal_spec, sc->res) != 0) {
619 device_printf(dev, "cannot allocate resources for device\n");
620 return (ENXIO);
621 }
622
623 if (clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_apb) == 0) {
624 error = clk_enable(sc->clk_apb);
625 if (error != 0) {
626 device_printf(dev, "cannot enable apb clock\n");
627 goto fail;
628 }
629 }
630
631 if (clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_ths) == 0) {
632 error = clk_set_freq(sc->clk_ths, sc->conf->clk_rate, 0);
633 if (error != 0) {
634 device_printf(dev, "cannot set ths clock rate\n");
635 goto fail;
636 }
637 error = clk_enable(sc->clk_ths);
638 if (error != 0) {
639 device_printf(dev, "cannot enable ths clock\n");
640 goto fail;
641 }
642 }
643
644 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
645 error = hwreset_deassert(rst);
646 if (error != 0) {
647 device_printf(dev, "cannot de-assert reset\n");
648 goto fail;
649 }
650 }
651
652 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
653 NULL, aw_thermal_intr, dev, &ih);
654 if (error != 0) {
655 device_printf(dev, "cannot setup interrupt handler\n");
656 goto fail;
657 }
658
659 for (i = 0; i < sc->conf->nsensors; i++) {
660 if (sc->conf->sensors[i].init_alarm > 0)
661 aw_thermal_setalarm(sc, i,
662 sc->conf->sensors[i].init_alarm);
663 if (sc->conf->sensors[i].init_shut > 0)
664 aw_thermal_setshut(sc, i,
665 sc->conf->sensors[i].init_shut);
666 }
667
668 if (aw_thermal_init(sc) != 0)
669 goto fail;
670
671 for (i = 0; i < sc->conf->nsensors; i++)
672 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
673 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
674 OID_AUTO, sc->conf->sensors[i].name,
675 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
676 sc, i, aw_thermal_sysctl, "IK0",
677 sc->conf->sensors[i].desc);
678
679 if (bootverbose)
680 for (i = 0; i < sc->conf->nsensors; i++) {
681 device_printf(dev,
682 "%s: alarm %dC hyst %dC shut %dC\n",
683 sc->conf->sensors[i].name,
684 aw_thermal_getalarm(sc, i),
685 aw_thermal_gethyst(sc, i),
686 aw_thermal_getshut(sc, i));
687 }
688
689 sc->cf_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change,
690 aw_thermal_cf_pre_change, sc, EVENTHANDLER_PRI_FIRST);
691
692 return (0);
693
694 fail:
695 if (ih != NULL)
696 bus_teardown_intr(dev, sc->res[1], ih);
697 if (rst != NULL)
698 hwreset_release(rst);
699 if (sc->clk_apb != NULL)
700 clk_release(sc->clk_apb);
701 if (sc->clk_ths != NULL)
702 clk_release(sc->clk_ths);
703 bus_release_resources(dev, aw_thermal_spec, sc->res);
704
705 return (ENXIO);
706 }
707
708 static device_method_t aw_thermal_methods[] = {
709 /* Device interface */
710 DEVMETHOD(device_probe, aw_thermal_probe),
711 DEVMETHOD(device_attach, aw_thermal_attach),
712
713 DEVMETHOD_END
714 };
715
716 static driver_t aw_thermal_driver = {
717 "aw_thermal",
718 aw_thermal_methods,
719 sizeof(struct aw_thermal_softc),
720 };
721
722 DRIVER_MODULE(aw_thermal, simplebus, aw_thermal_driver, 0, 0);
723 MODULE_VERSION(aw_thermal, 1);
724 MODULE_DEPEND(aw_thermal, aw_sid, 1, 1, 1);
725 SIMPLEBUS_PNP_INFO(compat_data);
726