1 /*-
2 * Copyright (c) 2018 Ruslan Bukin <[email protected]>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/rman.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <machine/bus.h>
41
42 #include <arm64/coresight/coresight.h>
43 #include <arm64/coresight/coresight-tmc.h>
44
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47
48 #include "coresight_if.h"
49
50 #define TMC_DEBUG
51 #undef TMC_DEBUG
52
53 #ifdef TMC_DEBUG
54 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
55 #else
56 #define dprintf(fmt, ...)
57 #endif
58
59 static struct ofw_compat_data compat_data[] = {
60 { "arm,coresight-tmc", 1 },
61 { NULL, 0 }
62 };
63
64 struct tmc_softc {
65 struct resource *res;
66 device_t dev;
67 uint64_t cycle;
68 struct coresight_platform_data *pdata;
69 uint32_t dev_type;
70 #define CORESIGHT_UNKNOWN 0
71 #define CORESIGHT_ETR 1
72 #define CORESIGHT_ETF 2
73 uint32_t nev;
74 struct coresight_event *event;
75 boolean_t etf_configured;
76 };
77
78 static struct resource_spec tmc_spec[] = {
79 { SYS_RES_MEMORY, 0, RF_ACTIVE },
80 { -1, 0 }
81 };
82
83 static int
tmc_start(device_t dev)84 tmc_start(device_t dev)
85 {
86 struct tmc_softc *sc;
87 uint32_t reg;
88
89 sc = device_get_softc(dev);
90
91 if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN)
92 return (-1);
93
94 /* Enable TMC */
95 bus_write_4(sc->res, TMC_CTL, CTL_TRACECAPTEN);
96 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)
97 panic("Not enabled\n");
98
99 do {
100 reg = bus_read_4(sc->res, TMC_STS);
101 } while ((reg & STS_TMCREADY) == 1);
102
103 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)
104 panic("Not enabled\n");
105
106 return (0);
107 }
108
109 static int
tmc_stop(device_t dev)110 tmc_stop(device_t dev)
111 {
112 struct tmc_softc *sc;
113 uint32_t reg;
114
115 sc = device_get_softc(dev);
116
117 reg = bus_read_4(sc->res, TMC_CTL);
118 reg &= ~CTL_TRACECAPTEN;
119 bus_write_4(sc->res, TMC_CTL, reg);
120
121 do {
122 reg = bus_read_4(sc->res, TMC_STS);
123 } while ((reg & STS_TMCREADY) == 1);
124
125 return (0);
126 }
127
128 static int
tmc_configure_etf(device_t dev)129 tmc_configure_etf(device_t dev)
130 {
131 struct tmc_softc *sc;
132 uint32_t reg;
133
134 sc = device_get_softc(dev);
135
136 do {
137 reg = bus_read_4(sc->res, TMC_STS);
138 } while ((reg & STS_TMCREADY) == 0);
139
140 bus_write_4(sc->res, TMC_MODE, MODE_HW_FIFO);
141 bus_write_4(sc->res, TMC_FFCR, FFCR_EN_FMT | FFCR_EN_TI);
142
143 tmc_start(dev);
144
145 dprintf("%s: STS %x, CTL %x, RSZ %x, RRP %x, RWP %x, "
146 "LBUFLEVEL %x, CBUFLEVEL %x\n", __func__,
147 bus_read_4(sc->res, TMC_STS),
148 bus_read_4(sc->res, TMC_CTL),
149 bus_read_4(sc->res, TMC_RSZ),
150 bus_read_4(sc->res, TMC_RRP),
151 bus_read_4(sc->res, TMC_RWP),
152 bus_read_4(sc->res, TMC_CBUFLEVEL),
153 bus_read_4(sc->res, TMC_LBUFLEVEL));
154
155 return (0);
156 }
157
158 static int
tmc_configure_etr(device_t dev,struct endpoint * endp,struct coresight_event * event)159 tmc_configure_etr(device_t dev, struct endpoint *endp,
160 struct coresight_event *event)
161 {
162 struct tmc_softc *sc;
163 uint32_t reg;
164
165 sc = device_get_softc(dev);
166
167 tmc_stop(dev);
168
169 do {
170 reg = bus_read_4(sc->res, TMC_STS);
171 } while ((reg & STS_TMCREADY) == 0);
172
173 /* Configure TMC */
174 bus_write_4(sc->res, TMC_MODE, MODE_CIRCULAR_BUFFER);
175
176 reg = AXICTL_PROT_CTRL_BIT1;
177 reg |= AXICTL_WRBURSTLEN_16;
178
179 /*
180 * SG operation is broken on DragonBoard 410c
181 * reg |= AXICTL_SG_MODE;
182 */
183
184 reg |= AXICTL_AXCACHE_OS;
185 bus_write_4(sc->res, TMC_AXICTL, reg);
186
187 reg = FFCR_EN_FMT | FFCR_EN_TI | FFCR_FON_FLIN |
188 FFCR_FON_TRIG_EVT | FFCR_TRIGON_TRIGIN;
189 bus_write_4(sc->res, TMC_FFCR, reg);
190
191 bus_write_4(sc->res, TMC_TRG, 8);
192
193 bus_write_4(sc->res, TMC_DBALO, event->etr.low);
194 bus_write_4(sc->res, TMC_DBAHI, event->etr.high);
195 bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4);
196
197 bus_write_4(sc->res, TMC_RRP, event->etr.low);
198 bus_write_4(sc->res, TMC_RWP, event->etr.low);
199
200 reg = bus_read_4(sc->res, TMC_STS);
201 reg &= ~STS_FULL;
202 bus_write_4(sc->res, TMC_STS, reg);
203
204 tmc_start(dev);
205
206 return (0);
207 }
208
209 static int
tmc_init(device_t dev)210 tmc_init(device_t dev)
211 {
212 struct tmc_softc *sc;
213 uint32_t reg;
214
215 sc = device_get_softc(dev);
216
217 /* Unlock Coresight */
218 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
219
220 /* Unlock TMC */
221 bus_write_4(sc->res, TMC_LAR, CORESIGHT_UNLOCK);
222
223 reg = bus_read_4(sc->res, TMC_DEVID);
224 reg &= DEVID_CONFIGTYPE_M;
225 switch (reg) {
226 case DEVID_CONFIGTYPE_ETR:
227 sc->dev_type = CORESIGHT_ETR;
228 dprintf(dev, "ETR configuration found\n");
229 break;
230 case DEVID_CONFIGTYPE_ETF:
231 sc->dev_type = CORESIGHT_ETF;
232 dprintf(dev, "ETF configuration found\n");
233 if (sc->etf_configured == false) {
234 tmc_configure_etf(dev);
235 sc->etf_configured = true;
236 }
237 break;
238 default:
239 sc->dev_type = CORESIGHT_UNKNOWN;
240 break;
241 }
242
243 return (0);
244 }
245
246 static int
tmc_enable(device_t dev,struct endpoint * endp,struct coresight_event * event)247 tmc_enable(device_t dev, struct endpoint *endp,
248 struct coresight_event *event)
249 {
250 struct tmc_softc *sc;
251 uint32_t nev;
252
253 sc = device_get_softc(dev);
254
255 if (sc->dev_type == CORESIGHT_ETF)
256 return (0);
257
258 KASSERT(sc->dev_type == CORESIGHT_ETR,
259 ("Wrong dev_type"));
260
261 /*
262 * Multiple CPUs can call this same time.
263 * We allow only one running configuration.
264 */
265
266 if (event->etr.flags & ETR_FLAG_ALLOCATE) {
267 event->etr.flags &= ~ETR_FLAG_ALLOCATE;
268 nev = atomic_fetchadd_int(&sc->nev, 1);
269 if (nev == 0) {
270 sc->event = event;
271 tmc_stop(dev);
272 tmc_configure_etr(dev, endp, event);
273 tmc_start(dev);
274 }
275 }
276
277 return (0);
278 }
279
280 static void
tmc_disable(device_t dev,struct endpoint * endp,struct coresight_event * event)281 tmc_disable(device_t dev, struct endpoint *endp,
282 struct coresight_event *event)
283 {
284 struct tmc_softc *sc;
285 uint32_t nev;
286
287 sc = device_get_softc(dev);
288
289 /* ETF configuration is static */
290 if (sc->dev_type == CORESIGHT_ETF)
291 return;
292
293 KASSERT(sc->dev_type == CORESIGHT_ETR, ("Wrong dev_type"));
294
295 if (event->etr.flags & ETR_FLAG_RELEASE) {
296 event->etr.flags &= ~ETR_FLAG_RELEASE;
297 nev = atomic_fetchadd_int(&sc->nev, -1);
298 if (nev == 1) {
299 tmc_stop(dev);
300 sc->event = NULL;
301 }
302 }
303 }
304
305 static int
tmc_read(device_t dev,struct endpoint * endp,struct coresight_event * event)306 tmc_read(device_t dev, struct endpoint *endp,
307 struct coresight_event *event)
308 {
309 struct tmc_softc *sc;
310 uint32_t cur_ptr;
311
312 sc = device_get_softc(dev);
313
314 if (sc->dev_type == CORESIGHT_ETF)
315 return (0);
316
317 /*
318 * Ensure the event we are reading information for
319 * is currently configured one.
320 */
321 if (sc->event != event)
322 return (0);
323
324 if (bus_read_4(sc->res, TMC_STS) & STS_FULL) {
325 event->etr.offset = 0;
326 event->etr.cycle++;
327 tmc_stop(dev);
328 tmc_start(dev);
329 } else {
330 cur_ptr = bus_read_4(sc->res, TMC_RWP);
331 event->etr.offset = (cur_ptr - event->etr.low);
332 }
333
334 return (0);
335 }
336
337 static int
tmc_probe(device_t dev)338 tmc_probe(device_t dev)
339 {
340
341 if (!ofw_bus_status_okay(dev))
342 return (ENXIO);
343
344 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
345 return (ENXIO);
346
347 device_set_desc(dev, "Coresight Trace Memory Controller (TMC)");
348
349 return (BUS_PROBE_DEFAULT);
350 }
351
352 static int
tmc_attach(device_t dev)353 tmc_attach(device_t dev)
354 {
355 struct coresight_desc desc;
356 struct tmc_softc *sc;
357
358 sc = device_get_softc(dev);
359
360 sc->dev = dev;
361
362 if (bus_alloc_resources(dev, tmc_spec, &sc->res) != 0) {
363 device_printf(dev, "cannot allocate resources for device\n");
364 return (ENXIO);
365 }
366
367 sc->pdata = coresight_get_platform_data(dev);
368 desc.pdata = sc->pdata;
369 desc.dev = dev;
370 desc.dev_type = CORESIGHT_TMC;
371 coresight_register(&desc);
372
373 return (0);
374 }
375
376 static device_method_t tmc_methods[] = {
377 /* Device interface */
378 DEVMETHOD(device_probe, tmc_probe),
379 DEVMETHOD(device_attach, tmc_attach),
380
381 /* Coresight interface */
382 DEVMETHOD(coresight_init, tmc_init),
383 DEVMETHOD(coresight_enable, tmc_enable),
384 DEVMETHOD(coresight_disable, tmc_disable),
385 DEVMETHOD(coresight_read, tmc_read),
386 DEVMETHOD_END
387 };
388
389 static driver_t tmc_driver = {
390 "tmc",
391 tmc_methods,
392 sizeof(struct tmc_softc),
393 };
394
395 static devclass_t tmc_devclass;
396
397 DRIVER_MODULE(tmc, simplebus, tmc_driver, tmc_devclass, 0, 0);
398 MODULE_VERSION(tmc, 1);
399