1 /*
2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <[email protected]> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <[email protected]>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
17 * distribution.
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * Intel fourth generation mobile cpus integrated I2C device.
39 *
40 * See ig4_reg.h for datasheet reference and notes.
41 * See ig4_var.h for locking semantics.
42 */
43
44 #include "opt_acpi.h"
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/errno.h>
51 #include <sys/kdb.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/proc.h>
55 #include <sys/sx.h>
56 #include <sys/syslog.h>
57 #include <sys/bus.h>
58 #include <sys/sysctl.h>
59
60 #include <machine/bus.h>
61 #include <sys/rman.h>
62
63 #ifdef DEV_ACPI
64 #include <contrib/dev/acpica/include/acpi.h>
65 #include <contrib/dev/acpica/include/accommon.h>
66 #include <dev/acpica/acpivar.h>
67 #endif
68
69 #include <dev/iicbus/iicbus.h>
70 #include <dev/iicbus/iiconf.h>
71
72 #include <dev/ichiic/ig4_reg.h>
73 #include <dev/ichiic/ig4_var.h>
74
75 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll)
76
77 /*
78 * tLOW, tHIGH periods of the SCL clock and maximal falling time of both
79 * lines are taken from I2C specifications.
80 */
81 #define IG4_SPEED_STD_THIGH 4000 /* nsec */
82 #define IG4_SPEED_STD_TLOW 4700 /* nsec */
83 #define IG4_SPEED_STD_TF_MAX 300 /* nsec */
84 #define IG4_SPEED_FAST_THIGH 600 /* nsec */
85 #define IG4_SPEED_FAST_TLOW 1300 /* nsec */
86 #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */
87
88 /*
89 * Ig4 hardware parameters except Haswell are taken from intel_lpss driver
90 */
91 static const struct ig4_hw ig4iic_hw[] = {
92 [IG4_HASWELL] = {
93 .ic_clock_rate = 100, /* MHz */
94 .sda_hold_time = 90, /* nsec */
95 .txfifo_depth = 32,
96 .rxfifo_depth = 32,
97 },
98 [IG4_ATOM] = {
99 .ic_clock_rate = 100,
100 .sda_fall_time = 280,
101 .scl_fall_time = 240,
102 .sda_hold_time = 60,
103 .txfifo_depth = 32,
104 .rxfifo_depth = 32,
105 },
106 [IG4_SKYLAKE] = {
107 .ic_clock_rate = 120,
108 .sda_hold_time = 230,
109 },
110 [IG4_APL] = {
111 .ic_clock_rate = 133,
112 .sda_fall_time = 171,
113 .scl_fall_time = 208,
114 .sda_hold_time = 207,
115 },
116 [IG4_CANNONLAKE] = {
117 .ic_clock_rate = 216,
118 .sda_hold_time = 230,
119 },
120 [IG4_TIGERLAKE] = {
121 .ic_clock_rate = 133,
122 .sda_fall_time = 171,
123 .scl_fall_time = 208,
124 .sda_hold_time = 42,
125 },
126 [IG4_GEMINILAKE] = {
127 .ic_clock_rate = 133,
128 .sda_fall_time = 171,
129 .scl_fall_time = 290,
130 .sda_hold_time = 313,
131 },
132 };
133
134 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
135 static driver_filter_t ig4iic_intr;
136 static void ig4iic_dump(ig4iic_softc_t *sc);
137
138 static int ig4_dump;
139 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
140 &ig4_dump, 0, "Dump controller registers");
141
142 /*
143 * Clock registers initialization control
144 * 0 - Try read clock registers from ACPI and fallback to p.1.
145 * 1 - Calculate values based on controller type (IC clock rate).
146 * 2 - Use values inherited from DragonflyBSD driver (old behavior).
147 * 3 - Keep clock registers intact.
148 */
149 static int ig4_timings;
150 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0,
151 "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change");
152
153 /*
154 * Low-level inline support functions
155 */
156 static __inline void
reg_write(ig4iic_softc_t * sc,uint32_t reg,uint32_t value)157 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
158 {
159 bus_write_4(sc->regs_res, reg, value);
160 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
161 }
162
163 static __inline uint32_t
reg_read(ig4iic_softc_t * sc,uint32_t reg)164 reg_read(ig4iic_softc_t *sc, uint32_t reg)
165 {
166 uint32_t value;
167
168 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
169 value = bus_read_4(sc->regs_res, reg);
170 return (value);
171 }
172
173 static void
ig4iic_set_intr_mask(ig4iic_softc_t * sc,uint32_t val)174 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val)
175 {
176 if (sc->intr_mask != val) {
177 reg_write(sc, IG4_REG_INTR_MASK, val);
178 sc->intr_mask = val;
179 }
180 }
181
182 static int
intrstat2iic(ig4iic_softc_t * sc,uint32_t val)183 intrstat2iic(ig4iic_softc_t *sc, uint32_t val)
184 {
185 uint32_t src;
186
187 if (val & IG4_INTR_RX_UNDER)
188 reg_read(sc, IG4_REG_CLR_RX_UNDER);
189 if (val & IG4_INTR_RX_OVER)
190 reg_read(sc, IG4_REG_CLR_RX_OVER);
191 if (val & IG4_INTR_TX_OVER)
192 reg_read(sc, IG4_REG_CLR_TX_OVER);
193
194 if (val & IG4_INTR_TX_ABRT) {
195 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
196 reg_read(sc, IG4_REG_CLR_TX_ABORT);
197 /* User-requested abort. Not really a error */
198 if (src & IG4_ABRTSRC_TRANSFER)
199 return (IIC_ESTATUS);
200 /* Master has lost arbitration */
201 if (src & IG4_ABRTSRC_ARBLOST)
202 return (IIC_EBUSBSY);
203 /* Did not receive an acknowledge from the remote slave */
204 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 |
205 IG4_ABRTSRC_TXNOACK_ADDR10_1 |
206 IG4_ABRTSRC_TXNOACK_ADDR10_2 |
207 IG4_ABRTSRC_TXNOACK_DATA |
208 IG4_ABRTSRC_GENCALL_NOACK))
209 return (IIC_ENOACK);
210 /* Programming errors */
211 if (src & (IG4_ABRTSRC_GENCALL_READ |
212 IG4_ABRTSRC_NORESTART_START |
213 IG4_ABRTSRC_NORESTART_10))
214 return (IIC_ENOTSUPP);
215 /* Other errors */
216 if (src & IG4_ABRTSRC_ACKED_START)
217 return (IIC_EBUSERR);
218 }
219 /*
220 * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth
221 * detection or driver's read/write pipelining errors.
222 */
223 if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER))
224 return (IIC_EOVERFLOW);
225 if (val & IG4_INTR_RX_UNDER)
226 return (IIC_EUNDERFLOW);
227
228 return (IIC_NOERR);
229 }
230
231 /*
232 * Enable or disable the controller and wait for the controller to acknowledge
233 * the state change.
234 */
235 static int
set_controller(ig4iic_softc_t * sc,uint32_t ctl)236 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
237 {
238 int retry;
239 int error;
240 uint32_t v;
241
242 /*
243 * When the controller is enabled, interrupt on STOP detect
244 * or receive character ready and clear pending interrupts.
245 */
246 ig4iic_set_intr_mask(sc, 0);
247 if (ctl & IG4_I2C_ENABLE)
248 reg_read(sc, IG4_REG_CLR_INTR);
249
250 reg_write(sc, IG4_REG_I2C_EN, ctl);
251 error = IIC_ETIMEOUT;
252
253 for (retry = 100; retry > 0; --retry) {
254 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
255 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
256 error = 0;
257 break;
258 }
259 pause("i2cslv", 1);
260 }
261 return (error);
262 }
263
264 /*
265 * Wait up to 25ms for the requested interrupt using a 25uS polling loop.
266 */
267 static int
wait_intr(ig4iic_softc_t * sc,uint32_t intr)268 wait_intr(ig4iic_softc_t *sc, uint32_t intr)
269 {
270 uint32_t v;
271 int error;
272 int txlvl = -1;
273 u_int count_us = 0;
274 u_int limit_us = 1000000; /* 1sec */
275
276 for (;;) {
277 /*
278 * Check requested status
279 */
280 v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
281 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK);
282 if (error || (v & intr))
283 break;
284
285 /*
286 * When waiting for the transmit FIFO to become empty,
287 * reset the timeout if we see a change in the transmit
288 * FIFO level as progress is being made.
289 */
290 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) {
291 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
292 if (txlvl != v) {
293 txlvl = v;
294 count_us = 0;
295 }
296 }
297
298 /*
299 * Stop if we've run out of time.
300 */
301 if (count_us >= limit_us) {
302 error = IIC_ETIMEOUT;
303 break;
304 }
305
306 /*
307 * When polling is not requested let the interrupt do its work.
308 */
309 if (!DO_POLL(sc)) {
310 mtx_lock_spin(&sc->io_lock);
311 ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK);
312 msleep_spin(sc, &sc->io_lock, "i2cwait",
313 (hz + 99) / 100); /* sleep up to 10ms */
314 ig4iic_set_intr_mask(sc, 0);
315 mtx_unlock_spin(&sc->io_lock);
316 count_us += 10000;
317 } else {
318 DELAY(25);
319 count_us += 25;
320 }
321 }
322
323 return (error);
324 }
325
326 /*
327 * Set the slave address. The controller must be disabled when
328 * changing the address.
329 *
330 * This operation does not issue anything to the I2C bus but sets
331 * the target address for when the controller later issues a START.
332 */
333 static void
set_slave_addr(ig4iic_softc_t * sc,uint8_t slave)334 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)
335 {
336 uint32_t tar;
337 uint32_t ctl;
338 bool use_10bit;
339
340 use_10bit = false;
341 if (sc->slave_valid && sc->last_slave == slave &&
342 sc->use_10bit == use_10bit) {
343 return;
344 }
345 sc->use_10bit = use_10bit;
346
347 /*
348 * Wait for TXFIFO to drain before disabling the controller.
349 */
350 reg_write(sc, IG4_REG_TX_TL, 0);
351 wait_intr(sc, IG4_INTR_TX_EMPTY);
352
353 set_controller(sc, 0);
354 ctl = reg_read(sc, IG4_REG_CTL);
355 ctl &= ~IG4_CTL_10BIT;
356 ctl |= IG4_CTL_RESTARTEN;
357
358 tar = slave;
359 if (sc->use_10bit) {
360 tar |= IG4_TAR_10BIT;
361 ctl |= IG4_CTL_10BIT;
362 }
363 reg_write(sc, IG4_REG_CTL, ctl);
364 reg_write(sc, IG4_REG_TAR_ADD, tar);
365 set_controller(sc, IG4_I2C_ENABLE);
366 sc->slave_valid = true;
367 sc->last_slave = slave;
368 }
369
370 /*
371 * IICBUS API FUNCTIONS
372 */
373 static int
ig4iic_xfer_start(ig4iic_softc_t * sc,uint16_t slave,bool repeated_start)374 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start)
375 {
376 set_slave_addr(sc, slave >> 1);
377
378 if (!repeated_start) {
379 /*
380 * Clear any previous TX/RX FIFOs overflow/underflow bits
381 * and I2C bus STOP condition.
382 */
383 reg_read(sc, IG4_REG_CLR_INTR);
384 }
385
386 return (0);
387 }
388
389 static bool
ig4iic_xfer_is_started(ig4iic_softc_t * sc)390 ig4iic_xfer_is_started(ig4iic_softc_t *sc)
391 {
392 /*
393 * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET
394 * register reads is issued after START condition.
395 */
396 return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
397 (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET);
398 }
399
400 static int
ig4iic_xfer_abort(ig4iic_softc_t * sc)401 ig4iic_xfer_abort(ig4iic_softc_t *sc)
402 {
403 int error;
404
405 /* Request send of STOP condition and flush of TX FIFO */
406 set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE);
407 /*
408 * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER
409 * bit set in TX_ABRT_SOURCE register.
410 */
411 error = wait_intr(sc, IG4_INTR_STOP_DET);
412 set_controller(sc, IG4_I2C_ENABLE);
413
414 return (error == IIC_ESTATUS ? 0 : error);
415 }
416
417 /*
418 * Amount of unread data before next burst to get better I2C bus utilization.
419 * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes.
420 * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs.
421 */
422 #define IG4_FIFO_LOWAT 2
423
424 static int
ig4iic_read(ig4iic_softc_t * sc,uint8_t * buf,uint16_t len,bool repeated_start,bool stop)425 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
426 bool repeated_start, bool stop)
427 {
428 uint32_t cmd;
429 int requested = 0;
430 int received = 0;
431 int burst, target, lowat = 0;
432 int error;
433
434 if (len == 0)
435 return (0);
436
437 while (received < len) {
438 /* Ensure we have some free space in TXFIFO */
439 burst = sc->cfg.txfifo_depth -
440 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
441 if (burst <= 0) {
442 reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);
443 error = wait_intr(sc, IG4_INTR_TX_EMPTY);
444 if (error)
445 break;
446 burst = sc->cfg.txfifo_depth -
447 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
448 }
449 /* Ensure we have enough free space in RXFIFO */
450 burst = MIN(burst, sc->cfg.rxfifo_depth -
451 (requested - received));
452 target = MIN(requested + burst, (int)len);
453 while (requested < target) {
454 cmd = IG4_DATA_COMMAND_RD;
455 if (repeated_start && requested == 0)
456 cmd |= IG4_DATA_RESTART;
457 if (stop && requested == len - 1)
458 cmd |= IG4_DATA_STOP;
459 reg_write(sc, IG4_REG_DATA_CMD, cmd);
460 requested++;
461 }
462 /* Leave some data queued to maintain the hardware pipeline */
463 lowat = 0;
464 if (requested != len && requested - received > IG4_FIFO_LOWAT)
465 lowat = IG4_FIFO_LOWAT;
466 /* After TXFLR fills up, clear it by reading available data */
467 while (received < requested - lowat) {
468 burst = MIN(requested - received,
469 reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
470 if (burst > 0) {
471 while (burst--)
472 buf[received++] = 0xFF &
473 reg_read(sc, IG4_REG_DATA_CMD);
474 } else {
475 reg_write(sc, IG4_REG_RX_TL,
476 requested - received - lowat - 1);
477 error = wait_intr(sc, IG4_INTR_RX_FULL);
478 if (error)
479 goto out;
480 }
481 }
482 }
483 out:
484 return (error);
485 }
486
487 static int
ig4iic_write(ig4iic_softc_t * sc,uint8_t * buf,uint16_t len,bool repeated_start,bool stop)488 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
489 bool repeated_start, bool stop)
490 {
491 uint32_t cmd;
492 int sent = 0;
493 int burst, target;
494 int error, lowat;
495
496 if (len == 0)
497 return (0);
498
499 while (sent < len) {
500 burst = sc->cfg.txfifo_depth -
501 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
502 target = MIN(sent + burst, (int)len);
503 while (sent < target) {
504 cmd = buf[sent];
505 if (repeated_start && sent == 0)
506 cmd |= IG4_DATA_RESTART;
507 if (stop && sent == len - 1)
508 cmd |= IG4_DATA_STOP;
509 reg_write(sc, IG4_REG_DATA_CMD, cmd);
510 sent++;
511 }
512 if (sent < len) {
513 if (len - sent <= sc->cfg.txfifo_depth)
514 lowat = sc->cfg.txfifo_depth - (len - sent);
515 else
516 lowat = IG4_FIFO_LOWAT;
517 reg_write(sc, IG4_REG_TX_TL, lowat);
518 error = wait_intr(sc, IG4_INTR_TX_EMPTY);
519 if (error)
520 break;
521 }
522 }
523
524 return (error);
525 }
526
527 int
ig4iic_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)528 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
529 {
530 ig4iic_softc_t *sc = device_get_softc(dev);
531 const char *reason = NULL;
532 uint32_t i;
533 int error;
534 int unit;
535 bool rpstart;
536 bool stop;
537 bool allocated;
538
539 /*
540 * The hardware interface imposes limits on allowed I2C messages.
541 * It is not possible to explicitly send a start or stop.
542 * They are automatically sent (or not sent, depending on the
543 * configuration) when a data byte is transferred.
544 * For this reason it's impossible to send a message with no data
545 * at all (like an SMBus quick message).
546 * The start condition is automatically generated after the stop
547 * condition, so it's impossible to not have a start after a stop.
548 * The repeated start condition is automatically sent if a change
549 * of the transfer direction happens, so it's impossible to have
550 * a change of direction without a (repeated) start.
551 * The repeated start can be forced even without the change of
552 * direction.
553 * Changing the target slave address requires resetting the hardware
554 * state, so it's impossible to do that without the stop followed
555 * by the start.
556 */
557 for (i = 0; i < nmsgs; i++) {
558 #if 0
559 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) {
560 reason = "first message without start";
561 break;
562 }
563 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) {
564 reason = "last message without stop";
565 break;
566 }
567 #endif
568 if (msgs[i].len == 0) {
569 reason = "message with no data";
570 break;
571 }
572 if (i > 0) {
573 if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
574 (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) {
575 reason = "stop not followed by start";
576 break;
577 }
578 if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 &&
579 msgs[i].slave != msgs[i - 1].slave) {
580 reason = "change of slave without stop";
581 break;
582 }
583 if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
584 (msgs[i].flags & IIC_M_RD) !=
585 (msgs[i - 1].flags & IIC_M_RD)) {
586 reason = "change of direction without repeated"
587 " start";
588 break;
589 }
590 }
591 }
592 if (reason != NULL) {
593 if (bootverbose)
594 device_printf(dev, "%s\n", reason);
595 return (IIC_ENOTSUPP);
596 }
597
598 /* Check if device is already allocated with iicbus_request_bus() */
599 allocated = sx_xlocked(&sc->call_lock) != 0;
600 if (!allocated)
601 sx_xlock(&sc->call_lock);
602
603 /* Debugging - dump registers. */
604 if (ig4_dump) {
605 unit = device_get_unit(dev);
606 if (ig4_dump & (1 << unit)) {
607 ig4_dump &= ~(1 << unit);
608 ig4iic_dump(sc);
609 }
610 }
611
612 /*
613 * Clear any previous abort condition that may have been holding
614 * the txfifo in reset.
615 */
616 reg_read(sc, IG4_REG_CLR_TX_ABORT);
617
618 rpstart = false;
619 error = 0;
620 for (i = 0; i < nmsgs; i++) {
621 if ((msgs[i].flags & IIC_M_NOSTART) == 0) {
622 error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart);
623 } else {
624 if (!sc->slave_valid ||
625 (msgs[i].slave >> 1) != sc->last_slave) {
626 device_printf(dev, "start condition suppressed"
627 "but slave address is not set up");
628 error = EINVAL;
629 break;
630 }
631 rpstart = false;
632 }
633 if (error != 0)
634 break;
635
636 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0;
637 if (msgs[i].flags & IIC_M_RD)
638 error = ig4iic_read(sc, msgs[i].buf, msgs[i].len,
639 rpstart, stop);
640 else
641 error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,
642 rpstart, stop);
643
644 /* Wait for error or stop condition occurred on the I2C bus */
645 if (stop && error == 0) {
646 error = wait_intr(sc, IG4_INTR_STOP_DET);
647 if (error == 0)
648 reg_read(sc, IG4_REG_CLR_INTR);
649 }
650
651 if (error != 0) {
652 /*
653 * Send STOP condition if it's not done yet and flush
654 * both FIFOs. Do a controller soft reset if transfer
655 * abort is failed.
656 */
657 if (ig4iic_xfer_is_started(sc) &&
658 ig4iic_xfer_abort(sc) != 0) {
659 device_printf(sc->dev, "Failed to abort "
660 "transfer. Do the controller reset.\n");
661 ig4iic_set_config(sc, true);
662 } else {
663 while (reg_read(sc, IG4_REG_I2C_STA) &
664 IG4_STATUS_RX_NOTEMPTY)
665 reg_read(sc, IG4_REG_DATA_CMD);
666 reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
667 reg_read(sc, IG4_REG_CLR_INTR);
668 }
669 break;
670 }
671
672 rpstart = !stop;
673 }
674
675 if (!allocated)
676 sx_unlock(&sc->call_lock);
677 return (error);
678 }
679
680 int
ig4iic_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)681 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
682 {
683 ig4iic_softc_t *sc = device_get_softc(dev);
684 bool allocated;
685
686 allocated = sx_xlocked(&sc->call_lock) != 0;
687 if (!allocated)
688 sx_xlock(&sc->call_lock);
689
690 /* TODO handle speed configuration? */
691 if (oldaddr != NULL)
692 *oldaddr = sc->last_slave << 1;
693 set_slave_addr(sc, addr >> 1);
694 if (addr == IIC_UNKNOWN)
695 sc->slave_valid = false;
696
697 if (!allocated)
698 sx_unlock(&sc->call_lock);
699 return (0);
700 }
701
702 int
ig4iic_callback(device_t dev,int index,caddr_t data)703 ig4iic_callback(device_t dev, int index, caddr_t data)
704 {
705 ig4iic_softc_t *sc = device_get_softc(dev);
706 int error = 0;
707 int how;
708
709 switch (index) {
710 case IIC_REQUEST_BUS:
711 /* force polling if ig4iic is requested with IIC_DONTWAIT */
712 how = *(int *)data;
713 if ((how & IIC_WAIT) == 0) {
714 if (sx_try_xlock(&sc->call_lock) == 0)
715 error = IIC_EBUSBSY;
716 else
717 sc->poll = true;
718 } else
719 sx_xlock(&sc->call_lock);
720 break;
721
722 case IIC_RELEASE_BUS:
723 sc->poll = false;
724 sx_unlock(&sc->call_lock);
725 break;
726
727 default:
728 error = errno2iic(EINVAL);
729 }
730
731 return (error);
732 }
733
734 /*
735 * Clock register values can be calculated with following rough equations:
736 * SCL_HCNT = ceil(IC clock rate * tHIGH)
737 * SCL_LCNT = ceil(IC clock rate * tLOW)
738 * SDA_HOLD = ceil(IC clock rate * SDA hold time)
739 * Precise equations take signal's falling, rising and spike suppression
740 * times in to account. They can be found in Synopsys or Intel documentation.
741 *
742 * Here we snarf formulas and defaults from Linux driver to be able to use
743 * timing values provided by Intel LPSS driver "as is".
744 */
745 static int
ig4iic_clk_params(const struct ig4_hw * hw,int speed,uint16_t * scl_hcnt,uint16_t * scl_lcnt,uint16_t * sda_hold)746 ig4iic_clk_params(const struct ig4_hw *hw, int speed,
747 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
748 {
749 uint32_t thigh, tlow, tf_max; /* nsec */
750 uint32_t sda_fall_time; /* nsec */
751 uint32_t scl_fall_time; /* nsec */
752
753 switch (speed) {
754 case IG4_CTL_SPEED_STD:
755 thigh = IG4_SPEED_STD_THIGH;
756 tlow = IG4_SPEED_STD_TLOW;
757 tf_max = IG4_SPEED_STD_TF_MAX;
758 break;
759
760 case IG4_CTL_SPEED_FAST:
761 thigh = IG4_SPEED_FAST_THIGH;
762 tlow = IG4_SPEED_FAST_TLOW;
763 tf_max = IG4_SPEED_FAST_TF_MAX;
764 break;
765
766 default:
767 return (EINVAL);
768 }
769
770 /* Use slowest falling time defaults to be on the safe side */
771 sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time;
772 *scl_hcnt = (uint16_t)
773 ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3);
774
775 scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time;
776 *scl_lcnt = (uint16_t)
777 ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1);
778
779 /*
780 * There is no "known good" default value for tHD;DAT so keep SDA_HOLD
781 * intact if sda_hold_time value is not provided.
782 */
783 if (hw->sda_hold_time != 0)
784 *sda_hold = (uint16_t)
785 ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000);
786
787 return (0);
788 }
789
790 #ifdef DEV_ACPI
791 static ACPI_STATUS
ig4iic_acpi_params(ACPI_HANDLE handle,char * method,uint16_t * scl_hcnt,uint16_t * scl_lcnt,uint16_t * sda_hold)792 ig4iic_acpi_params(ACPI_HANDLE handle, char *method,
793 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
794 {
795 ACPI_BUFFER buf;
796 ACPI_OBJECT *obj, *elems;
797 ACPI_STATUS status;
798
799 buf.Pointer = NULL;
800 buf.Length = ACPI_ALLOCATE_BUFFER;
801
802 status = AcpiEvaluateObject(handle, method, NULL, &buf);
803 if (ACPI_FAILURE(status))
804 return (status);
805
806 status = AE_TYPE;
807 obj = (ACPI_OBJECT *)buf.Pointer;
808 if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) {
809 elems = obj->Package.Elements;
810 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK;
811 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK;
812 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK;
813 status = AE_OK;
814 }
815
816 AcpiOsFree(obj);
817
818 return (status);
819 }
820 #endif /* DEV_ACPI */
821
822 static void
ig4iic_get_config(ig4iic_softc_t * sc)823 ig4iic_get_config(ig4iic_softc_t *sc)
824 {
825 const struct ig4_hw *hw;
826 uint32_t v;
827 #ifdef DEV_ACPI
828 ACPI_HANDLE handle;
829 #endif
830 /* Fetch default hardware config from controller */
831 sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
832 sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
833 sc->cfg.ss_scl_hcnt =
834 reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
835 sc->cfg.ss_scl_lcnt =
836 reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
837 sc->cfg.fs_scl_hcnt =
838 reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
839 sc->cfg.fs_scl_lcnt =
840 reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
841 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold =
842 reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;
843
844 if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD)
845 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
846
847 /* REG_COMP_PARAM1 is not documented in latest Intel specs */
848 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
849 v = reg_read(sc, IG4_REG_COMP_PARAM1);
850 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0)
851 sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v);
852 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0)
853 sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v);
854 }
855
856 /* Override hardware config with IC_clock-based counter values */
857 if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) {
858 hw = &ig4iic_hw[sc->version];
859 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
860 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt,
861 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
862 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt,
863 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
864 if (hw->txfifo_depth != 0)
865 sc->cfg.txfifo_depth = hw->txfifo_depth;
866 if (hw->rxfifo_depth != 0)
867 sc->cfg.rxfifo_depth = hw->rxfifo_depth;
868 } else if (ig4_timings == 2) {
869 /*
870 * Timings of original ig4 driver:
871 * Program based on a 25000 Hz clock. This is a bit of a
872 * hack (obviously). The defaults are 400 and 470 for standard
873 * and 60 and 130 for fast. The defaults for standard fail
874 * utterly (presumably cause an abort) because the clock time
875 * is ~18.8ms by default. This brings it down to ~4ms.
876 */
877 sc->cfg.bus_speed = IG4_CTL_SPEED_STD;
878 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100;
879 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125;
880 if (sc->version == IG4_SKYLAKE)
881 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28;
882 }
883
884 #ifdef DEV_ACPI
885 /* Evaluate SSCN and FMCN ACPI methods to fetch timings */
886 if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) {
887 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt,
888 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
889 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt,
890 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
891 }
892 #endif
893
894 if (bootverbose) {
895 device_printf(sc->dev, "Controller parameters:\n");
896 printf(" Speed: %s\n",
897 sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast");
898 printf(" Regs: HCNT :LCNT :SDAHLD\n");
899 printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n",
900 sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt,
901 sc->cfg.ss_sda_hold);
902 printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n",
903 sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt,
904 sc->cfg.fs_sda_hold);
905 }
906 }
907
908 static int
ig4iic_set_config(ig4iic_softc_t * sc,bool reset)909 ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
910 {
911 uint32_t v;
912
913 v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
914 if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
915 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);
916 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
917 pause("i2crst", 1);
918 reset = true;
919 }
920
921 if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) {
922 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
923 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
924 } else if (IG4_HAS_ADDREGS(sc->version) && reset) {
925 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
926 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
927 }
928
929 if (sc->version == IG4_ATOM)
930 v = reg_read(sc, IG4_REG_COMP_TYPE);
931
932 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
933 v = reg_read(sc, IG4_REG_COMP_PARAM1);
934 v = reg_read(sc, IG4_REG_GENERAL);
935 /*
936 * The content of IG4_REG_GENERAL is different for each
937 * controller version.
938 */
939 if (sc->version == IG4_HASWELL &&
940 (v & IG4_GENERAL_SWMODE) == 0) {
941 v |= IG4_GENERAL_SWMODE;
942 reg_write(sc, IG4_REG_GENERAL, v);
943 v = reg_read(sc, IG4_REG_GENERAL);
944 }
945 }
946
947 if (sc->version == IG4_HASWELL) {
948 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
949 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
950 } else if (IG4_HAS_ADDREGS(sc->version)) {
951 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
952 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
953 }
954
955 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
956 v = reg_read(sc, IG4_REG_COMP_VER);
957 if (v < IG4_COMP_MIN_VER)
958 return(ENXIO);
959 }
960
961 if (set_controller(sc, 0)) {
962 device_printf(sc->dev, "controller error during attach-1\n");
963 return (ENXIO);
964 }
965
966 reg_read(sc, IG4_REG_CLR_INTR);
967 reg_write(sc, IG4_REG_INTR_MASK, 0);
968 sc->intr_mask = 0;
969
970 reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);
971 reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);
972 reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);
973 reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);
974 reg_write(sc, IG4_REG_SDA_HOLD,
975 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ?
976 sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold);
977
978 reg_write(sc, IG4_REG_RX_TL, 0);
979 reg_write(sc, IG4_REG_TX_TL, 0);
980
981 reg_write(sc, IG4_REG_CTL,
982 IG4_CTL_MASTER |
983 IG4_CTL_SLAVE_DISABLE |
984 IG4_CTL_RESTARTEN |
985 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK));
986
987 /* Force setting of the target address on the next transfer */
988 sc->slave_valid = false;
989
990 return (0);
991 }
992
993 static void
ig4iic_get_fifo(ig4iic_softc_t * sc)994 ig4iic_get_fifo(ig4iic_softc_t *sc)
995 {
996 uint32_t v;
997
998 /*
999 * Hardware does not allow FIFO Threshold Levels value to be set larger
1000 * than the depth of the buffer. If an attempt is made to do that, the
1001 * actual value set will be the maximum depth of the buffer.
1002 */
1003 if (sc->cfg.txfifo_depth == 0) {
1004 v = reg_read(sc, IG4_REG_TX_TL);
1005 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK);
1006 sc->cfg.txfifo_depth =
1007 (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
1008 reg_write(sc, IG4_REG_TX_TL, v);
1009 }
1010 if (sc->cfg.rxfifo_depth == 0) {
1011 v = reg_read(sc, IG4_REG_RX_TL);
1012 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK);
1013 sc->cfg.rxfifo_depth =
1014 (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
1015 reg_write(sc, IG4_REG_RX_TL, v);
1016 }
1017 if (bootverbose) {
1018 printf(" FIFO: RX:0x%04x: TX:0x%04x\n",
1019 sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth);
1020 }
1021 }
1022
1023 /*
1024 * Called from ig4iic_pci_attach/detach()
1025 */
1026 int
ig4iic_attach(ig4iic_softc_t * sc)1027 ig4iic_attach(ig4iic_softc_t *sc)
1028 {
1029 int error;
1030
1031 mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN);
1032 sx_init(&sc->call_lock, "IG4 call lock");
1033
1034 ig4iic_get_config(sc);
1035
1036 error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
1037 if (error)
1038 goto done;
1039 ig4iic_get_fifo(sc);
1040
1041 sc->iicbus = device_add_child(sc->dev, "iicbus", -1);
1042 if (sc->iicbus == NULL) {
1043 device_printf(sc->dev, "iicbus driver not found\n");
1044 error = ENXIO;
1045 goto done;
1046 }
1047
1048 if (set_controller(sc, IG4_I2C_ENABLE)) {
1049 device_printf(sc->dev, "controller error during attach-2\n");
1050 error = ENXIO;
1051 goto done;
1052 }
1053 if (set_controller(sc, 0)) {
1054 device_printf(sc->dev, "controller error during attach-3\n");
1055 error = ENXIO;
1056 goto done;
1057 }
1058 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
1059 ig4iic_intr, NULL, sc, &sc->intr_handle);
1060 if (error) {
1061 device_printf(sc->dev,
1062 "Unable to setup irq: error %d\n", error);
1063 }
1064
1065 error = bus_generic_attach(sc->dev);
1066 if (error) {
1067 device_printf(sc->dev,
1068 "failed to attach child: error %d\n", error);
1069 }
1070
1071 done:
1072 return (error);
1073 }
1074
1075 int
ig4iic_detach(ig4iic_softc_t * sc)1076 ig4iic_detach(ig4iic_softc_t *sc)
1077 {
1078 int error;
1079
1080 if (device_is_attached(sc->dev)) {
1081 error = bus_generic_detach(sc->dev);
1082 if (error)
1083 return (error);
1084 }
1085 if (sc->iicbus)
1086 device_delete_child(sc->dev, sc->iicbus);
1087 if (sc->intr_handle)
1088 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
1089
1090 sx_xlock(&sc->call_lock);
1091
1092 sc->iicbus = NULL;
1093 sc->intr_handle = NULL;
1094 reg_write(sc, IG4_REG_INTR_MASK, 0);
1095 set_controller(sc, 0);
1096
1097 sx_xunlock(&sc->call_lock);
1098
1099 mtx_destroy(&sc->io_lock);
1100 sx_destroy(&sc->call_lock);
1101
1102 return (0);
1103 }
1104
1105 int
ig4iic_suspend(ig4iic_softc_t * sc)1106 ig4iic_suspend(ig4iic_softc_t *sc)
1107 {
1108 int error;
1109
1110 /* suspend all children */
1111 error = bus_generic_suspend(sc->dev);
1112
1113 sx_xlock(&sc->call_lock);
1114 set_controller(sc, 0);
1115 if (IG4_HAS_ADDREGS(sc->version)) {
1116 /*
1117 * Place the device in the idle state, just to be safe
1118 */
1119 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);
1120 /*
1121 * Controller can become dysfunctional if I2C lines are pulled
1122 * down when suspend procedure turns off power to I2C device.
1123 * Place device in the reset state to avoid this.
1124 */
1125 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
1126 }
1127 sx_xunlock(&sc->call_lock);
1128
1129 return (error);
1130 }
1131
ig4iic_resume(ig4iic_softc_t * sc)1132 int ig4iic_resume(ig4iic_softc_t *sc)
1133 {
1134 int error;
1135
1136 sx_xlock(&sc->call_lock);
1137 if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
1138 device_printf(sc->dev, "controller error during resume\n");
1139 sx_xunlock(&sc->call_lock);
1140
1141 error = bus_generic_resume(sc->dev);
1142
1143 return (error);
1144 }
1145
1146 /*
1147 * Interrupt Operation, see ig4_var.h for locking semantics.
1148 */
1149 static int
ig4iic_intr(void * cookie)1150 ig4iic_intr(void *cookie)
1151 {
1152 ig4iic_softc_t *sc = cookie;
1153 int retval = FILTER_STRAY;
1154
1155 mtx_lock_spin(&sc->io_lock);
1156 /* Ignore stray interrupts */
1157 if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) {
1158 /* Interrupt bits are cleared in wait_intr() loop */
1159 ig4iic_set_intr_mask(sc, 0);
1160 wakeup(sc);
1161 retval = FILTER_HANDLED;
1162 }
1163 mtx_unlock_spin(&sc->io_lock);
1164
1165 return (retval);
1166 }
1167
1168 #define REGDUMP(sc, reg) \
1169 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))
1170
1171 static void
ig4iic_dump(ig4iic_softc_t * sc)1172 ig4iic_dump(ig4iic_softc_t *sc)
1173 {
1174 device_printf(sc->dev, "ig4iic register dump:\n");
1175 REGDUMP(sc, IG4_REG_CTL);
1176 REGDUMP(sc, IG4_REG_TAR_ADD);
1177 REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
1178 REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
1179 REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
1180 REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
1181 REGDUMP(sc, IG4_REG_INTR_STAT);
1182 REGDUMP(sc, IG4_REG_INTR_MASK);
1183 REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
1184 REGDUMP(sc, IG4_REG_RX_TL);
1185 REGDUMP(sc, IG4_REG_TX_TL);
1186 REGDUMP(sc, IG4_REG_I2C_EN);
1187 REGDUMP(sc, IG4_REG_I2C_STA);
1188 REGDUMP(sc, IG4_REG_TXFLR);
1189 REGDUMP(sc, IG4_REG_RXFLR);
1190 REGDUMP(sc, IG4_REG_SDA_HOLD);
1191 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
1192 REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
1193 REGDUMP(sc, IG4_REG_DMA_CTRL);
1194 REGDUMP(sc, IG4_REG_DMA_TDLR);
1195 REGDUMP(sc, IG4_REG_DMA_RDLR);
1196 REGDUMP(sc, IG4_REG_SDA_SETUP);
1197 REGDUMP(sc, IG4_REG_ENABLE_STATUS);
1198 REGDUMP(sc, IG4_REG_COMP_PARAM1);
1199 REGDUMP(sc, IG4_REG_COMP_VER);
1200 if (sc->version == IG4_ATOM) {
1201 REGDUMP(sc, IG4_REG_COMP_TYPE);
1202 REGDUMP(sc, IG4_REG_CLK_PARMS);
1203 }
1204 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
1205 REGDUMP(sc, IG4_REG_RESETS_HSW);
1206 REGDUMP(sc, IG4_REG_GENERAL);
1207 } else if (sc->version == IG4_SKYLAKE) {
1208 REGDUMP(sc, IG4_REG_RESETS_SKL);
1209 }
1210 if (sc->version == IG4_HASWELL) {
1211 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
1212 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
1213 } else if (IG4_HAS_ADDREGS(sc->version)) {
1214 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
1215 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
1216 }
1217 }
1218 #undef REGDUMP
1219
1220 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, NULL, NULL);
1221 #ifdef DEV_ACPI
1222 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, NULL, NULL);
1223 #endif
1224 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
1225 MODULE_VERSION(ig4iic, 1);
1226