1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 *		http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 *		www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include "exynos4.dtsi"
20#include "exynos4-cpu-thermal.dtsi"
21
22/ {
23	compatible = "samsung,exynos4210", "samsung,exynos4";
24
25	aliases {
26		pinctrl0 = &pinctrl_0;
27		pinctrl1 = &pinctrl_1;
28		pinctrl2 = &pinctrl_2;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu0: cpu@900 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a9";
38			reg = <0x900>;
39			clocks = <&clock CLK_ARM_CLK>;
40			clock-names = "cpu";
41			clock-latency = <160000>;
42
43			operating-points = <
44				1200000 1250000
45				1000000 1150000
46				800000	1075000
47				500000	975000
48				400000	975000
49				200000	950000
50			>;
51			#cooling-cells = <2>; /* min followed by max */
52		};
53
54		cpu1: cpu@901 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a9";
57			reg = <0x901>;
58			clocks = <&clock CLK_ARM_CLK>;
59			clock-names = "cpu";
60			clock-latency = <160000>;
61
62			operating-points = <
63				1200000 1250000
64				1000000 1150000
65				800000	1075000
66				500000	975000
67				400000	975000
68				200000	950000
69			>;
70			#cooling-cells = <2>; /* min followed by max */
71		};
72	};
73
74	soc: soc {
75		sysram: sram@2020000 {
76			compatible = "mmio-sram";
77			reg = <0x02020000 0x20000>;
78			#address-cells = <1>;
79			#size-cells = <1>;
80			ranges = <0 0x02020000 0x20000>;
81
82			smp-sram@0 {
83				compatible = "samsung,exynos4210-sysram";
84				reg = <0x0 0x1000>;
85			};
86
87			smp-sram@1f000 {
88				compatible = "samsung,exynos4210-sysram-ns";
89				reg = <0x1f000 0x1000>;
90			};
91		};
92
93		pd_lcd1: power-domain@10023ca0 {
94			compatible = "samsung,exynos4210-pd";
95			reg = <0x10023CA0 0x20>;
96			#power-domain-cells = <0>;
97			label = "LCD1";
98		};
99
100		l2c: cache-controller@10502000 {
101			compatible = "arm,pl310-cache";
102			reg = <0x10502000 0x1000>;
103			cache-unified;
104			cache-level = <2>;
105			arm,tag-latency = <2 2 1>;
106			arm,data-latency = <2 2 1>;
107		};
108
109		mct: timer@10050000 {
110			compatible = "samsung,exynos4210-mct";
111			reg = <0x10050000 0x800>;
112			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
113			clock-names = "fin_pll", "mct";
114			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
115					      <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
116					      <&combiner 12 6>,
117					      <&combiner 12 7>,
118					      <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
119					      <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
120		};
121
122		watchdog: watchdog@10060000 {
123			compatible = "samsung,s3c6410-wdt";
124			reg = <0x10060000 0x100>;
125			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
126			clocks = <&clock CLK_WDT>;
127			clock-names = "watchdog";
128		};
129
130		clock: clock-controller@10030000 {
131			compatible = "samsung,exynos4210-clock";
132			reg = <0x10030000 0x20000>;
133			#clock-cells = <1>;
134		};
135
136		pinctrl_0: pinctrl@11400000 {
137			compatible = "samsung,exynos4210-pinctrl";
138			reg = <0x11400000 0x1000>;
139			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
140		};
141
142		pinctrl_1: pinctrl@11000000 {
143			compatible = "samsung,exynos4210-pinctrl";
144			reg = <0x11000000 0x1000>;
145			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146
147			wakup_eint: wakeup-interrupt-controller {
148				compatible = "samsung,exynos4210-wakeup-eint";
149				interrupt-parent = <&gic>;
150				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
151			};
152		};
153
154		pinctrl_2: pinctrl@3860000 {
155			compatible = "samsung,exynos4210-pinctrl";
156			reg = <0x03860000 0x1000>;
157		};
158
159		g2d: g2d@12800000 {
160			compatible = "samsung,s5pv210-g2d";
161			reg = <0x12800000 0x1000>;
162			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
163			clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
164			clock-names = "sclk_fimg2d", "fimg2d";
165			power-domains = <&pd_lcd0>;
166			iommus = <&sysmmu_g2d>;
167		};
168
169		ppmu_acp: ppmu_acp@10ae0000 {
170			compatible = "samsung,exynos-ppmu";
171			reg = <0x10ae0000 0x2000>;
172			status = "disabled";
173		};
174
175		ppmu_lcd1: ppmu_lcd1@12240000 {
176			compatible = "samsung,exynos-ppmu";
177			reg = <0x12240000 0x2000>;
178			clocks = <&clock CLK_PPMULCD1>;
179			clock-names = "ppmu";
180			status = "disabled";
181		};
182
183		sysmmu_g2d: sysmmu@12a20000 {
184			compatible = "samsung,exynos-sysmmu";
185			reg = <0x12A20000 0x1000>;
186			interrupt-parent = <&combiner>;
187			interrupts = <4 7>;
188			clock-names = "sysmmu", "master";
189			clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
190			power-domains = <&pd_lcd0>;
191			#iommu-cells = <0>;
192		};
193
194		sysmmu_fimd1: sysmmu@12220000 {
195			compatible = "samsung,exynos-sysmmu";
196			interrupt-parent = <&combiner>;
197			reg = <0x12220000 0x1000>;
198			interrupts = <5 3>;
199			clock-names = "sysmmu", "master";
200			clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
201			power-domains = <&pd_lcd1>;
202			#iommu-cells = <0>;
203		};
204
205		bus_dmc: bus_dmc {
206			compatible = "samsung,exynos-bus";
207			clocks = <&clock CLK_DIV_DMC>;
208			clock-names = "bus";
209			operating-points-v2 = <&bus_dmc_opp_table>;
210			status = "disabled";
211		};
212
213		bus_acp: bus_acp {
214			compatible = "samsung,exynos-bus";
215			clocks = <&clock CLK_DIV_ACP>;
216			clock-names = "bus";
217			operating-points-v2 = <&bus_acp_opp_table>;
218			status = "disabled";
219		};
220
221		bus_peri: bus_peri {
222			compatible = "samsung,exynos-bus";
223			clocks = <&clock CLK_ACLK100>;
224			clock-names = "bus";
225			operating-points-v2 = <&bus_peri_opp_table>;
226			status = "disabled";
227		};
228
229		bus_fsys: bus_fsys {
230			compatible = "samsung,exynos-bus";
231			clocks = <&clock CLK_ACLK133>;
232			clock-names = "bus";
233			operating-points-v2 = <&bus_fsys_opp_table>;
234			status = "disabled";
235		};
236
237		bus_display: bus_display {
238			compatible = "samsung,exynos-bus";
239			clocks = <&clock CLK_ACLK160>;
240			clock-names = "bus";
241			operating-points-v2 = <&bus_display_opp_table>;
242			status = "disabled";
243		};
244
245		bus_lcd0: bus_lcd0 {
246			compatible = "samsung,exynos-bus";
247			clocks = <&clock CLK_ACLK200>;
248			clock-names = "bus";
249			operating-points-v2 = <&bus_leftbus_opp_table>;
250			status = "disabled";
251		};
252
253		bus_leftbus: bus_leftbus {
254			compatible = "samsung,exynos-bus";
255			clocks = <&clock CLK_DIV_GDL>;
256			clock-names = "bus";
257			operating-points-v2 = <&bus_leftbus_opp_table>;
258			status = "disabled";
259		};
260
261		bus_rightbus: bus_rightbus {
262			compatible = "samsung,exynos-bus";
263			clocks = <&clock CLK_DIV_GDR>;
264			clock-names = "bus";
265			operating-points-v2 = <&bus_leftbus_opp_table>;
266			status = "disabled";
267		};
268
269		bus_mfc: bus_mfc {
270			compatible = "samsung,exynos-bus";
271			clocks = <&clock CLK_SCLK_MFC>;
272			clock-names = "bus";
273			operating-points-v2 = <&bus_leftbus_opp_table>;
274			status = "disabled";
275		};
276
277		bus_dmc_opp_table: opp_table1 {
278			compatible = "operating-points-v2";
279			opp-shared;
280
281			opp-134000000 {
282				opp-hz = /bits/ 64 <134000000>;
283				opp-microvolt = <1025000>;
284			};
285			opp-267000000 {
286				opp-hz = /bits/ 64 <267000000>;
287				opp-microvolt = <1050000>;
288			};
289			opp-400000000 {
290				opp-hz = /bits/ 64 <400000000>;
291				opp-microvolt = <1150000>;
292				opp-suspend;
293			};
294		};
295
296		bus_acp_opp_table: opp_table2 {
297			compatible = "operating-points-v2";
298			opp-shared;
299
300			opp-134000000 {
301				opp-hz = /bits/ 64 <134000000>;
302			};
303			opp-160000000 {
304				opp-hz = /bits/ 64 <160000000>;
305			};
306			opp-200000000 {
307				opp-hz = /bits/ 64 <200000000>;
308			};
309		};
310
311		bus_peri_opp_table: opp_table3 {
312			compatible = "operating-points-v2";
313			opp-shared;
314
315			opp-5000000 {
316				opp-hz = /bits/ 64 <5000000>;
317			};
318			opp-100000000 {
319				opp-hz = /bits/ 64 <100000000>;
320			};
321		};
322
323		bus_fsys_opp_table: opp_table4 {
324			compatible = "operating-points-v2";
325			opp-shared;
326
327			opp-10000000 {
328				opp-hz = /bits/ 64 <10000000>;
329			};
330			opp-134000000 {
331				opp-hz = /bits/ 64 <134000000>;
332			};
333		};
334
335		bus_display_opp_table: opp_table5 {
336			compatible = "operating-points-v2";
337			opp-shared;
338
339			opp-100000000 {
340				opp-hz = /bits/ 64 <100000000>;
341			};
342			opp-134000000 {
343				opp-hz = /bits/ 64 <134000000>;
344			};
345			opp-160000000 {
346				opp-hz = /bits/ 64 <160000000>;
347			};
348		};
349
350		bus_leftbus_opp_table: opp_table6 {
351			compatible = "operating-points-v2";
352			opp-shared;
353
354			opp-100000000 {
355				opp-hz = /bits/ 64 <100000000>;
356			};
357			opp-160000000 {
358				opp-hz = /bits/ 64 <160000000>;
359			};
360			opp-200000000 {
361				opp-hz = /bits/ 64 <200000000>;
362				opp-suspend;
363			};
364		};
365	};
366
367	thermal-zones {
368		cpu_thermal: cpu-thermal {
369			polling-delay-passive = <0>;
370			polling-delay = <0>;
371			thermal-sensors = <&tmu 0>;
372
373			trips {
374				cpu_alert0: cpu-alert-0 {
375					temperature = <85000>; /* millicelsius */
376				};
377				cpu_alert1: cpu-alert-1 {
378					temperature = <100000>; /* millicelsius */
379				};
380				cpu_alert2: cpu-alert-2 {
381					temperature = <110000>; /* millicelsius */
382				};
383			};
384		};
385	};
386};
387
388&gic {
389	cpu-offset = <0x8000>;
390};
391
392&camera {
393	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
394		 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
395	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
396};
397
398&combiner {
399	samsung,combiner-nr = <16>;
400	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
402		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
403		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
404		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
405		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
406		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
407		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
408		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
409		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
410		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
411		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
412		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
413		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
414		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
415		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
416};
417
418&fimc_0 {
419	samsung,pix-limits = <4224 8192 1920 4224>;
420	samsung,mainscaler-ext;
421	samsung,cam-if;
422};
423
424&fimc_1 {
425	samsung,pix-limits = <4224 8192 1920 4224>;
426	samsung,mainscaler-ext;
427	samsung,cam-if;
428};
429
430&fimc_2 {
431	samsung,pix-limits = <4224 8192 1920 4224>;
432	samsung,mainscaler-ext;
433	samsung,lcd-wb;
434};
435
436&fimc_3 {
437	samsung,pix-limits = <1920 8192 1366 1920>;
438	samsung,rotators = <0>;
439	samsung,mainscaler-ext;
440	samsung,lcd-wb;
441};
442
443&gpu {
444	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
445		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
446		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
447		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
448		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
449		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
450		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
451		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
452		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
453		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
454	interrupt-names = "gp",
455			  "gpmmu",
456			  "pp0",
457			  "ppmmu0",
458			  "pp1",
459			  "ppmmu1",
460			  "pp2",
461			  "ppmmu2",
462			  "pp3",
463			  "ppmmu3";
464	operating-points-v2 = <&gpu_opp_table>;
465
466	gpu_opp_table: opp_table {
467		compatible = "operating-points-v2";
468
469		opp-160000000 {
470			opp-hz = /bits/ 64 <160000000>;
471			opp-microvolt = <950000>;
472		};
473		opp-267000000 {
474			opp-hz = /bits/ 64 <267000000>;
475			opp-microvolt = <1050000>;
476		};
477	};
478};
479
480&mdma1 {
481	power-domains = <&pd_lcd0>;
482};
483
484&mixer {
485	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
486		      "sclk_mixer";
487	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
488		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
489		 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
490};
491
492&pmu {
493	interrupts = <2 2>, <3 2>;
494	interrupt-affinity = <&cpu0>, <&cpu1>;
495	status = "okay";
496};
497
498&pmu_system_controller {
499	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
500			"clkout4", "clkout8", "clkout9";
501	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
502		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
503		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
504	#clock-cells = <1>;
505};
506
507&rotator {
508	power-domains = <&pd_lcd0>;
509};
510
511&sysmmu_rotator {
512	power-domains = <&pd_lcd0>;
513};
514
515&tmu {
516	compatible = "samsung,exynos4210-tmu";
517	clocks = <&clock CLK_TMU_APBIF>;
518	clock-names = "tmu_apbif";
519	samsung,tmu_gain = <15>;
520	samsung,tmu_reference_voltage = <7>;
521};
522
523#include "exynos4210-pinctrl.dtsi"
524