1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2000-2004 Taku YAMAMOTO <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
29 */
30
31 /*
32 * Credits:
33 *
34 * Part of this code (especially in many magic numbers) was heavily inspired
35 * by the Linux driver originally written by
36 * Alan Cox <[email protected]>, modified heavily by
37 * Zach Brown <[email protected]>.
38 *
39 * busdma()-ize and buffer size reduction were suggested by
40 * Cameron Grant <[email protected]>.
41 * Also he showed me the way to use busdma() suite.
42 *
43 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
44 * were looked at by
45 * Munehiro Matsuda <[email protected]>,
46 * who brought patches based on the Linux driver with some simplification.
47 *
48 * Hardware volume controller was implemented by
49 * John Baldwin <[email protected]>.
50 */
51
52 #ifdef HAVE_KERNEL_OPTION_HEADERS
53 #include "opt_snd.h"
54 #endif
55
56 #include <dev/sound/pcm/sound.h>
57 #include <dev/sound/pcm/ac97.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
60
61 #include <dev/sound/pci/maestro_reg.h>
62
63 SND_DECLARE_FILE("$FreeBSD$");
64
65 /*
66 * PCI IDs of supported chips:
67 *
68 * MAESTRO-1 0x01001285
69 * MAESTRO-2 0x1968125d
70 * MAESTRO-2E 0x1978125d
71 */
72
73 #define MAESTRO_1_PCI_ID 0x01001285
74 #define MAESTRO_2_PCI_ID 0x1968125d
75 #define MAESTRO_2E_PCI_ID 0x1978125d
76
77 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
78 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
79
80 #ifdef AGG_MAXPLAYCH
81 # if AGG_MAXPLAYCH > 4
82 # undef AGG_MAXPLAYCH
83 # define AGG_MAXPLAYCH 4
84 # endif
85 #else
86 # define AGG_MAXPLAYCH 4
87 #endif
88
89 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
90
91 #ifndef PCIR_BAR
92 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
93 #endif
94
95 /* -----------------------------
96 * Data structures.
97 */
98 struct agg_chinfo {
99 /* parent softc */
100 struct agg_info *parent;
101
102 /* FreeBSD newpcm related */
103 struct pcm_channel *channel;
104 struct snd_dbuf *buffer;
105
106 /* OS independent */
107 bus_dmamap_t map;
108 bus_addr_t phys; /* channel buffer physical address */
109 bus_addr_t base; /* channel buffer segment base */
110 u_int32_t blklen; /* DMA block length in WORDs */
111 u_int32_t buflen; /* channel buffer length in WORDs */
112 u_int32_t speed;
113 unsigned num : 3;
114 unsigned stereo : 1;
115 unsigned qs16 : 1; /* quantum size is 16bit */
116 unsigned us : 1; /* in unsigned format */
117 };
118
119 struct agg_rchinfo {
120 /* parent softc */
121 struct agg_info *parent;
122
123 /* FreeBSD newpcm related */
124 struct pcm_channel *channel;
125 struct snd_dbuf *buffer;
126
127 /* OS independent */
128 bus_dmamap_t map;
129 bus_addr_t phys; /* channel buffer physical address */
130 bus_addr_t base; /* channel buffer segment base */
131 u_int32_t blklen; /* DMA block length in WORDs */
132 u_int32_t buflen; /* channel buffer length in WORDs */
133 u_int32_t speed;
134 unsigned : 3;
135 unsigned stereo : 1;
136 bus_addr_t srcphys;
137 int16_t *src; /* stereo peer buffer */
138 int16_t *sink; /* channel buffer pointer */
139 volatile u_int32_t hwptr; /* ready point in 16bit sample */
140 };
141
142 struct agg_info {
143 /* FreeBSD newbus related */
144 device_t dev;
145
146 /* I wonder whether bus_space_* are in common in *BSD... */
147 struct resource *reg;
148 int regid;
149 bus_space_tag_t st;
150 bus_space_handle_t sh;
151
152 struct resource *irq;
153 int irqid;
154 void *ih;
155
156 bus_dma_tag_t buf_dmat;
157 bus_dma_tag_t stat_dmat;
158
159 /* FreeBSD SMPng related */
160 struct mtx lock; /* mutual exclusion */
161 /* FreeBSD newpcm related */
162 struct ac97_info *codec;
163
164 /* OS independent */
165 bus_dmamap_t stat_map;
166 u_int8_t *stat; /* status buffer pointer */
167 bus_addr_t phys; /* status buffer physical address */
168 unsigned int bufsz; /* channel buffer size in bytes */
169 u_int playchns;
170 volatile u_int active;
171 struct agg_chinfo pch[AGG_MAXPLAYCH];
172 struct agg_rchinfo rch;
173 volatile u_int8_t curpwr; /* current power status: D[0-3] */
174 };
175
176 /* -----------------------------
177 * Sysctls for debug.
178 */
179 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
180 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
181 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
182 #else
183 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
184 #endif
185 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
186
187 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
188 device_get_sysctl_*() as discussed on multimedia@ in msg-id
189 <[email protected]> */
190 static SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
191 "");
192 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
193 &powerstate_active, 0, "The Dx power state when active (0-1)");
194 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
195 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
196 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
197 &powerstate_init, 0,
198 "The Dx power state prior to the first use (0-2)");
199
200 /* -----------------------------
201 * Prototypes
202 */
203
204 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
205
206 #if 0
207 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
208 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
209 int size);
210 #endif
211 static int agg_rdcodec(struct agg_info*, int);
212 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
213
214 static void ringbus_setdest(struct agg_info*, int, int);
215
216 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
217 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
218 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
219 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
220 static void wp_settimer(struct agg_info*, u_int);
221 static void wp_starttimer(struct agg_info*);
222 static void wp_stoptimer(struct agg_info*);
223
224 #if 0
225 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
226 #endif
227 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
228 #if 0
229 static u_int16_t wc_rdchctl(struct agg_info*, int);
230 #endif
231 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
232
233 static void agg_stopclock(struct agg_info*, int part, int st);
234
235 static void agg_initcodec(struct agg_info*);
236 static void agg_init(struct agg_info*);
237 static void agg_power(struct agg_info*, int);
238
239 static void aggch_start_dac(struct agg_chinfo*);
240 static void aggch_stop_dac(struct agg_chinfo*);
241 static void aggch_start_adc(struct agg_rchinfo*);
242 static void aggch_stop_adc(struct agg_rchinfo*);
243 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
244 static void aggch_feed_adc_mono(struct agg_rchinfo*);
245
246 #ifdef AGG_JITTER_CORRECTION
247 static void suppress_jitter(struct agg_chinfo*);
248 static void suppress_rec_jitter(struct agg_rchinfo*);
249 #endif
250
251 static void set_timer(struct agg_info*);
252
253 static void agg_intr(void *);
254 static int agg_probe(device_t);
255 static int agg_attach(device_t);
256 static int agg_detach(device_t);
257 static int agg_suspend(device_t);
258 static int agg_resume(device_t);
259 static int agg_shutdown(device_t);
260
261 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*,
262 bus_dmamap_t *);
263 static void dma_free(bus_dma_tag_t, void *, bus_dmamap_t);
264
265 /* -----------------------------
266 * Subsystems.
267 */
268
269 /* locking */
270 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
271 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
272
273 static void
agg_sleep(struct agg_info * sc,const char * wmesg,int msec)274 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
275 {
276 int timo;
277
278 timo = msec * hz / 1000;
279 if (timo == 0)
280 timo = 1;
281 msleep(sc, &sc->lock, PWAIT, wmesg, timo);
282 }
283
284 /* I/O port */
285
286 #if 0
287 static __inline u_int32_t
288 agg_rd(struct agg_info *sc, int regno, int size)
289 {
290 switch (size) {
291 case 1:
292 return bus_space_read_1(sc->st, sc->sh, regno);
293 case 2:
294 return bus_space_read_2(sc->st, sc->sh, regno);
295 case 4:
296 return bus_space_read_4(sc->st, sc->sh, regno);
297 default:
298 return ~(u_int32_t)0;
299 }
300 }
301 #endif
302
303 #define AGG_RD(sc, regno, size) \
304 bus_space_read_##size( \
305 ((struct agg_info*)(sc))->st, \
306 ((struct agg_info*)(sc))->sh, (regno))
307
308 #if 0
309 static __inline void
310 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
311 {
312 switch (size) {
313 case 1:
314 bus_space_write_1(sc->st, sc->sh, regno, data);
315 break;
316 case 2:
317 bus_space_write_2(sc->st, sc->sh, regno, data);
318 break;
319 case 4:
320 bus_space_write_4(sc->st, sc->sh, regno, data);
321 break;
322 }
323 }
324 #endif
325
326 #define AGG_WR(sc, regno, data, size) \
327 bus_space_write_##size( \
328 ((struct agg_info*)(sc))->st, \
329 ((struct agg_info*)(sc))->sh, (regno), (data))
330
331 /* -------------------------------------------------------------------- */
332
333 /* Codec/Ringbus */
334
335 static int
agg_codec_wait4idle(struct agg_info * ess)336 agg_codec_wait4idle(struct agg_info *ess)
337 {
338 unsigned t = 26;
339
340 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
341 if (--t == 0)
342 return EBUSY;
343 DELAY(2); /* 20.8us / 13 */
344 }
345 return 0;
346 }
347
348 static int
agg_rdcodec(struct agg_info * ess,int regno)349 agg_rdcodec(struct agg_info *ess, int regno)
350 {
351 int ret;
352
353 /* We have to wait for a SAFE time to write addr/data */
354 if (agg_codec_wait4idle(ess)) {
355 /* Timed out. No read performed. */
356 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
357 return -1;
358 }
359
360 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
361 /*DELAY(21); * AC97 cycle = 20.8usec */
362
363 /* Wait for data retrieve */
364 if (!agg_codec_wait4idle(ess)) {
365 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
366 } else {
367 /* Timed out. No read performed. */
368 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
369 ret = -1;
370 }
371
372 return ret;
373 }
374
375 static int
agg_wrcodec(struct agg_info * ess,int regno,u_int32_t data)376 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
377 {
378 /* We have to wait for a SAFE time to write addr/data */
379 if (agg_codec_wait4idle(ess)) {
380 /* Timed out. Abort writing. */
381 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
382 return -1;
383 }
384
385 AGG_WR(ess, PORT_CODEC_REG, data, 2);
386 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
387
388 /* Wait for write completion */
389 if (agg_codec_wait4idle(ess)) {
390 /* Timed out. */
391 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
392 return -1;
393 }
394
395 return 0;
396 }
397
398 static void
ringbus_setdest(struct agg_info * ess,int src,int dest)399 ringbus_setdest(struct agg_info *ess, int src, int dest)
400 {
401 u_int32_t data;
402
403 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
404 data &= ~(0xfU << src);
405 data |= (0xfU & dest) << src;
406 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
407 }
408
409 /* -------------------------------------------------------------------- */
410
411 /* Wave Processor */
412
413 static u_int16_t
wp_rdreg(struct agg_info * ess,u_int16_t reg)414 wp_rdreg(struct agg_info *ess, u_int16_t reg)
415 {
416 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
417 return AGG_RD(ess, PORT_DSP_DATA, 2);
418 }
419
420 static void
wp_wrreg(struct agg_info * ess,u_int16_t reg,u_int16_t data)421 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
422 {
423 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
424 AGG_WR(ess, PORT_DSP_DATA, data, 2);
425 }
426
427 static int
wp_wait_data(struct agg_info * ess,u_int16_t data)428 wp_wait_data(struct agg_info *ess, u_int16_t data)
429 {
430 unsigned t = 0;
431
432 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
433 if (++t == 1000) {
434 return EAGAIN;
435 }
436 AGG_WR(ess, PORT_DSP_DATA, data, 2);
437 }
438
439 return 0;
440 }
441
442 static u_int16_t
wp_rdapu(struct agg_info * ess,unsigned ch,u_int16_t reg)443 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
444 {
445 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
446 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
447 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
448 return wp_rdreg(ess, WPREG_DATA_PORT);
449 }
450
451 static void
wp_wrapu(struct agg_info * ess,unsigned ch,u_int16_t reg,u_int16_t data)452 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
453 {
454 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
455 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
456 wp_wrreg(ess, WPREG_DATA_PORT, data);
457 if (wp_wait_data(ess, data) != 0)
458 device_printf(ess->dev,
459 "wp_wrapu() write timed out.\n");
460 } else {
461 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
462 }
463 }
464
465 static void
apu_setparam(struct agg_info * ess,int apuch,u_int32_t wpwa,u_int16_t size,int16_t pan,u_int dv)466 apu_setparam(struct agg_info *ess, int apuch,
467 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
468 {
469 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
470 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
471 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
472 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
473 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
474 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
475 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
476 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
477 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
478 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
479 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
480 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
481 }
482
483 static void
wp_settimer(struct agg_info * ess,u_int divide)484 wp_settimer(struct agg_info *ess, u_int divide)
485 {
486 u_int prescale = 0;
487
488 RANGE(divide, 2, 32 << 7);
489
490 for (; divide > 32; divide >>= 1) {
491 prescale++;
492 divide++;
493 }
494
495 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
496 prescale++;
497
498 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
499 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
500 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
501 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
502 }
503
504 static void
wp_starttimer(struct agg_info * ess)505 wp_starttimer(struct agg_info *ess)
506 {
507 AGG_WR(ess, PORT_INT_STAT, 1, 2);
508 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
509 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
510 wp_wrreg(ess, WPREG_TIMER_START, 1);
511 }
512
513 static void
wp_stoptimer(struct agg_info * ess)514 wp_stoptimer(struct agg_info *ess)
515 {
516 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
517 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
518 AGG_WR(ess, PORT_INT_STAT, 1, 2);
519 wp_wrreg(ess, WPREG_TIMER_START, 0);
520 }
521
522 /* -------------------------------------------------------------------- */
523
524 /* WaveCache */
525
526 #if 0
527 static u_int16_t
528 wc_rdreg(struct agg_info *ess, u_int16_t reg)
529 {
530 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
531 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
532 }
533 #endif
534
535 static void
wc_wrreg(struct agg_info * ess,u_int16_t reg,u_int16_t data)536 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
537 {
538 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
539 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
540 }
541
542 #if 0
543 static u_int16_t
544 wc_rdchctl(struct agg_info *ess, int ch)
545 {
546 return wc_rdreg(ess, ch << 3);
547 }
548 #endif
549
550 static void
wc_wrchctl(struct agg_info * ess,int ch,u_int16_t data)551 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
552 {
553 wc_wrreg(ess, ch << 3, data);
554 }
555
556 /* -------------------------------------------------------------------- */
557
558 /* Power management */
559 static void
agg_stopclock(struct agg_info * ess,int part,int st)560 agg_stopclock(struct agg_info *ess, int part, int st)
561 {
562 u_int32_t data;
563
564 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
565 if (part < 16) {
566 if (st == PCI_POWERSTATE_D1)
567 data &= ~(1 << part);
568 else
569 data |= (1 << part);
570 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
571 data |= (0x10000 << part);
572 else
573 data &= ~(0x10000 << part);
574 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
575 }
576 }
577
578 /* -----------------------------
579 * Controller.
580 */
581
582 static void
agg_initcodec(struct agg_info * ess)583 agg_initcodec(struct agg_info* ess)
584 {
585 u_int16_t data;
586
587 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
588 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
589 DELAY(104); /* 20.8us * (4 + 1) */
590 }
591 /* XXX - 2nd codec should be looked at. */
592 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
593 DELAY(2);
594 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
595 DELAY(50);
596
597 if (agg_rdcodec(ess, 0) < 0) {
598 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
599 DELAY(21);
600
601 /* Try cold reset. */
602 device_printf(ess->dev, "will perform cold reset.\n");
603 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
604 if (pci_read_config(ess->dev, 0x58, 2) & 1)
605 data |= 0x10;
606 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
607 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
608 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
609 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
610 DELAY(2);
611 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
612 DELAY(1);
613 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
614 agg_sleep(ess, "agginicd", 500);
615 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
616 DELAY(84); /* 20.8us * 4 */
617 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
618 DELAY(50);
619 }
620 }
621
622 static void
agg_init(struct agg_info * ess)623 agg_init(struct agg_info* ess)
624 {
625 u_int32_t data;
626
627 /* Setup PCI config registers. */
628
629 /* Disable all legacy emulations. */
630 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
631 data |= LEGACY_DISABLED;
632 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
633
634 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
635 * Enable posted write.
636 * Prefer PCI timing rather than that of ISA.
637 * Don't swap L/R. */
638 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
639 data |= MAESTRO_PMC;
640 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
641 data &= ~MAESTRO_SWAP_LR;
642 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
643
644 /* Turn off unused parts if necessary. */
645 /* consult CONF_MAESTRO. */
646 if (data & MAESTRO_SPDIF)
647 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
648 else
649 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
650 if (data & MAESTRO_HWVOL)
651 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
652 else
653 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
654
655 /* parts that never be used */
656 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
657 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
658 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
659 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
660 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
661 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
662 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
663
664 /* parts that will be used only when play/recording */
665 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
666
667 /* parts that should always be turned on */
668 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
669 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
670 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
671 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
672
673 /* Reset direct sound. */
674 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
675 DELAY(100);
676 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
677 DELAY(100);
678 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
679 DELAY(100);
680 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
681 DELAY(100);
682
683 /* Enable hardware volume control interruption. */
684 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
685 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
686
687 /* Setup Wave Processor. */
688
689 /* Enable WaveCache, set DMA base address. */
690 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
691 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
692 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
693
694 AGG_WR(ess, PORT_WAVCACHE_CTRL,
695 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
696
697 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
698 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
699
700 /* Setup Codec/Ringbus. */
701 agg_initcodec(ess);
702 AGG_WR(ess, PORT_RINGBUS_CTRL,
703 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
704
705 wp_wrreg(ess, 0x08, 0xB004);
706 wp_wrreg(ess, 0x09, 0x001B);
707 wp_wrreg(ess, 0x0A, 0x8000);
708 wp_wrreg(ess, 0x0B, 0x3F37);
709 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
710 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
711 ringbus_setdest(ess, RINGBUS_SRC_ADC,
712 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
713 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
714 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
715
716 /* Enable S/PDIF if necessary. */
717 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
718 /* XXX - why not use device flags? */
719 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
720 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
721
722 /* Setup ASSP. Needed for Dell Inspiron 7500? */
723 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
724 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
725 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
726
727 /*
728 * Setup GPIO.
729 * There seems to be speciality with NEC systems.
730 */
731 switch (pci_get_subvendor(ess->dev)
732 | (pci_get_subdevice(ess->dev) << 16)) {
733 case NEC_SUBID1:
734 case NEC_SUBID2:
735 /* Matthew Braithwaite <[email protected]> reported that
736 * NEC Versa LX doesn't need GPIO operation. */
737 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
738 AGG_WR(ess, PORT_GPIO_DIR,
739 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
740 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
741 break;
742 }
743 }
744
745 /* Deals power state transition. Must be called with softc->lock held. */
746 static void
agg_power(struct agg_info * ess,int status)747 agg_power(struct agg_info *ess, int status)
748 {
749 u_int8_t lastpwr;
750
751 lastpwr = ess->curpwr;
752 if (lastpwr == status)
753 return;
754
755 switch (status) {
756 case PCI_POWERSTATE_D0:
757 case PCI_POWERSTATE_D1:
758 switch (lastpwr) {
759 case PCI_POWERSTATE_D2:
760 pci_set_powerstate(ess->dev, status);
761 /* Turn on PCM-related parts. */
762 agg_wrcodec(ess, AC97_REG_POWER, 0);
763 DELAY(100);
764 #if 0
765 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
766 device_printf(ess->dev,
767 "warning: codec not ready.\n");
768 #endif
769 AGG_WR(ess, PORT_RINGBUS_CTRL,
770 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
771 & ~RINGBUS_CTRL_ACLINK_ENABLED)
772 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
773 DELAY(50);
774 AGG_WR(ess, PORT_RINGBUS_CTRL,
775 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
776 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
777 break;
778 case PCI_POWERSTATE_D3:
779 /* Initialize. */
780 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
781 DELAY(100);
782 agg_init(ess);
783 /* FALLTHROUGH */
784 case PCI_POWERSTATE_D0:
785 case PCI_POWERSTATE_D1:
786 pci_set_powerstate(ess->dev, status);
787 break;
788 }
789 break;
790 case PCI_POWERSTATE_D2:
791 switch (lastpwr) {
792 case PCI_POWERSTATE_D3:
793 /* Initialize. */
794 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
795 DELAY(100);
796 agg_init(ess);
797 /* FALLTHROUGH */
798 case PCI_POWERSTATE_D0:
799 case PCI_POWERSTATE_D1:
800 /* Turn off PCM-related parts. */
801 AGG_WR(ess, PORT_RINGBUS_CTRL,
802 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
803 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
804 DELAY(100);
805 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
806 DELAY(100);
807 break;
808 }
809 pci_set_powerstate(ess->dev, status);
810 break;
811 case PCI_POWERSTATE_D3:
812 /* Entirely power down. */
813 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
814 DELAY(100);
815 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
816 /*DELAY(1);*/
817 if (lastpwr != PCI_POWERSTATE_D2)
818 wp_stoptimer(ess);
819 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
820 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
821 pci_set_powerstate(ess->dev, status);
822 break;
823 default:
824 /* Invalid power state; let it ignored. */
825 status = lastpwr;
826 break;
827 }
828
829 ess->curpwr = status;
830 }
831
832 /* -------------------------------------------------------------------- */
833
834 /* Channel controller. */
835
836 static void
aggch_start_dac(struct agg_chinfo * ch)837 aggch_start_dac(struct agg_chinfo *ch)
838 {
839 bus_addr_t wpwa;
840 u_int32_t speed;
841 u_int16_t size, apuch, wtbar, wcreg, aputype;
842 u_int dv;
843 int pan;
844
845 speed = ch->speed;
846 wpwa = (ch->phys - ch->base) >> 1;
847 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
848 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
849 size = ch->buflen;
850 apuch = (ch->num << 1) | 32;
851 pan = PAN_RIGHT - PAN_FRONT;
852
853 if (ch->stereo) {
854 wcreg |= WAVCACHE_CHCTL_STEREO;
855 if (ch->qs16) {
856 aputype = APUTYPE_16BITSTEREO;
857 wpwa >>= 1;
858 size >>= 1;
859 pan = -pan;
860 } else
861 aputype = APUTYPE_8BITSTEREO;
862 } else {
863 pan = 0;
864 if (ch->qs16)
865 aputype = APUTYPE_16BITLINEAR;
866 else {
867 aputype = APUTYPE_8BITLINEAR;
868 speed >>= 1;
869 }
870 }
871 if (ch->us)
872 wcreg |= WAVCACHE_CHCTL_U8;
873
874 if (wtbar > 8)
875 wtbar = (wtbar >> 1) + 4;
876
877 dv = (((speed % 48000) << 16) + 24000) / 48000
878 + ((speed / 48000) << 16);
879
880 agg_lock(ch->parent);
881 agg_power(ch->parent, powerstate_active);
882
883 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
884 ch->base >> WAVCACHE_BASEADDR_SHIFT);
885 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
886 ch->base >> WAVCACHE_BASEADDR_SHIFT);
887 if (wtbar < 8) {
888 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
889 ch->base >> WAVCACHE_BASEADDR_SHIFT);
890 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
891 ch->base >> WAVCACHE_BASEADDR_SHIFT);
892 }
893 wc_wrchctl(ch->parent, apuch, wcreg);
894 wc_wrchctl(ch->parent, apuch + 1, wcreg);
895
896 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
897 if (ch->stereo) {
898 if (ch->qs16)
899 wpwa |= (WPWA_STEREO >> 1);
900 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
901
902 critical_enter();
903 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
904 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
905 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
906 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
907 critical_exit();
908 } else {
909 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
910 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
911 }
912
913 /* to mark that this channel is ready for intr. */
914 ch->parent->active |= (1 << ch->num);
915
916 set_timer(ch->parent);
917 wp_starttimer(ch->parent);
918 agg_unlock(ch->parent);
919 }
920
921 static void
aggch_stop_dac(struct agg_chinfo * ch)922 aggch_stop_dac(struct agg_chinfo *ch)
923 {
924 agg_lock(ch->parent);
925
926 /* to mark that this channel no longer needs further intrs. */
927 ch->parent->active &= ~(1 << ch->num);
928
929 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
930 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
931 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
932 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
933
934 if (ch->parent->active) {
935 set_timer(ch->parent);
936 wp_starttimer(ch->parent);
937 } else {
938 wp_stoptimer(ch->parent);
939 agg_power(ch->parent, powerstate_idle);
940 }
941 agg_unlock(ch->parent);
942 }
943
944 static void
aggch_start_adc(struct agg_rchinfo * ch)945 aggch_start_adc(struct agg_rchinfo *ch)
946 {
947 bus_addr_t wpwa, wpwa2;
948 u_int16_t wcreg, wcreg2;
949 u_int dv;
950 int pan;
951
952 /* speed > 48000 not cared */
953 dv = ((ch->speed << 16) + 24000) / 48000;
954
955 /* RATECONV doesn't seem to like dv == 0x10000. */
956 if (dv == 0x10000)
957 dv--;
958
959 if (ch->stereo) {
960 wpwa = (ch->srcphys - ch->base) >> 1;
961 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
962 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
963 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
964 pan = PAN_LEFT - PAN_FRONT;
965 } else {
966 wpwa = (ch->phys - ch->base) >> 1;
967 wpwa2 = (ch->srcphys - ch->base) >> 1;
968 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
969 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
970 pan = 0;
971 }
972
973 agg_lock(ch->parent);
974
975 ch->hwptr = 0;
976 agg_power(ch->parent, powerstate_active);
977
978 /* Invalidate WaveCache. */
979 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
980 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
981 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
982 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
983
984 /* Load APU registers. */
985 /* APU #0 : Sample rate converter for left/center. */
986 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
987 ch->buflen >> ch->stereo, 0, dv);
988 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
989 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
990
991 /* APU #1 : Sample rate converter for right. */
992 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
993 ch->buflen >> ch->stereo, 0, dv);
994 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
995 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
996
997 /* APU #2 : Input mixer for left. */
998 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
999 ch->parent->bufsz >> 2, pan, 0x10000);
1000 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1001 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1002 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1003
1004 /* APU #3 : Input mixer for right. */
1005 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1006 ch->parent->bufsz >> 2, -pan, 0x10000);
1007 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1008 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1009 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1010
1011 /* to mark this channel ready for intr. */
1012 ch->parent->active |= (1 << ch->parent->playchns);
1013
1014 /* start adc */
1015 critical_enter();
1016 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1017 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1018 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1019 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1020 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1021 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1022 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1023 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1024 critical_exit();
1025
1026 set_timer(ch->parent);
1027 wp_starttimer(ch->parent);
1028 agg_unlock(ch->parent);
1029 }
1030
1031 static void
aggch_stop_adc(struct agg_rchinfo * ch)1032 aggch_stop_adc(struct agg_rchinfo *ch)
1033 {
1034 int apuch;
1035
1036 agg_lock(ch->parent);
1037
1038 /* to mark that this channel no longer needs further intrs. */
1039 ch->parent->active &= ~(1 << ch->parent->playchns);
1040
1041 for (apuch = 0; apuch < 4; apuch++)
1042 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1043 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1044
1045 if (ch->parent->active) {
1046 set_timer(ch->parent);
1047 wp_starttimer(ch->parent);
1048 } else {
1049 wp_stoptimer(ch->parent);
1050 agg_power(ch->parent, powerstate_idle);
1051 }
1052 agg_unlock(ch->parent);
1053 }
1054
1055 /*
1056 * Feed from L/R channel of ADC to destination with stereo interleaving.
1057 * This function expects n not overwrapping the buffer boundary.
1058 * Note that n is measured in sample unit.
1059 *
1060 * XXX - this function works in 16bit stereo format only.
1061 */
1062 static void
interleave(int16_t * l,int16_t * r,int16_t * p,unsigned n)1063 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1064 {
1065 int16_t *end;
1066
1067 for (end = l + n; l < end; ) {
1068 *p++ = *l++;
1069 *p++ = *r++;
1070 }
1071 }
1072
1073 static void
aggch_feed_adc_stereo(struct agg_rchinfo * ch)1074 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1075 {
1076 unsigned cur, last;
1077 int16_t *src2;
1078
1079 agg_lock(ch->parent);
1080 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1081 agg_unlock(ch->parent);
1082 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1083 last = ch->hwptr;
1084 src2 = ch->src + ch->parent->bufsz/4;
1085
1086 if (cur < last) {
1087 interleave(ch->src + last, src2 + last,
1088 ch->sink + 2*last, ch->buflen/2 - last);
1089 interleave(ch->src, src2,
1090 ch->sink, cur);
1091 } else if (cur > last)
1092 interleave(ch->src + last, src2 + last,
1093 ch->sink + 2*last, cur - last);
1094 ch->hwptr = cur;
1095 }
1096
1097 /*
1098 * Feed from R channel of ADC and mixdown to destination L/center.
1099 * This function expects n not overwrapping the buffer boundary.
1100 * Note that n is measured in sample unit.
1101 *
1102 * XXX - this function works in 16bit monoral format only.
1103 */
1104 static void
mixdown(int16_t * src,int16_t * dest,unsigned n)1105 mixdown(int16_t *src, int16_t *dest, unsigned n)
1106 {
1107 int16_t *end;
1108
1109 for (end = dest + n; dest < end; dest++)
1110 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1111 }
1112
1113 static void
aggch_feed_adc_mono(struct agg_rchinfo * ch)1114 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1115 {
1116 unsigned cur, last;
1117
1118 agg_lock(ch->parent);
1119 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1120 agg_unlock(ch->parent);
1121 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1122 last = ch->hwptr;
1123
1124 if (cur < last) {
1125 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1126 mixdown(ch->src, ch->sink, cur);
1127 } else if (cur > last)
1128 mixdown(ch->src + last, ch->sink + last, cur - last);
1129 ch->hwptr = cur;
1130 }
1131
1132 #ifdef AGG_JITTER_CORRECTION
1133 /*
1134 * Stereo jitter suppressor.
1135 * Sometimes playback pointers differ in stereo-paired channels.
1136 * Calling this routine within intr fixes the problem.
1137 */
1138 static void
suppress_jitter(struct agg_chinfo * ch)1139 suppress_jitter(struct agg_chinfo *ch)
1140 {
1141 if (ch->stereo) {
1142 int cp1, cp2, diff /*, halfsize*/ ;
1143
1144 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1145 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1146 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1147 if (cp1 != cp2) {
1148 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1149 if (diff > 1 /* && diff < halfsize*/ )
1150 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1151 }
1152 }
1153 }
1154
1155 static void
suppress_rec_jitter(struct agg_rchinfo * ch)1156 suppress_rec_jitter(struct agg_rchinfo *ch)
1157 {
1158 int cp1, cp2, diff /*, halfsize*/ ;
1159
1160 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1161 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1162 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1163 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1164 if (cp1 != cp2) {
1165 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1166 if (diff > 1 /* && diff < halfsize*/ )
1167 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1168 }
1169 }
1170 #endif
1171
1172 static u_int
calc_timer_div(struct agg_chinfo * ch)1173 calc_timer_div(struct agg_chinfo *ch)
1174 {
1175 u_int speed;
1176
1177 speed = ch->speed;
1178 #ifdef INVARIANTS
1179 if (speed == 0) {
1180 printf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1181 ch->num);
1182 speed = 1;
1183 }
1184 #endif
1185 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1186 + speed - 1) / speed;
1187 }
1188
1189 static u_int
calc_timer_div_rch(struct agg_rchinfo * ch)1190 calc_timer_div_rch(struct agg_rchinfo *ch)
1191 {
1192 u_int speed;
1193
1194 speed = ch->speed;
1195 #ifdef INVARIANTS
1196 if (speed == 0) {
1197 printf("snd_maestro: rch.speed == 0, which shouldn't\n");
1198 speed = 1;
1199 }
1200 #endif
1201 return (48000 * (ch->blklen << (!ch->stereo))
1202 + speed - 1) / speed;
1203 }
1204
1205 static void
set_timer(struct agg_info * ess)1206 set_timer(struct agg_info *ess)
1207 {
1208 int i;
1209 u_int dv = 32 << 7, newdv;
1210
1211 for (i = 0; i < ess->playchns; i++)
1212 if ((ess->active & (1 << i)) &&
1213 (dv > (newdv = calc_timer_div(ess->pch + i))))
1214 dv = newdv;
1215 if ((ess->active & (1 << i)) &&
1216 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1217 dv = newdv;
1218
1219 wp_settimer(ess, dv);
1220 }
1221
1222 /* -----------------------------
1223 * Newpcm glue.
1224 */
1225
1226 /* AC97 mixer interface. */
1227
1228 static u_int32_t
agg_ac97_init(kobj_t obj,void * sc)1229 agg_ac97_init(kobj_t obj, void *sc)
1230 {
1231 struct agg_info *ess = sc;
1232
1233 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1234 }
1235
1236 static int
agg_ac97_read(kobj_t obj,void * sc,int regno)1237 agg_ac97_read(kobj_t obj, void *sc, int regno)
1238 {
1239 struct agg_info *ess = sc;
1240 int ret;
1241
1242 /* XXX sound locking violation: agg_lock(ess); */
1243 ret = agg_rdcodec(ess, regno);
1244 /* agg_unlock(ess); */
1245 return ret;
1246 }
1247
1248 static int
agg_ac97_write(kobj_t obj,void * sc,int regno,u_int32_t data)1249 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1250 {
1251 struct agg_info *ess = sc;
1252 int ret;
1253
1254 /* XXX sound locking violation: agg_lock(ess); */
1255 ret = agg_wrcodec(ess, regno, data);
1256 /* agg_unlock(ess); */
1257 return ret;
1258 }
1259
1260 static kobj_method_t agg_ac97_methods[] = {
1261 KOBJMETHOD(ac97_init, agg_ac97_init),
1262 KOBJMETHOD(ac97_read, agg_ac97_read),
1263 KOBJMETHOD(ac97_write, agg_ac97_write),
1264 KOBJMETHOD_END
1265 };
1266 AC97_DECLARE(agg_ac97);
1267
1268 /* -------------------------------------------------------------------- */
1269
1270 /* Playback channel. */
1271
1272 static void *
aggpch_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)1273 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1274 struct pcm_channel *c, int dir)
1275 {
1276 struct agg_info *ess = devinfo;
1277 struct agg_chinfo *ch;
1278 bus_addr_t physaddr;
1279 void *p;
1280
1281 KASSERT((dir == PCMDIR_PLAY),
1282 ("aggpch_init() called for RECORDING channel!"));
1283 ch = ess->pch + ess->playchns;
1284
1285 ch->parent = ess;
1286 ch->channel = c;
1287 ch->buffer = b;
1288 ch->num = ess->playchns;
1289
1290 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr, &ch->map);
1291 if (p == NULL)
1292 return NULL;
1293 ch->phys = physaddr;
1294 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1295
1296 sndbuf_setup(b, p, ess->bufsz);
1297 ch->blklen = sndbuf_getblksz(b) / 2;
1298 ch->buflen = sndbuf_getsize(b) / 2;
1299 ess->playchns++;
1300
1301 return ch;
1302 }
1303
1304 static void
adjust_pchbase(struct agg_chinfo * chans,u_int n,u_int size)1305 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1306 {
1307 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1308 u_int i, j, k;
1309 bus_addr_t base;
1310
1311 /* sort pchs by phys address */
1312 for (i = 0; i < n; i++) {
1313 for (j = 0; j < i; j++)
1314 if (chans[i].phys < pchs[j]->phys) {
1315 for (k = i; k > j; k--)
1316 pchs[k] = pchs[k - 1];
1317 break;
1318 }
1319 pchs[j] = chans + i;
1320 }
1321
1322 /* use new base register if next buffer can not be addressed
1323 via current base. */
1324 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1325 base = pchs[0]->base;
1326 for (k = 1, i = 1; i < n; i++) {
1327 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1328 /* not addressable: assign new base */
1329 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1330 else
1331 pchs[i]->base = base;
1332 }
1333 #undef BASE_SHIFT
1334
1335 if (bootverbose) {
1336 printf("Total of %d bases are assigned.\n", k);
1337 for (i = 0; i < n; i++) {
1338 printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1339 i, (long long)chans[i].phys,
1340 (long long)(chans[i].phys -
1341 chans[i].base) >> 1);
1342 }
1343 }
1344 }
1345
1346 static int
aggpch_free(kobj_t obj,void * data)1347 aggpch_free(kobj_t obj, void *data)
1348 {
1349 struct agg_chinfo *ch = data;
1350 struct agg_info *ess = ch->parent;
1351
1352 /* free up buffer - called after channel stopped */
1353 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer), ch->map);
1354
1355 /* return 0 if ok */
1356 return 0;
1357 }
1358
1359 static int
aggpch_setformat(kobj_t obj,void * data,u_int32_t format)1360 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1361 {
1362 struct agg_chinfo *ch = data;
1363
1364 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1365 return EINVAL;
1366 ch->stereo = ch->qs16 = ch->us = 0;
1367 if (AFMT_CHANNEL(format) > 1)
1368 ch->stereo = 1;
1369
1370 if (format & AFMT_U8 || format & AFMT_S8) {
1371 if (format & AFMT_U8)
1372 ch->us = 1;
1373 } else
1374 ch->qs16 = 1;
1375 return 0;
1376 }
1377
1378 static u_int32_t
aggpch_setspeed(kobj_t obj,void * data,u_int32_t speed)1379 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1380 {
1381
1382 ((struct agg_chinfo*)data)->speed = speed;
1383
1384 return (speed);
1385 }
1386
1387 static u_int32_t
aggpch_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)1388 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1389 {
1390 struct agg_chinfo *ch = data;
1391 int blkcnt;
1392
1393 /* try to keep at least 20msec DMA space */
1394 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1395 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1396
1397 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1398 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1399 blkcnt = sndbuf_getblkcnt(ch->buffer);
1400 blocksize = sndbuf_getblksz(ch->buffer);
1401 } else {
1402 sndbuf_setblkcnt(ch->buffer, blkcnt);
1403 sndbuf_setblksz(ch->buffer, blocksize);
1404 }
1405
1406 ch->blklen = blocksize / 2;
1407 ch->buflen = blkcnt * blocksize / 2;
1408 return blocksize;
1409 }
1410
1411 static int
aggpch_trigger(kobj_t obj,void * data,int go)1412 aggpch_trigger(kobj_t obj, void *data, int go)
1413 {
1414 struct agg_chinfo *ch = data;
1415
1416 switch (go) {
1417 case PCMTRIG_EMLDMAWR:
1418 break;
1419 case PCMTRIG_START:
1420 aggch_start_dac(ch);
1421 break;
1422 case PCMTRIG_ABORT:
1423 case PCMTRIG_STOP:
1424 aggch_stop_dac(ch);
1425 break;
1426 }
1427 return 0;
1428 }
1429
1430 static u_int32_t
aggpch_getptr(kobj_t obj,void * data)1431 aggpch_getptr(kobj_t obj, void *data)
1432 {
1433 struct agg_chinfo *ch = data;
1434 u_int32_t cp;
1435
1436 agg_lock(ch->parent);
1437 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1438 agg_unlock(ch->parent);
1439
1440 return ch->qs16 && ch->stereo
1441 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1442 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1443 }
1444
1445 static struct pcmchan_caps *
aggpch_getcaps(kobj_t obj,void * data)1446 aggpch_getcaps(kobj_t obj, void *data)
1447 {
1448 static u_int32_t playfmt[] = {
1449 SND_FORMAT(AFMT_U8, 1, 0),
1450 SND_FORMAT(AFMT_U8, 2, 0),
1451 SND_FORMAT(AFMT_S8, 1, 0),
1452 SND_FORMAT(AFMT_S8, 2, 0),
1453 SND_FORMAT(AFMT_S16_LE, 1, 0),
1454 SND_FORMAT(AFMT_S16_LE, 2, 0),
1455 0
1456 };
1457 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1458
1459 return &playcaps;
1460 }
1461
1462 static kobj_method_t aggpch_methods[] = {
1463 KOBJMETHOD(channel_init, aggpch_init),
1464 KOBJMETHOD(channel_free, aggpch_free),
1465 KOBJMETHOD(channel_setformat, aggpch_setformat),
1466 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1467 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1468 KOBJMETHOD(channel_trigger, aggpch_trigger),
1469 KOBJMETHOD(channel_getptr, aggpch_getptr),
1470 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1471 KOBJMETHOD_END
1472 };
1473 CHANNEL_DECLARE(aggpch);
1474
1475 /* -------------------------------------------------------------------- */
1476
1477 /* Recording channel. */
1478
1479 static void *
aggrch_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)1480 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1481 struct pcm_channel *c, int dir)
1482 {
1483 struct agg_info *ess = devinfo;
1484 struct agg_rchinfo *ch;
1485 u_int8_t *p;
1486
1487 KASSERT((dir == PCMDIR_REC),
1488 ("aggrch_init() called for PLAYBACK channel!"));
1489 ch = &ess->rch;
1490
1491 ch->parent = ess;
1492 ch->channel = c;
1493 ch->buffer = b;
1494
1495 /* Uses the bottom-half of the status buffer. */
1496 p = ess->stat + ess->bufsz;
1497 ch->phys = ess->phys + ess->bufsz;
1498 ch->base = ess->phys;
1499 ch->src = (int16_t *)(p + ess->bufsz);
1500 ch->srcphys = ch->phys + ess->bufsz;
1501 ch->sink = (int16_t *)p;
1502
1503 sndbuf_setup(b, p, ess->bufsz);
1504 ch->blklen = sndbuf_getblksz(b) / 2;
1505 ch->buflen = sndbuf_getsize(b) / 2;
1506
1507 return ch;
1508 }
1509
1510 static int
aggrch_setformat(kobj_t obj,void * data,u_int32_t format)1511 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1512 {
1513 struct agg_rchinfo *ch = data;
1514
1515 if (!(format & AFMT_S16_LE))
1516 return EINVAL;
1517 if (AFMT_CHANNEL(format) > 1)
1518 ch->stereo = 1;
1519 else
1520 ch->stereo = 0;
1521 return 0;
1522 }
1523
1524 static u_int32_t
aggrch_setspeed(kobj_t obj,void * data,u_int32_t speed)1525 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1526 {
1527
1528 ((struct agg_rchinfo*)data)->speed = speed;
1529
1530 return (speed);
1531 }
1532
1533 static u_int32_t
aggrch_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)1534 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1535 {
1536 struct agg_rchinfo *ch = data;
1537 int blkcnt;
1538
1539 /* try to keep at least 20msec DMA space */
1540 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1541 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1542
1543 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1544 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1545 blkcnt = sndbuf_getblkcnt(ch->buffer);
1546 blocksize = sndbuf_getblksz(ch->buffer);
1547 } else {
1548 sndbuf_setblkcnt(ch->buffer, blkcnt);
1549 sndbuf_setblksz(ch->buffer, blocksize);
1550 }
1551
1552 ch->blklen = blocksize / 2;
1553 ch->buflen = blkcnt * blocksize / 2;
1554 return blocksize;
1555 }
1556
1557 static int
aggrch_trigger(kobj_t obj,void * sc,int go)1558 aggrch_trigger(kobj_t obj, void *sc, int go)
1559 {
1560 struct agg_rchinfo *ch = sc;
1561
1562 switch (go) {
1563 case PCMTRIG_EMLDMARD:
1564 if (ch->stereo)
1565 aggch_feed_adc_stereo(ch);
1566 else
1567 aggch_feed_adc_mono(ch);
1568 break;
1569 case PCMTRIG_START:
1570 aggch_start_adc(ch);
1571 break;
1572 case PCMTRIG_ABORT:
1573 case PCMTRIG_STOP:
1574 aggch_stop_adc(ch);
1575 break;
1576 }
1577 return 0;
1578 }
1579
1580 static u_int32_t
aggrch_getptr(kobj_t obj,void * sc)1581 aggrch_getptr(kobj_t obj, void *sc)
1582 {
1583 struct agg_rchinfo *ch = sc;
1584
1585 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1586 }
1587
1588 static struct pcmchan_caps *
aggrch_getcaps(kobj_t obj,void * sc)1589 aggrch_getcaps(kobj_t obj, void *sc)
1590 {
1591 static u_int32_t recfmt[] = {
1592 SND_FORMAT(AFMT_S16_LE, 1, 0),
1593 SND_FORMAT(AFMT_S16_LE, 2, 0),
1594 0
1595 };
1596 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1597
1598 return &reccaps;
1599 }
1600
1601 static kobj_method_t aggrch_methods[] = {
1602 KOBJMETHOD(channel_init, aggrch_init),
1603 /* channel_free: no-op */
1604 KOBJMETHOD(channel_setformat, aggrch_setformat),
1605 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1606 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1607 KOBJMETHOD(channel_trigger, aggrch_trigger),
1608 KOBJMETHOD(channel_getptr, aggrch_getptr),
1609 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1610 KOBJMETHOD_END
1611 };
1612 CHANNEL_DECLARE(aggrch);
1613
1614 /* -----------------------------
1615 * Bus space.
1616 */
1617
1618 static void
agg_intr(void * sc)1619 agg_intr(void *sc)
1620 {
1621 struct agg_info* ess = sc;
1622 register u_int8_t status;
1623 int i;
1624 u_int m;
1625
1626 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1627 if (!status)
1628 return;
1629
1630 /* Acknowledge intr. */
1631 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1632
1633 if (status & HOSTINT_STAT_DSOUND) {
1634 #ifdef AGG_JITTER_CORRECTION
1635 agg_lock(ess);
1636 #endif
1637 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1638 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1639 #ifdef AGG_JITTER_CORRECTION
1640 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1641 if (ess->active & m)
1642 suppress_jitter(ess->pch + i);
1643 }
1644 if (ess->active & m)
1645 suppress_rec_jitter(&ess->rch);
1646 agg_unlock(ess);
1647 #endif
1648 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1649 if (ess->active & m) {
1650 if (ess->curpwr <= PCI_POWERSTATE_D1)
1651 chn_intr(ess->pch[i].channel);
1652 else {
1653 m = 0;
1654 break;
1655 }
1656 }
1657 }
1658 if ((ess->active & m)
1659 && ess->curpwr <= PCI_POWERSTATE_D1)
1660 chn_intr(ess->rch.channel);
1661 }
1662 #ifdef AGG_JITTER_CORRECTION
1663 else
1664 agg_unlock(ess);
1665 #endif
1666 }
1667
1668 if (status & HOSTINT_STAT_HWVOL) {
1669 register u_int8_t event;
1670
1671 agg_lock(ess);
1672 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1673 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1674 agg_unlock(ess);
1675
1676 switch (event) {
1677 case HWVOL_UP:
1678 mixer_hwvol_step(ess->dev, 1, 1);
1679 break;
1680 case HWVOL_DOWN:
1681 mixer_hwvol_step(ess->dev, -1, -1);
1682 break;
1683 case HWVOL_NOP:
1684 break;
1685 default:
1686 if (event & HWVOL_MUTE) {
1687 mixer_hwvol_mute(ess->dev);
1688 break;
1689 }
1690 device_printf(ess->dev,
1691 "%s: unknown HWVOL event 0x%x\n",
1692 device_get_nameunit(ess->dev), event);
1693 }
1694 }
1695 }
1696
1697 static void
setmap(void * arg,bus_dma_segment_t * segs,int nseg,int error)1698 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1699 {
1700 bus_addr_t *phys = arg;
1701
1702 *phys = error? 0 : segs->ds_addr;
1703
1704 if (bootverbose) {
1705 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1706 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1707 nseg, error);
1708 }
1709 }
1710
1711 static void *
dma_malloc(bus_dma_tag_t dmat,u_int32_t sz,bus_addr_t * phys,bus_dmamap_t * map)1712 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys,
1713 bus_dmamap_t *map)
1714 {
1715 void *buf;
1716
1717 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, map))
1718 return NULL;
1719 if (bus_dmamap_load(dmat, *map, buf, sz, setmap, phys, 0) != 0 ||
1720 *phys == 0) {
1721 bus_dmamem_free(dmat, buf, *map);
1722 return NULL;
1723 }
1724 return buf;
1725 }
1726
1727 static void
dma_free(bus_dma_tag_t dmat,void * buf,bus_dmamap_t map)1728 dma_free(bus_dma_tag_t dmat, void *buf, bus_dmamap_t map)
1729 {
1730 bus_dmamap_unload(dmat, map);
1731 bus_dmamem_free(dmat, buf, map);
1732 }
1733
1734 static int
agg_probe(device_t dev)1735 agg_probe(device_t dev)
1736 {
1737 char *s = NULL;
1738
1739 switch (pci_get_devid(dev)) {
1740 case MAESTRO_1_PCI_ID:
1741 s = "ESS Technology Maestro-1";
1742 break;
1743
1744 case MAESTRO_2_PCI_ID:
1745 s = "ESS Technology Maestro-2";
1746 break;
1747
1748 case MAESTRO_2E_PCI_ID:
1749 s = "ESS Technology Maestro-2E";
1750 break;
1751 }
1752
1753 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1754 device_set_desc(dev, s);
1755 return BUS_PROBE_DEFAULT;
1756 }
1757 return ENXIO;
1758 }
1759
1760 static int
agg_attach(device_t dev)1761 agg_attach(device_t dev)
1762 {
1763 struct agg_info *ess = NULL;
1764 u_int32_t data;
1765 int regid = PCIR_BAR(0);
1766 struct resource *reg = NULL;
1767 struct ac97_info *codec = NULL;
1768 int irqid = 0;
1769 struct resource *irq = NULL;
1770 void *ih = NULL;
1771 char status[SND_STATUSLEN];
1772 int dacn, ret = 0;
1773
1774 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1775 ess->dev = dev;
1776
1777 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1778 MTX_DEF | MTX_RECURSE);
1779 if (!mtx_initialized(&ess->lock)) {
1780 device_printf(dev, "failed to create a mutex.\n");
1781 ret = ENOMEM;
1782 goto bad;
1783 }
1784
1785 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1786 "dac", &dacn) == 0) {
1787 if (dacn < 1)
1788 dacn = 1;
1789 else if (dacn > AGG_MAXPLAYCH)
1790 dacn = AGG_MAXPLAYCH;
1791 } else
1792 dacn = AGG_MAXPLAYCH;
1793
1794 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1795 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1796 /*align */ 4, 1 << (16+1),
1797 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1798 /*filter*/ NULL, NULL,
1799 /*size */ ess->bufsz, 1, 0x3ffff,
1800 /*flags */ 0,
1801 /*lock */ busdma_lock_mutex, &Giant,
1802 &ess->buf_dmat) != 0) {
1803 device_printf(dev, "unable to create dma tag\n");
1804 ret = ENOMEM;
1805 goto bad;
1806 }
1807
1808 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1809 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1810 1 << (16+1),
1811 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1812 /*filter*/ NULL, NULL,
1813 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1814 /*flags */ 0,
1815 /*lock */ busdma_lock_mutex, &Giant,
1816 &ess->stat_dmat) != 0) {
1817 device_printf(dev, "unable to create dma tag\n");
1818 ret = ENOMEM;
1819 goto bad;
1820 }
1821
1822 /* Allocate the room for brain-damaging status buffer. */
1823 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys,
1824 &ess->stat_map);
1825 if (ess->stat == NULL) {
1826 device_printf(dev, "cannot allocate status buffer\n");
1827 ret = ENOMEM;
1828 goto bad;
1829 }
1830 if (bootverbose)
1831 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1832 (long long)ess->phys);
1833
1834 /* State D0-uninitialized. */
1835 ess->curpwr = PCI_POWERSTATE_D3;
1836 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1837
1838 pci_enable_busmaster(dev);
1839
1840 /* Allocate resources. */
1841 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id, RF_ACTIVE);
1842 if (reg != NULL) {
1843 ess->reg = reg;
1844 ess->regid = regid;
1845 ess->st = rman_get_bustag(reg);
1846 ess->sh = rman_get_bushandle(reg);
1847 } else {
1848 device_printf(dev, "unable to map register space\n");
1849 ret = ENXIO;
1850 goto bad;
1851 }
1852 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1853 RF_ACTIVE | RF_SHAREABLE);
1854 if (irq != NULL) {
1855 ess->irq = irq;
1856 ess->irqid = irqid;
1857 } else {
1858 device_printf(dev, "unable to map interrupt\n");
1859 ret = ENXIO;
1860 goto bad;
1861 }
1862
1863 /* Setup resources. */
1864 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1865 device_printf(dev, "unable to setup interrupt\n");
1866 ret = ENXIO;
1867 goto bad;
1868 } else
1869 ess->ih = ih;
1870
1871 /* Transition from D0-uninitialized to D0. */
1872 agg_lock(ess);
1873 agg_power(ess, PCI_POWERSTATE_D0);
1874 if (agg_rdcodec(ess, 0) == 0x80) {
1875 /* XXX - TODO: PT101 */
1876 agg_unlock(ess);
1877 device_printf(dev, "PT101 codec detected!\n");
1878 ret = ENXIO;
1879 goto bad;
1880 }
1881 agg_unlock(ess);
1882 codec = AC97_CREATE(dev, ess, agg_ac97);
1883 if (codec == NULL) {
1884 device_printf(dev, "failed to create AC97 codec softc!\n");
1885 ret = ENOMEM;
1886 goto bad;
1887 }
1888 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1889 device_printf(dev, "mixer initialization failed!\n");
1890 ret = ENXIO;
1891 goto bad;
1892 }
1893 ess->codec = codec;
1894
1895 ret = pcm_register(dev, ess, dacn, 1);
1896 if (ret)
1897 goto bad;
1898
1899 mixer_hwvol_init(dev);
1900 agg_lock(ess);
1901 agg_power(ess, powerstate_init);
1902 agg_unlock(ess);
1903 for (data = 0; data < dacn; data++)
1904 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1905 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1906 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1907
1908 snprintf(status, SND_STATUSLEN,
1909 "port 0x%jx-0x%jx irq %jd at device %d.%d on pci%d",
1910 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1911 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1912 pcm_setstatus(dev, status);
1913
1914 return 0;
1915
1916 bad:
1917 if (codec != NULL)
1918 ac97_destroy(codec);
1919 if (ih != NULL)
1920 bus_teardown_intr(dev, irq, ih);
1921 if (irq != NULL)
1922 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1923 if (reg != NULL)
1924 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1925 if (ess != NULL) {
1926 if (ess->stat != NULL)
1927 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1928 if (ess->stat_dmat != NULL)
1929 bus_dma_tag_destroy(ess->stat_dmat);
1930 if (ess->buf_dmat != NULL)
1931 bus_dma_tag_destroy(ess->buf_dmat);
1932 if (mtx_initialized(&ess->lock))
1933 mtx_destroy(&ess->lock);
1934 free(ess, M_DEVBUF);
1935 }
1936
1937 return ret;
1938 }
1939
1940 static int
agg_detach(device_t dev)1941 agg_detach(device_t dev)
1942 {
1943 struct agg_info *ess = pcm_getdevinfo(dev);
1944 int r;
1945 u_int16_t icr;
1946
1947 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1948 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1949
1950 agg_lock(ess);
1951 if (ess->active) {
1952 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1953 agg_unlock(ess);
1954 return EBUSY;
1955 }
1956 agg_unlock(ess);
1957
1958 r = pcm_unregister(dev);
1959 if (r) {
1960 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1961 return r;
1962 }
1963
1964 agg_lock(ess);
1965 agg_power(ess, PCI_POWERSTATE_D3);
1966 agg_unlock(ess);
1967
1968 bus_teardown_intr(dev, ess->irq, ess->ih);
1969 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1970 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1971 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1972 bus_dma_tag_destroy(ess->stat_dmat);
1973 bus_dma_tag_destroy(ess->buf_dmat);
1974 mtx_destroy(&ess->lock);
1975 free(ess, M_DEVBUF);
1976 return 0;
1977 }
1978
1979 static int
agg_suspend(device_t dev)1980 agg_suspend(device_t dev)
1981 {
1982 struct agg_info *ess = pcm_getdevinfo(dev);
1983
1984 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1985 agg_lock(ess);
1986 agg_power(ess, PCI_POWERSTATE_D3);
1987 agg_unlock(ess);
1988
1989 return 0;
1990 }
1991
1992 static int
agg_resume(device_t dev)1993 agg_resume(device_t dev)
1994 {
1995 int i;
1996 struct agg_info *ess = pcm_getdevinfo(dev);
1997
1998 for (i = 0; i < ess->playchns; i++)
1999 if (ess->active & (1 << i))
2000 aggch_start_dac(ess->pch + i);
2001 if (ess->active & (1 << i))
2002 aggch_start_adc(&ess->rch);
2003
2004 agg_lock(ess);
2005 if (!ess->active)
2006 agg_power(ess, powerstate_init);
2007 agg_unlock(ess);
2008
2009 if (mixer_reinit(dev)) {
2010 device_printf(dev, "unable to reinitialize the mixer\n");
2011 return ENXIO;
2012 }
2013
2014 return 0;
2015 }
2016
2017 static int
agg_shutdown(device_t dev)2018 agg_shutdown(device_t dev)
2019 {
2020 struct agg_info *ess = pcm_getdevinfo(dev);
2021
2022 agg_lock(ess);
2023 agg_power(ess, PCI_POWERSTATE_D3);
2024 agg_unlock(ess);
2025
2026 return 0;
2027 }
2028
2029 static device_method_t agg_methods[] = {
2030 DEVMETHOD(device_probe, agg_probe),
2031 DEVMETHOD(device_attach, agg_attach),
2032 DEVMETHOD(device_detach, agg_detach),
2033 DEVMETHOD(device_suspend, agg_suspend),
2034 DEVMETHOD(device_resume, agg_resume),
2035 DEVMETHOD(device_shutdown, agg_shutdown),
2036 { 0, 0 }
2037 };
2038
2039 static driver_t agg_driver = {
2040 "pcm",
2041 agg_methods,
2042 PCM_SOFTC_SIZE,
2043 };
2044
2045 /*static devclass_t pcm_devclass;*/
2046
2047 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2048 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2049 MODULE_VERSION(snd_maestro, 1);
2050