1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
3 *
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <[email protected]>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <[email protected]>
9 * Copyright (c) 2014-2016 Michal Meloun <[email protected]>
10 * All rights reserved.
11 *
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
41 */
42 /*-
43 * Copyright (c) 2003 Networks Associates Technology, Inc.
44 * All rights reserved.
45 *
46 * This software was developed for the FreeBSD Project by Jake Burkholder,
47 * Safeport Network Services, and Network Associates Laboratories, the
48 * Security Research Division of Network Associates, Inc. under
49 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
50 * CHATS research program.
51 *
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
54 * are met:
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 *
61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71 * SUCH DAMAGE.
72 */
73
74 #include <sys/cdefs.h>
75 /*
76 * Manages physical address maps.
77 *
78 * Since the information managed by this module is
79 * also stored by the logical address mapping module,
80 * this module may throw away valid virtual-to-physical
81 * mappings at almost any time. However, invalidations
82 * of virtual-to-physical mappings must be done as
83 * requested.
84 *
85 * In order to cope with hardware architectures which
86 * make virtual-to-physical map invalidates expensive,
87 * this module may delay invalidate or reduced protection
88 * operations until such time as they are actually
89 * necessary. This module is given full information as
90 * to which processors are currently using which maps,
91 * and to when physical maps must be made correct.
92 */
93
94 #include "opt_vm.h"
95 #include "opt_pmap.h"
96 #include "opt_ddb.h"
97
98 #include <sys/param.h>
99 #include <sys/systm.h>
100 #include <sys/kernel.h>
101 #include <sys/ktr.h>
102 #include <sys/lock.h>
103 #include <sys/proc.h>
104 #include <sys/rwlock.h>
105 #include <sys/malloc.h>
106 #include <sys/vmmeter.h>
107 #include <sys/malloc.h>
108 #include <sys/mman.h>
109 #include <sys/sf_buf.h>
110 #include <sys/smp.h>
111 #include <sys/sched.h>
112 #include <sys/sysctl.h>
113
114 #ifdef DDB
115 #include <ddb/ddb.h>
116 #endif
117
118 #include <vm/vm.h>
119 #include <vm/uma.h>
120 #include <vm/pmap.h>
121 #include <vm/vm_param.h>
122 #include <vm/vm_kern.h>
123 #include <vm/vm_object.h>
124 #include <vm/vm_map.h>
125 #include <vm/vm_page.h>
126 #include <vm/vm_pageout.h>
127 #include <vm/vm_phys.h>
128 #include <vm/vm_extern.h>
129 #include <vm/vm_reserv.h>
130 #include <sys/lock.h>
131 #include <sys/mutex.h>
132
133 #include <machine/md_var.h>
134 #include <machine/pmap_var.h>
135 #include <machine/cpu.h>
136 #include <machine/pcb.h>
137 #include <machine/sf_buf.h>
138 #ifdef SMP
139 #include <machine/smp.h>
140 #endif
141 #ifndef PMAP_SHPGPERPROC
142 #define PMAP_SHPGPERPROC 200
143 #endif
144
145 #ifndef DIAGNOSTIC
146 #define PMAP_INLINE __inline
147 #else
148 #define PMAP_INLINE
149 #endif
150
151 #ifdef PMAP_DEBUG
152 static void pmap_zero_page_check(vm_page_t m);
153 void pmap_debug(int level);
154 int pmap_pid_dump(int pid);
155
156 #define PDEBUG(_lev_,_stat_) \
157 if (pmap_debug_level >= (_lev_)) \
158 ((_stat_))
159 #define dprintf printf
160 int pmap_debug_level = 1;
161 #else /* PMAP_DEBUG */
162 #define PDEBUG(_lev_,_stat_) /* Nothing */
163 #define dprintf(x, arg...)
164 #endif /* PMAP_DEBUG */
165
166 /*
167 * Level 2 page tables map definion ('max' is excluded).
168 */
169
170 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
171 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
172
173 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
174 #define UPT2V_MAX_ADDRESS \
175 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
176
177 /*
178 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
179 * 4KB (PTE2) page mappings have identical settings for the following fields:
180 */
181 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
182 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
183 PTE2_ATTR_MASK)
184
185 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
186 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
187 PTE1_ATTR_MASK)
188
189 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
190 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
191 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
192 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
193 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
194 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
195 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
196 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
197 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
198 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
199 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
200
201 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
202 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
203 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
204 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
205 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
206 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
207 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
208 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
209 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
210 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
211 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
212
213 /*
214 * PTE2 descriptors creation macros.
215 */
216 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
217 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
218
219 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
220 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
221
222 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
223 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
224
225 #define PV_STATS
226 #ifdef PV_STATS
227 #define PV_STAT(x) do { x ; } while (0)
228 #else
229 #define PV_STAT(x) do { } while (0)
230 #endif
231
232 /*
233 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
234 * We can init many things with no memory allocation thanks to its static
235 * allocation and this brings two main advantages:
236 * (1) other cores can be started very simply,
237 * (2) various boot loaders can be supported as its arguments can be processed
238 * in virtual address space and can be moved to safe location before
239 * first allocation happened.
240 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
241 * However, the table is uninitialized and so lays in bss. Therefore kernel
242 * image size is not influenced.
243 *
244 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
245 * CPU suspend/resume game.
246 */
247 extern pt1_entry_t boot_pt1[];
248
249 vm_paddr_t base_pt1;
250 pt1_entry_t *kern_pt1;
251 pt2_entry_t *kern_pt2tab;
252 pt2_entry_t *PT2MAP;
253
254 static uint32_t ttb_flags;
255 static vm_memattr_t pt_memattr;
256 ttb_entry_t pmap_kern_ttb;
257
258 struct pmap kernel_pmap_store;
259 LIST_HEAD(pmaplist, pmap);
260 static struct pmaplist allpmaps;
261 static struct mtx allpmaps_lock;
262
263 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
264 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
265
266 static vm_offset_t kernel_vm_end_new;
267 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
268 vm_offset_t vm_max_kernel_address;
269 vm_paddr_t kernel_l1pa;
270
271 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
272
273 /*
274 * Data for the pv entry allocation mechanism
275 */
276 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
277 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
278 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
279 static int shpgperproc = PMAP_SHPGPERPROC;
280
281 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
282 int pv_maxchunks; /* How many chunks we have KVA for */
283 vm_offset_t pv_vafree; /* freelist stored in the PTE */
284
285 vm_paddr_t first_managed_pa;
286 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
287
288 /*
289 * All those kernel PT submaps that BSD is so fond of
290 */
291 caddr_t _tmppt = 0;
292
293 /*
294 * Crashdump maps.
295 */
296 static caddr_t crashdumpmap;
297
298 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
299 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
300 #ifdef DDB
301 static pt2_entry_t *PMAP3;
302 static pt2_entry_t *PADDR3;
303 static int PMAP3cpu __unused; /* for SMP only */
304 #endif
305 #ifdef SMP
306 static int PMAP1cpu;
307 static int PMAP1changedcpu;
308 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
309 &PMAP1changedcpu, 0,
310 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
311 #endif
312 static int PMAP1changed;
313 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
314 &PMAP1changed, 0,
315 "Number of times pmap_pte2_quick changed PMAP1");
316 static int PMAP1unchanged;
317 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
318 &PMAP1unchanged, 0,
319 "Number of times pmap_pte2_quick didn't change PMAP1");
320 static struct mtx PMAP2mutex;
321
322 /*
323 * Internal flags for pmap_enter()'s helper functions.
324 */
325 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
326 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
327
328 static __inline void pt2_wirecount_init(vm_page_t m);
329 static boolean_t pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
330 vm_offset_t va);
331 static int pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1,
332 u_int flags, vm_page_t m);
333 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
334
335 /*
336 * Function to set the debug level of the pmap code.
337 */
338 #ifdef PMAP_DEBUG
339 void
pmap_debug(int level)340 pmap_debug(int level)
341 {
342
343 pmap_debug_level = level;
344 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
345 }
346 #endif /* PMAP_DEBUG */
347
348 /*
349 * This table must corespond with memory attribute configuration in vm.h.
350 * First entry is used for normal system mapping.
351 *
352 * Device memory is always marked as shared.
353 * Normal memory is shared only in SMP .
354 * Not outer shareable bits are not used yet.
355 * Class 6 cannot be used on ARM11.
356 */
357 #define TEXDEF_TYPE_SHIFT 0
358 #define TEXDEF_TYPE_MASK 0x3
359 #define TEXDEF_INNER_SHIFT 2
360 #define TEXDEF_INNER_MASK 0x3
361 #define TEXDEF_OUTER_SHIFT 4
362 #define TEXDEF_OUTER_MASK 0x3
363 #define TEXDEF_NOS_SHIFT 6
364 #define TEXDEF_NOS_MASK 0x1
365
366 #define TEX(t, i, o, s) \
367 ((t) << TEXDEF_TYPE_SHIFT) | \
368 ((i) << TEXDEF_INNER_SHIFT) | \
369 ((o) << TEXDEF_OUTER_SHIFT | \
370 ((s) << TEXDEF_NOS_SHIFT))
371
372 static uint32_t tex_class[8] = {
373 /* type inner cache outer cache */
374 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
375 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
376 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
377 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
378 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
379 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
380 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
381 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
382 };
383 #undef TEX
384
385 static uint32_t pte2_attr_tab[8] = {
386 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
387 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
388 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
389 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
390 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
391 0, /* 5 - NOT USED YET */
392 0, /* 6 - NOT USED YET */
393 0 /* 7 - NOT USED YET */
394 };
395 CTASSERT(VM_MEMATTR_WB_WA == 0);
396 CTASSERT(VM_MEMATTR_NOCACHE == 1);
397 CTASSERT(VM_MEMATTR_DEVICE == 2);
398 CTASSERT(VM_MEMATTR_SO == 3);
399 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
400 #define VM_MEMATTR_END (VM_MEMATTR_WRITE_THROUGH + 1)
401
402 boolean_t
pmap_is_valid_memattr(pmap_t pmap __unused,vm_memattr_t mode)403 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
404 {
405
406 return (mode >= 0 && mode < VM_MEMATTR_END);
407 }
408
409 static inline uint32_t
vm_memattr_to_pte2(vm_memattr_t ma)410 vm_memattr_to_pte2(vm_memattr_t ma)
411 {
412
413 KASSERT((u_int)ma < VM_MEMATTR_END,
414 ("%s: bad vm_memattr_t %d", __func__, ma));
415 return (pte2_attr_tab[(u_int)ma]);
416 }
417
418 static inline uint32_t
vm_page_pte2_attr(vm_page_t m)419 vm_page_pte2_attr(vm_page_t m)
420 {
421
422 return (vm_memattr_to_pte2(m->md.pat_mode));
423 }
424
425 /*
426 * Convert TEX definition entry to TTB flags.
427 */
428 static uint32_t
encode_ttb_flags(int idx)429 encode_ttb_flags(int idx)
430 {
431 uint32_t inner, outer, nos, reg;
432
433 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
434 TEXDEF_INNER_MASK;
435 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
436 TEXDEF_OUTER_MASK;
437 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
438 TEXDEF_NOS_MASK;
439
440 reg = nos << 5;
441 reg |= outer << 3;
442 if (cpuinfo.coherent_walk)
443 reg |= (inner & 0x1) << 6;
444 reg |= (inner & 0x2) >> 1;
445 #ifdef SMP
446 ARM_SMP_UP(
447 reg |= 1 << 1,
448 );
449 #endif
450 return reg;
451 }
452
453 /*
454 * Set TEX remapping registers in current CPU.
455 */
456 void
pmap_set_tex(void)457 pmap_set_tex(void)
458 {
459 uint32_t prrr, nmrr;
460 uint32_t type, inner, outer, nos;
461 int i;
462
463 #ifdef PMAP_PTE_NOCACHE
464 /* XXX fixme */
465 if (cpuinfo.coherent_walk) {
466 pt_memattr = VM_MEMATTR_WB_WA;
467 ttb_flags = encode_ttb_flags(0);
468 }
469 else {
470 pt_memattr = VM_MEMATTR_NOCACHE;
471 ttb_flags = encode_ttb_flags(1);
472 }
473 #else
474 pt_memattr = VM_MEMATTR_WB_WA;
475 ttb_flags = encode_ttb_flags(0);
476 #endif
477
478 prrr = 0;
479 nmrr = 0;
480
481 /* Build remapping register from TEX classes. */
482 for (i = 0; i < 8; i++) {
483 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
484 TEXDEF_TYPE_MASK;
485 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
486 TEXDEF_INNER_MASK;
487 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
488 TEXDEF_OUTER_MASK;
489 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
490 TEXDEF_NOS_MASK;
491
492 prrr |= type << (i * 2);
493 prrr |= nos << (i + 24);
494 nmrr |= inner << (i * 2);
495 nmrr |= outer << (i * 2 + 16);
496 }
497 /* Add shareable bits for device memory. */
498 prrr |= PRRR_DS0 | PRRR_DS1;
499
500 /* Add shareable bits for normal memory in SMP case. */
501 #ifdef SMP
502 ARM_SMP_UP(
503 prrr |= PRRR_NS1,
504 );
505 #endif
506 cp15_prrr_set(prrr);
507 cp15_nmrr_set(nmrr);
508
509 /* Caches are disabled, so full TLB flush should be enough. */
510 tlb_flush_all_local();
511 }
512
513 /*
514 * Remap one vm_meattr class to another one. This can be useful as
515 * workaround for SOC errata, e.g. if devices must be accessed using
516 * SO memory class.
517 *
518 * !!! Please note that this function is absolutely last resort thing.
519 * It should not be used under normal circumstances. !!!
520 *
521 * Usage rules:
522 * - it shall be called after pmap_bootstrap_prepare() and before
523 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
524 * to be called from platform_attach() or platform_late_init().
525 *
526 * - if remapping doesn't change caching mode, or until uncached class
527 * is remapped to any kind of cached one, then no other restriction exists.
528 *
529 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
530 * remapped) remain cached, then caller is resposible for calling
531 * of dcache_wbinv_poc_all().
532 *
533 * - remapping of any kind of cached class to uncached is not permitted.
534 */
535 void
pmap_remap_vm_attr(vm_memattr_t old_attr,vm_memattr_t new_attr)536 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
537 {
538 int old_idx, new_idx;
539
540 /* Map VM memattrs to indexes to tex_class table. */
541 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
542 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
543
544 /* Replace TEX attribute and apply it. */
545 tex_class[old_idx] = tex_class[new_idx];
546 pmap_set_tex();
547 }
548
549 /*
550 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
551 * KERNBASE is mapped by first L2 page table in L2 page table page. It
552 * meets same constrain due to PT2MAP being placed just under KERNBASE.
553 */
554 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
555 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
556
557 /*
558 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
559 * For now, anyhow, the following check must be fulfilled.
560 */
561 CTASSERT(PAGE_SIZE == PTE2_SIZE);
562 /*
563 * We don't want to mess up MI code with all MMU and PMAP definitions,
564 * so some things, which depend on other ones, are defined independently.
565 * Now, it is time to check that we don't screw up something.
566 */
567 CTASSERT(PDRSHIFT == PTE1_SHIFT);
568 /*
569 * Check L1 and L2 page table entries definitions consistency.
570 */
571 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
572 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
573 /*
574 * Check L2 page tables page consistency.
575 */
576 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
577 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
578 /*
579 * Check PT2TAB consistency.
580 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
581 * This should be done without remainder.
582 */
583 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
584
585 /*
586 * A PT2MAP magic.
587 *
588 * All level 2 page tables (PT2s) are mapped continuously and accordingly
589 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
590 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
591 * must be used together, but not necessary at once. The first PT2 in a page
592 * must map things on correctly aligned address and the others must follow
593 * in right order.
594 */
595 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
596 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
597 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
598
599 /*
600 * Check PT2TAB consistency.
601 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
602 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
603 * The both should be done without remainder.
604 */
605 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
606 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
607 /*
608 * The implementation was made general, however, with the assumption
609 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
610 * the code should be once more rechecked.
611 */
612 CTASSERT(NPG_IN_PT2TAB == 1);
613
614 /*
615 * Get offset of PT2 in a page
616 * associated with given PT1 index.
617 */
618 static __inline u_int
page_pt2off(u_int pt1_idx)619 page_pt2off(u_int pt1_idx)
620 {
621
622 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
623 }
624
625 /*
626 * Get physical address of PT2
627 * associated with given PT2s page and PT1 index.
628 */
629 static __inline vm_paddr_t
page_pt2pa(vm_paddr_t pgpa,u_int pt1_idx)630 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
631 {
632
633 return (pgpa + page_pt2off(pt1_idx));
634 }
635
636 /*
637 * Get first entry of PT2
638 * associated with given PT2s page and PT1 index.
639 */
640 static __inline pt2_entry_t *
page_pt2(vm_offset_t pgva,u_int pt1_idx)641 page_pt2(vm_offset_t pgva, u_int pt1_idx)
642 {
643
644 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
645 }
646
647 /*
648 * Get virtual address of PT2s page (mapped in PT2MAP)
649 * which holds PT2 which holds entry which maps given virtual address.
650 */
651 static __inline vm_offset_t
pt2map_pt2pg(vm_offset_t va)652 pt2map_pt2pg(vm_offset_t va)
653 {
654
655 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
656 return ((vm_offset_t)pt2map_entry(va));
657 }
658
659 /*****************************************************************************
660 *
661 * THREE pmap initialization milestones exist:
662 *
663 * locore.S
664 * -> fundamental init (including MMU) in ASM
665 *
666 * initarm()
667 * -> fundamental init continues in C
668 * -> first available physical address is known
669 *
670 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
671 * -> basic (safe) interface for physical address allocation is made
672 * -> basic (safe) interface for virtual mapping is made
673 * -> limited not SMP coherent work is possible
674 *
675 * -> more fundamental init continues in C
676 * -> locks and some more things are available
677 * -> all fundamental allocations and mappings are done
678 *
679 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
680 * -> phys_avail[] and virtual_avail is set
681 * -> control is passed to vm subsystem
682 * -> physical and virtual address allocation are off limit
683 * -> low level mapping functions, some SMP coherent,
684 * are available, which cannot be used before vm subsystem
685 * is being inited
686 *
687 * mi_startup()
688 * -> vm subsystem is being inited
689 *
690 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
691 * -> pmap is fully inited
692 *
693 *****************************************************************************/
694
695 /*****************************************************************************
696 *
697 * PMAP first stage initialization and utility functions
698 * for pre-bootstrap epoch.
699 *
700 * After pmap_bootstrap_prepare() is called, the following functions
701 * can be used:
702 *
703 * (1) strictly only for this stage functions for physical page allocations,
704 * virtual space allocations, and mappings:
705 *
706 * vm_paddr_t pmap_preboot_get_pages(u_int num);
707 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
708 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
709 * vm_offset_t pmap_preboot_get_vpages(u_int num);
710 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
711 * vm_prot_t prot, vm_memattr_t attr);
712 *
713 * (2) for all stages:
714 *
715 * vm_paddr_t pmap_kextract(vm_offset_t va);
716 *
717 * NOTE: This is not SMP coherent stage.
718 *
719 *****************************************************************************/
720
721 #define KERNEL_P2V(pa) \
722 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
723 #define KERNEL_V2P(va) \
724 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
725
726 static vm_paddr_t last_paddr;
727
728 /*
729 * Pre-bootstrap epoch page allocator.
730 */
731 vm_paddr_t
pmap_preboot_get_pages(u_int num)732 pmap_preboot_get_pages(u_int num)
733 {
734 vm_paddr_t ret;
735
736 ret = last_paddr;
737 last_paddr += num * PAGE_SIZE;
738
739 return (ret);
740 }
741
742 /*
743 * The fundamental initialization of PMAP stuff.
744 *
745 * Some things already happened in locore.S and some things could happen
746 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
747 * 1. Caches are disabled.
748 * 2. We are running on virtual addresses already with 'boot_pt1'
749 * as L1 page table.
750 * 3. So far, all virtual addresses can be converted to physical ones and
751 * vice versa by the following macros:
752 * KERNEL_P2V(pa) .... physical to virtual ones,
753 * KERNEL_V2P(va) .... virtual to physical ones.
754 *
755 * What is done herein:
756 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
757 * 2. PT2MAP magic is brought to live.
758 * 3. Basic preboot functions for page allocations and mappings can be used.
759 * 4. Everything is prepared for L1 cache enabling.
760 *
761 * Variations:
762 * 1. To use second TTB register, so kernel and users page tables will be
763 * separated. This way process forking - pmap_pinit() - could be faster,
764 * it saves physical pages and KVA per a process, and it's simple change.
765 * However, it will lead, due to hardware matter, to the following:
766 * (a) 2G space for kernel and 2G space for users.
767 * (b) 1G space for kernel in low addresses and 3G for users above it.
768 * A question is: Is the case (b) really an option? Note that case (b)
769 * does save neither physical memory and KVA.
770 */
771 void
pmap_bootstrap_prepare(vm_paddr_t last)772 pmap_bootstrap_prepare(vm_paddr_t last)
773 {
774 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
775 vm_offset_t pt2pg_va;
776 pt1_entry_t *pte1p;
777 pt2_entry_t *pte2p;
778 u_int i;
779 uint32_t l1_attr;
780
781 /*
782 * Now, we are going to make real kernel mapping. Note that we are
783 * already running on some mapping made in locore.S and we expect
784 * that it's large enough to ensure nofault access to physical memory
785 * allocated herein before switch.
786 *
787 * As kernel image and everything needed before are and will be mapped
788 * by section mappings, we align last physical address to PTE1_SIZE.
789 */
790 last_paddr = pte1_roundup(last);
791
792 /*
793 * Allocate and zero page(s) for kernel L1 page table.
794 *
795 * Note that it's first allocation on space which was PTE1_SIZE
796 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
797 */
798 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
799 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
800 bzero((void*)kern_pt1, NB_IN_PT1);
801 pte1_sync_range(kern_pt1, NB_IN_PT1);
802
803 /* Allocate and zero page(s) for kernel PT2TAB. */
804 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
805 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
806 bzero(kern_pt2tab, NB_IN_PT2TAB);
807 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
808
809 /* Allocate and zero page(s) for kernel L2 page tables. */
810 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
811 pt2pg_va = KERNEL_P2V(pt2pg_pa);
812 size = NKPT2PG * PAGE_SIZE;
813 bzero((void*)pt2pg_va, size);
814 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
815
816 /*
817 * Add a physical memory segment (vm_phys_seg) corresponding to the
818 * preallocated pages for kernel L2 page tables so that vm_page
819 * structures representing these pages will be created. The vm_page
820 * structures are required for promotion of the corresponding kernel
821 * virtual addresses to section mappings.
822 */
823 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
824
825 /*
826 * Insert allocated L2 page table pages to PT2TAB and make
827 * link to all PT2s in L1 page table. See how kernel_vm_end
828 * is initialized.
829 *
830 * We play simple and safe. So every KVA will have underlaying
831 * L2 page table, even kernel image mapped by sections.
832 */
833 pte2p = kern_pt2tab_entry(KERNBASE);
834 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
835 pt2tab_store(pte2p++, PTE2_KPT(pa));
836
837 pte1p = kern_pte1(KERNBASE);
838 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
839 pte1_store(pte1p++, PTE1_LINK(pa));
840
841 /* Make section mappings for kernel. */
842 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
843 pte1p = kern_pte1(KERNBASE);
844 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
845 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
846
847 /*
848 * Get free and aligned space for PT2MAP and make L1 page table links
849 * to L2 page tables held in PT2TAB.
850 *
851 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
852 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
853 * each entry in PT2TAB maps all PT2s in a page. This implies that
854 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
855 */
856 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
857 pte1p = kern_pte1((vm_offset_t)PT2MAP);
858 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
859 pte1_store(pte1p++, PTE1_LINK(pa));
860 }
861
862 /*
863 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
864 * Each pmap will hold own PT2TAB, so the mapping should be not global.
865 */
866 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
867 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
868 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
869 }
870
871 /*
872 * Choose correct L2 page table and make mappings for allocations
873 * made herein which replaces temporary locore.S mappings after a while.
874 * Note that PT2MAP cannot be used until we switch to kern_pt1.
875 *
876 * Note, that these allocations started aligned on 1M section and
877 * kernel PT1 was allocated first. Making of mappings must follow
878 * order of physical allocations as we've used KERNEL_P2V() macro
879 * for virtual addresses resolution.
880 */
881 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
882 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
883
884 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
885
886 /* Make mapping for kernel L1 page table. */
887 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
888 pte2_store(pte2p++, PTE2_KPT(pa));
889
890 /* Make mapping for kernel PT2TAB. */
891 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
892 pte2_store(pte2p++, PTE2_KPT(pa));
893
894 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
895 pmap_kern_ttb = base_pt1 | ttb_flags;
896 cpuinfo_reinit_mmu(pmap_kern_ttb);
897 /*
898 * Initialize the first available KVA. As kernel image is mapped by
899 * sections, we are leaving some gap behind.
900 */
901 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
902 }
903
904 /*
905 * Setup L2 page table page for given KVA.
906 * Used in pre-bootstrap epoch.
907 *
908 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
909 * and used them for mapping KVA starting from KERNBASE. However, this is not
910 * enough. Vectors and devices need L2 page tables too. Note that they are
911 * even above VM_MAX_KERNEL_ADDRESS.
912 */
913 static __inline vm_paddr_t
pmap_preboot_pt2pg_setup(vm_offset_t va)914 pmap_preboot_pt2pg_setup(vm_offset_t va)
915 {
916 pt2_entry_t *pte2p, pte2;
917 vm_paddr_t pt2pg_pa;
918
919 /* Get associated entry in PT2TAB. */
920 pte2p = kern_pt2tab_entry(va);
921
922 /* Just return, if PT2s page exists already. */
923 pte2 = pt2tab_load(pte2p);
924 if (pte2_is_valid(pte2))
925 return (pte2_pa(pte2));
926
927 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
928 ("%s: NKPT2PG too small", __func__));
929
930 /*
931 * Allocate page for PT2s and insert it to PT2TAB.
932 * In other words, map it into PT2MAP space.
933 */
934 pt2pg_pa = pmap_preboot_get_pages(1);
935 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
936
937 /* Zero all PT2s in allocated page. */
938 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
939 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
940
941 return (pt2pg_pa);
942 }
943
944 /*
945 * Setup L2 page table for given KVA.
946 * Used in pre-bootstrap epoch.
947 */
948 static void
pmap_preboot_pt2_setup(vm_offset_t va)949 pmap_preboot_pt2_setup(vm_offset_t va)
950 {
951 pt1_entry_t *pte1p;
952 vm_paddr_t pt2pg_pa, pt2_pa;
953
954 /* Setup PT2's page. */
955 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
956 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
957
958 /* Insert PT2 to PT1. */
959 pte1p = kern_pte1(va);
960 pte1_store(pte1p, PTE1_LINK(pt2_pa));
961 }
962
963 /*
964 * Get L2 page entry associated with given KVA.
965 * Used in pre-bootstrap epoch.
966 */
967 static __inline pt2_entry_t*
pmap_preboot_vtopte2(vm_offset_t va)968 pmap_preboot_vtopte2(vm_offset_t va)
969 {
970 pt1_entry_t *pte1p;
971
972 /* Setup PT2 if needed. */
973 pte1p = kern_pte1(va);
974 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
975 pmap_preboot_pt2_setup(va);
976
977 return (pt2map_entry(va));
978 }
979
980 /*
981 * Pre-bootstrap epoch page(s) mapping(s).
982 */
983 void
pmap_preboot_map_pages(vm_paddr_t pa,vm_offset_t va,u_int num)984 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
985 {
986 u_int i;
987 pt2_entry_t *pte2p;
988
989 /* Map all the pages. */
990 for (i = 0; i < num; i++) {
991 pte2p = pmap_preboot_vtopte2(va);
992 pte2_store(pte2p, PTE2_KRW(pa));
993 va += PAGE_SIZE;
994 pa += PAGE_SIZE;
995 }
996 }
997
998 /*
999 * Pre-bootstrap epoch virtual space alocator.
1000 */
1001 vm_offset_t
pmap_preboot_reserve_pages(u_int num)1002 pmap_preboot_reserve_pages(u_int num)
1003 {
1004 u_int i;
1005 vm_offset_t start, va;
1006 pt2_entry_t *pte2p;
1007
1008 /* Allocate virtual space. */
1009 start = va = virtual_avail;
1010 virtual_avail += num * PAGE_SIZE;
1011
1012 /* Zero the mapping. */
1013 for (i = 0; i < num; i++) {
1014 pte2p = pmap_preboot_vtopte2(va);
1015 pte2_store(pte2p, 0);
1016 va += PAGE_SIZE;
1017 }
1018
1019 return (start);
1020 }
1021
1022 /*
1023 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1024 */
1025 vm_offset_t
pmap_preboot_get_vpages(u_int num)1026 pmap_preboot_get_vpages(u_int num)
1027 {
1028 vm_paddr_t pa;
1029 vm_offset_t va;
1030
1031 /* Allocate physical page(s). */
1032 pa = pmap_preboot_get_pages(num);
1033
1034 /* Allocate virtual space. */
1035 va = virtual_avail;
1036 virtual_avail += num * PAGE_SIZE;
1037
1038 /* Map and zero all. */
1039 pmap_preboot_map_pages(pa, va, num);
1040 bzero((void *)va, num * PAGE_SIZE);
1041
1042 return (va);
1043 }
1044
1045 /*
1046 * Pre-bootstrap epoch page mapping(s) with attributes.
1047 */
1048 void
pmap_preboot_map_attr(vm_paddr_t pa,vm_offset_t va,vm_size_t size,vm_prot_t prot,vm_memattr_t attr)1049 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1050 vm_prot_t prot, vm_memattr_t attr)
1051 {
1052 u_int num;
1053 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1054 pt1_entry_t *pte1p;
1055 pt2_entry_t *pte2p;
1056
1057 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1058 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1059 l2_attr = vm_memattr_to_pte2(attr);
1060 l1_prot = ATTR_TO_L1(l2_prot);
1061 l1_attr = ATTR_TO_L1(l2_attr);
1062
1063 /* Map all the pages. */
1064 num = round_page(size);
1065 while (num > 0) {
1066 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1067 pte1p = kern_pte1(va);
1068 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1069 va += PTE1_SIZE;
1070 pa += PTE1_SIZE;
1071 num -= PTE1_SIZE;
1072 } else {
1073 pte2p = pmap_preboot_vtopte2(va);
1074 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1075 va += PAGE_SIZE;
1076 pa += PAGE_SIZE;
1077 num -= PAGE_SIZE;
1078 }
1079 }
1080 }
1081
1082 /*
1083 * Extract from the kernel page table the physical address
1084 * that is mapped by the given virtual address "va".
1085 */
1086 vm_paddr_t
pmap_kextract(vm_offset_t va)1087 pmap_kextract(vm_offset_t va)
1088 {
1089 vm_paddr_t pa;
1090 pt1_entry_t pte1;
1091 pt2_entry_t pte2;
1092
1093 pte1 = pte1_load(kern_pte1(va));
1094 if (pte1_is_section(pte1)) {
1095 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1096 } else if (pte1_is_link(pte1)) {
1097 /*
1098 * We should beware of concurrent promotion that changes
1099 * pte1 at this point. However, it's not a problem as PT2
1100 * page is preserved by promotion in PT2TAB. So even if
1101 * it happens, using of PT2MAP is still safe.
1102 *
1103 * QQQ: However, concurrent removing is a problem which
1104 * ends in abort on PT2MAP space. Locking must be used
1105 * to deal with this.
1106 */
1107 pte2 = pte2_load(pt2map_entry(va));
1108 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1109 }
1110 else {
1111 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1112 }
1113 return (pa);
1114 }
1115
1116 /*
1117 * Extract from the kernel page table the physical address
1118 * that is mapped by the given virtual address "va". Also
1119 * return L2 page table entry which maps the address.
1120 *
1121 * This is only intended to be used for panic dumps.
1122 */
1123 vm_paddr_t
pmap_dump_kextract(vm_offset_t va,pt2_entry_t * pte2p)1124 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1125 {
1126 vm_paddr_t pa;
1127 pt1_entry_t pte1;
1128 pt2_entry_t pte2;
1129
1130 pte1 = pte1_load(kern_pte1(va));
1131 if (pte1_is_section(pte1)) {
1132 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1133 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1134 } else if (pte1_is_link(pte1)) {
1135 pte2 = pte2_load(pt2map_entry(va));
1136 pa = pte2_pa(pte2);
1137 } else {
1138 pte2 = 0;
1139 pa = 0;
1140 }
1141 if (pte2p != NULL)
1142 *pte2p = pte2;
1143 return (pa);
1144 }
1145
1146 /*****************************************************************************
1147 *
1148 * PMAP second stage initialization and utility functions
1149 * for bootstrap epoch.
1150 *
1151 * After pmap_bootstrap() is called, the following functions for
1152 * mappings can be used:
1153 *
1154 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1155 * void pmap_kremove(vm_offset_t va);
1156 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1157 * int prot);
1158 *
1159 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1160 * allowed during this stage.
1161 *
1162 *****************************************************************************/
1163
1164 /*
1165 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1166 * reserve various virtual spaces for temporary mappings.
1167 */
1168 void
pmap_bootstrap(vm_offset_t firstaddr)1169 pmap_bootstrap(vm_offset_t firstaddr)
1170 {
1171 pt2_entry_t *unused __unused;
1172 struct pcpu *pc;
1173
1174 /*
1175 * Initialize the kernel pmap (which is statically allocated).
1176 */
1177 PMAP_LOCK_INIT(kernel_pmap);
1178 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1179 kernel_pmap->pm_pt1 = kern_pt1;
1180 kernel_pmap->pm_pt2tab = kern_pt2tab;
1181 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1182 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1183
1184 /*
1185 * Initialize the global pv list lock.
1186 */
1187 rw_init(&pvh_global_lock, "pmap pv global");
1188
1189 LIST_INIT(&allpmaps);
1190
1191 /*
1192 * Request a spin mutex so that changes to allpmaps cannot be
1193 * preempted by smp_rendezvous_cpus().
1194 */
1195 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1196 mtx_lock_spin(&allpmaps_lock);
1197 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1198 mtx_unlock_spin(&allpmaps_lock);
1199
1200 /*
1201 * Reserve some special page table entries/VA space for temporary
1202 * mapping of pages.
1203 */
1204 #define SYSMAP(c, p, v, n) do { \
1205 v = (c)pmap_preboot_reserve_pages(n); \
1206 p = pt2map_entry((vm_offset_t)v); \
1207 } while (0)
1208
1209 /*
1210 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1211 * Local CMAP2 is also used for data cache cleaning.
1212 */
1213 pc = get_pcpu();
1214 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1215 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1216 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1217 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1218
1219 /*
1220 * Crashdump maps.
1221 */
1222 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1223
1224 /*
1225 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1226 */
1227 SYSMAP(caddr_t, unused, _tmppt, 1);
1228
1229 /*
1230 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1231 * respectively. PADDR3 is used by pmap_pte2_ddb().
1232 */
1233 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1234 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1235 #ifdef DDB
1236 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1237 #endif
1238 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1239
1240 /*
1241 * Note that in very short time in initarm(), we are going to
1242 * initialize phys_avail[] array and no further page allocation
1243 * can happen after that until vm subsystem will be initialized.
1244 */
1245 kernel_vm_end_new = kernel_vm_end;
1246 virtual_end = vm_max_kernel_address;
1247 }
1248
1249 static void
pmap_init_reserved_pages(void)1250 pmap_init_reserved_pages(void)
1251 {
1252 struct pcpu *pc;
1253 vm_offset_t pages;
1254 int i;
1255
1256 CPU_FOREACH(i) {
1257 pc = pcpu_find(i);
1258 /*
1259 * Skip if the mapping has already been initialized,
1260 * i.e. this is the BSP.
1261 */
1262 if (pc->pc_cmap1_addr != 0)
1263 continue;
1264 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1265 pages = kva_alloc(PAGE_SIZE * 3);
1266 if (pages == 0)
1267 panic("%s: unable to allocate KVA", __func__);
1268 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1269 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1270 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1271 pc->pc_cmap1_addr = (caddr_t)pages;
1272 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1273 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1274 }
1275 }
1276 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1277
1278 /*
1279 * The function can already be use in second initialization stage.
1280 * As such, the function DOES NOT call pmap_growkernel() where PT2
1281 * allocation can happen. So if used, be sure that PT2 for given
1282 * virtual address is allocated already!
1283 *
1284 * Add a wired page to the kva.
1285 * Note: not SMP coherent.
1286 */
1287 static __inline void
pmap_kenter_prot_attr(vm_offset_t va,vm_paddr_t pa,uint32_t prot,uint32_t attr)1288 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1289 uint32_t attr)
1290 {
1291 pt1_entry_t *pte1p;
1292 pt2_entry_t *pte2p;
1293
1294 pte1p = kern_pte1(va);
1295 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1296 /*
1297 * This is a very low level function, so PT2 and particularly
1298 * PT2PG associated with given virtual address must be already
1299 * allocated. It's a pain mainly during pmap initialization
1300 * stage. However, called after pmap initialization with
1301 * virtual address not under kernel_vm_end will lead to
1302 * the same misery.
1303 */
1304 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1305 panic("%s: kernel PT2 not allocated!", __func__);
1306 }
1307
1308 pte2p = pt2map_entry(va);
1309 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1310 }
1311
1312 PMAP_INLINE void
pmap_kenter(vm_offset_t va,vm_paddr_t pa)1313 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1314 {
1315
1316 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1317 }
1318
1319 /*
1320 * Remove a page from the kernel pagetables.
1321 * Note: not SMP coherent.
1322 */
1323 PMAP_INLINE void
pmap_kremove(vm_offset_t va)1324 pmap_kremove(vm_offset_t va)
1325 {
1326 pt1_entry_t *pte1p;
1327 pt2_entry_t *pte2p;
1328
1329 pte1p = kern_pte1(va);
1330 if (pte1_is_section(pte1_load(pte1p))) {
1331 pte1_clear(pte1p);
1332 } else {
1333 pte2p = pt2map_entry(va);
1334 pte2_clear(pte2p);
1335 }
1336 }
1337
1338 /*
1339 * Share new kernel PT2PG with all pmaps.
1340 * The caller is responsible for maintaining TLB consistency.
1341 */
1342 static void
pmap_kenter_pt2tab(vm_offset_t va,pt2_entry_t npte2)1343 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1344 {
1345 pmap_t pmap;
1346 pt2_entry_t *pte2p;
1347
1348 mtx_lock_spin(&allpmaps_lock);
1349 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1350 pte2p = pmap_pt2tab_entry(pmap, va);
1351 pt2tab_store(pte2p, npte2);
1352 }
1353 mtx_unlock_spin(&allpmaps_lock);
1354 }
1355
1356 /*
1357 * Share new kernel PTE1 with all pmaps.
1358 * The caller is responsible for maintaining TLB consistency.
1359 */
1360 static void
pmap_kenter_pte1(vm_offset_t va,pt1_entry_t npte1)1361 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1362 {
1363 pmap_t pmap;
1364 pt1_entry_t *pte1p;
1365
1366 mtx_lock_spin(&allpmaps_lock);
1367 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1368 pte1p = pmap_pte1(pmap, va);
1369 pte1_store(pte1p, npte1);
1370 }
1371 mtx_unlock_spin(&allpmaps_lock);
1372 }
1373
1374 /*
1375 * Used to map a range of physical addresses into kernel
1376 * virtual address space.
1377 *
1378 * The value passed in '*virt' is a suggested virtual address for
1379 * the mapping. Architectures which can support a direct-mapped
1380 * physical to virtual region can return the appropriate address
1381 * within that region, leaving '*virt' unchanged. Other
1382 * architectures should map the pages starting at '*virt' and
1383 * update '*virt' with the first usable address after the mapped
1384 * region.
1385 *
1386 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1387 * the function is used herein!
1388 */
1389 vm_offset_t
pmap_map(vm_offset_t * virt,vm_paddr_t start,vm_paddr_t end,int prot)1390 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1391 {
1392 vm_offset_t va, sva;
1393 vm_paddr_t pte1_offset;
1394 pt1_entry_t npte1;
1395 uint32_t l1prot, l2prot;
1396 uint32_t l1attr, l2attr;
1397
1398 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1399 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1400
1401 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1402 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1403 l1prot = ATTR_TO_L1(l2prot);
1404
1405 l2attr = PTE2_ATTR_DEFAULT;
1406 l1attr = ATTR_TO_L1(l2attr);
1407
1408 va = *virt;
1409 /*
1410 * Does the physical address range's size and alignment permit at
1411 * least one section mapping to be created?
1412 */
1413 pte1_offset = start & PTE1_OFFSET;
1414 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1415 PTE1_SIZE) {
1416 /*
1417 * Increase the starting virtual address so that its alignment
1418 * does not preclude the use of section mappings.
1419 */
1420 if ((va & PTE1_OFFSET) < pte1_offset)
1421 va = pte1_trunc(va) + pte1_offset;
1422 else if ((va & PTE1_OFFSET) > pte1_offset)
1423 va = pte1_roundup(va) + pte1_offset;
1424 }
1425 sva = va;
1426 while (start < end) {
1427 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1428 KASSERT((va & PTE1_OFFSET) == 0,
1429 ("%s: misaligned va %#x", __func__, va));
1430 npte1 = PTE1_KERN(start, l1prot, l1attr);
1431 pmap_kenter_pte1(va, npte1);
1432 va += PTE1_SIZE;
1433 start += PTE1_SIZE;
1434 } else {
1435 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1436 va += PAGE_SIZE;
1437 start += PAGE_SIZE;
1438 }
1439 }
1440 tlb_flush_range(sva, va - sva);
1441 *virt = va;
1442 return (sva);
1443 }
1444
1445 /*
1446 * Make a temporary mapping for a physical address.
1447 * This is only intended to be used for panic dumps.
1448 */
1449 void *
pmap_kenter_temporary(vm_paddr_t pa,int i)1450 pmap_kenter_temporary(vm_paddr_t pa, int i)
1451 {
1452 vm_offset_t va;
1453
1454 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1455
1456 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1457 pmap_kenter(va, pa);
1458 tlb_flush_local(va);
1459 return ((void *)crashdumpmap);
1460 }
1461
1462 /*************************************
1463 *
1464 * TLB & cache maintenance routines.
1465 *
1466 *************************************/
1467
1468 /*
1469 * We inline these within pmap.c for speed.
1470 */
1471 PMAP_INLINE void
pmap_tlb_flush(pmap_t pmap,vm_offset_t va)1472 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1473 {
1474
1475 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1476 tlb_flush(va);
1477 }
1478
1479 PMAP_INLINE void
pmap_tlb_flush_range(pmap_t pmap,vm_offset_t sva,vm_size_t size)1480 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1481 {
1482
1483 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1484 tlb_flush_range(sva, size);
1485 }
1486
1487 /*
1488 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1489 * Requirements:
1490 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1491 * are ever set, PTE2_V in particular.
1492 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1493 * - Assumes nothing will ever test these addresses for 0 to indicate
1494 * no mapping instead of correctly checking PTE2_V.
1495 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1496 * Because PTE2_V is never set, there can be no mappings to invalidate.
1497 */
1498 static vm_offset_t
pmap_pte2list_alloc(vm_offset_t * head)1499 pmap_pte2list_alloc(vm_offset_t *head)
1500 {
1501 pt2_entry_t *pte2p;
1502 vm_offset_t va;
1503
1504 va = *head;
1505 if (va == 0)
1506 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1507 pte2p = pt2map_entry(va);
1508 *head = *pte2p;
1509 if (*head & PTE2_V)
1510 panic("%s: va with PTE2_V set!", __func__);
1511 *pte2p = 0;
1512 return (va);
1513 }
1514
1515 static void
pmap_pte2list_free(vm_offset_t * head,vm_offset_t va)1516 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1517 {
1518 pt2_entry_t *pte2p;
1519
1520 if (va & PTE2_V)
1521 panic("%s: freeing va with PTE2_V set!", __func__);
1522 pte2p = pt2map_entry(va);
1523 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1524 *head = va;
1525 }
1526
1527 static void
pmap_pte2list_init(vm_offset_t * head,void * base,int npages)1528 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1529 {
1530 int i;
1531 vm_offset_t va;
1532
1533 *head = 0;
1534 for (i = npages - 1; i >= 0; i--) {
1535 va = (vm_offset_t)base + i * PAGE_SIZE;
1536 pmap_pte2list_free(head, va);
1537 }
1538 }
1539
1540 /*****************************************************************************
1541 *
1542 * PMAP third and final stage initialization.
1543 *
1544 * After pmap_init() is called, PMAP subsystem is fully initialized.
1545 *
1546 *****************************************************************************/
1547
1548 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1549 "VM/pmap parameters");
1550
1551 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1552 "Max number of PV entries");
1553 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1554 "Page share factor per proc");
1555
1556 static u_long nkpt2pg = NKPT2PG;
1557 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1558 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1559
1560 static int sp_enabled = 1;
1561 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1562 &sp_enabled, 0, "Are large page mappings enabled?");
1563
1564 bool
pmap_ps_enabled(pmap_t pmap __unused)1565 pmap_ps_enabled(pmap_t pmap __unused)
1566 {
1567
1568 return (sp_enabled != 0);
1569 }
1570
1571 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1572 "1MB page mapping counters");
1573
1574 static u_long pmap_pte1_demotions;
1575 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1576 &pmap_pte1_demotions, 0, "1MB page demotions");
1577
1578 static u_long pmap_pte1_mappings;
1579 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1580 &pmap_pte1_mappings, 0, "1MB page mappings");
1581
1582 static u_long pmap_pte1_p_failures;
1583 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1584 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1585
1586 static u_long pmap_pte1_promotions;
1587 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1588 &pmap_pte1_promotions, 0, "1MB page promotions");
1589
1590 static u_long pmap_pte1_kern_demotions;
1591 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1592 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1593
1594 static u_long pmap_pte1_kern_promotions;
1595 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1596 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1597
1598 static __inline ttb_entry_t
pmap_ttb_get(pmap_t pmap)1599 pmap_ttb_get(pmap_t pmap)
1600 {
1601
1602 return (vtophys(pmap->pm_pt1) | ttb_flags);
1603 }
1604
1605 /*
1606 * Initialize a vm_page's machine-dependent fields.
1607 *
1608 * Variations:
1609 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1610 * pt2_wirecount can share same physical space. However, proper
1611 * initialization on a page alloc for page tables and reinitialization
1612 * on the page free must be ensured.
1613 */
1614 void
pmap_page_init(vm_page_t m)1615 pmap_page_init(vm_page_t m)
1616 {
1617
1618 TAILQ_INIT(&m->md.pv_list);
1619 pt2_wirecount_init(m);
1620 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1621 }
1622
1623 /*
1624 * Virtualization for faster way how to zero whole page.
1625 */
1626 static __inline void
pagezero(void * page)1627 pagezero(void *page)
1628 {
1629
1630 bzero(page, PAGE_SIZE);
1631 }
1632
1633 /*
1634 * Zero L2 page table page.
1635 * Use same KVA as in pmap_zero_page().
1636 */
1637 static __inline vm_paddr_t
pmap_pt2pg_zero(vm_page_t m)1638 pmap_pt2pg_zero(vm_page_t m)
1639 {
1640 pt2_entry_t *cmap2_pte2p;
1641 vm_paddr_t pa;
1642 struct pcpu *pc;
1643
1644 pa = VM_PAGE_TO_PHYS(m);
1645
1646 /*
1647 * XXX: For now, we map whole page even if it's already zero,
1648 * to sync it even if the sync is only DSB.
1649 */
1650 sched_pin();
1651 pc = get_pcpu();
1652 cmap2_pte2p = pc->pc_cmap2_pte2p;
1653 mtx_lock(&pc->pc_cmap_lock);
1654 if (pte2_load(cmap2_pte2p) != 0)
1655 panic("%s: CMAP2 busy", __func__);
1656 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1657 vm_page_pte2_attr(m)));
1658 /* Even VM_ALLOC_ZERO request is only advisory. */
1659 if ((m->flags & PG_ZERO) == 0)
1660 pagezero(pc->pc_cmap2_addr);
1661 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1662 pte2_clear(cmap2_pte2p);
1663 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1664
1665 /*
1666 * Unpin the thread before releasing the lock. Otherwise the thread
1667 * could be rescheduled while still bound to the current CPU, only
1668 * to unpin itself immediately upon resuming execution.
1669 */
1670 sched_unpin();
1671 mtx_unlock(&pc->pc_cmap_lock);
1672
1673 return (pa);
1674 }
1675
1676 /*
1677 * Init just allocated page as L2 page table(s) holder
1678 * and return its physical address.
1679 */
1680 static __inline vm_paddr_t
pmap_pt2pg_init(pmap_t pmap,vm_offset_t va,vm_page_t m)1681 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1682 {
1683 vm_paddr_t pa;
1684 pt2_entry_t *pte2p;
1685
1686 /* Check page attributes. */
1687 if (m->md.pat_mode != pt_memattr)
1688 pmap_page_set_memattr(m, pt_memattr);
1689
1690 /* Zero page and init wire counts. */
1691 pa = pmap_pt2pg_zero(m);
1692 pt2_wirecount_init(m);
1693
1694 /*
1695 * Map page to PT2MAP address space for given pmap.
1696 * Note that PT2MAP space is shared with all pmaps.
1697 */
1698 if (pmap == kernel_pmap)
1699 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1700 else {
1701 pte2p = pmap_pt2tab_entry(pmap, va);
1702 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1703 }
1704
1705 return (pa);
1706 }
1707
1708 /*
1709 * Initialize the pmap module.
1710 *
1711 * Called by vm_mem_init(), to initialize any structures that the pmap system
1712 * needs to map virtual memory.
1713 */
1714 void
pmap_init(void)1715 pmap_init(void)
1716 {
1717 vm_size_t s;
1718 pt2_entry_t *pte2p, pte2;
1719 u_int i, pte1_idx, pv_npg;
1720
1721 PDEBUG(1, printf("%s: phys_start = %#x\n", __func__, PHYSADDR));
1722
1723 /*
1724 * Initialize the vm page array entries for kernel pmap's
1725 * L2 page table pages allocated in advance.
1726 */
1727 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1728 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1729 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1730 vm_paddr_t pa;
1731 vm_page_t m;
1732
1733 pte2 = pte2_load(pte2p);
1734 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1735
1736 pa = pte2_pa(pte2);
1737 m = PHYS_TO_VM_PAGE(pa);
1738 KASSERT(m >= vm_page_array &&
1739 m < &vm_page_array[vm_page_array_size],
1740 ("%s: L2 page table page is out of range", __func__));
1741
1742 m->pindex = pte1_idx;
1743 m->phys_addr = pa;
1744 pte1_idx += NPT2_IN_PG;
1745 }
1746
1747 /*
1748 * Initialize the address space (zone) for the pv entries. Set a
1749 * high water mark so that the system can recover from excessive
1750 * numbers of pv entries.
1751 */
1752 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1753 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1754 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max);
1755 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1756 pv_entry_high_water = 9 * (pv_entry_max / 10);
1757
1758 /*
1759 * Are large page mappings enabled?
1760 */
1761 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1762 if (sp_enabled) {
1763 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1764 ("%s: can't assign to pagesizes[1]", __func__));
1765 pagesizes[1] = PTE1_SIZE;
1766 }
1767
1768 /*
1769 * Calculate the size of the pv head table for sections.
1770 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1771 * Note that the table is only for sections which could be promoted.
1772 */
1773 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1774 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1775 - first_managed_pa) / PTE1_SIZE + 1;
1776
1777 /*
1778 * Allocate memory for the pv head table for sections.
1779 */
1780 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1781 s = round_page(s);
1782 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO);
1783 for (i = 0; i < pv_npg; i++)
1784 TAILQ_INIT(&pv_table[i].pv_list);
1785
1786 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1787 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1788 if (pv_chunkbase == NULL)
1789 panic("%s: not enough kvm for pv chunks", __func__);
1790 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1791 }
1792
1793 /*
1794 * Add a list of wired pages to the kva
1795 * this routine is only used for temporary
1796 * kernel mappings that do not need to have
1797 * page modification or references recorded.
1798 * Note that old mappings are simply written
1799 * over. The page *must* be wired.
1800 * Note: SMP coherent. Uses a ranged shootdown IPI.
1801 */
1802 void
pmap_qenter(vm_offset_t sva,vm_page_t * ma,int count)1803 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1804 {
1805 u_int anychanged;
1806 pt2_entry_t *epte2p, *pte2p, pte2;
1807 vm_page_t m;
1808 vm_paddr_t pa;
1809
1810 anychanged = 0;
1811 pte2p = pt2map_entry(sva);
1812 epte2p = pte2p + count;
1813 while (pte2p < epte2p) {
1814 m = *ma++;
1815 pa = VM_PAGE_TO_PHYS(m);
1816 pte2 = pte2_load(pte2p);
1817 if ((pte2_pa(pte2) != pa) ||
1818 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1819 anychanged++;
1820 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1821 vm_page_pte2_attr(m)));
1822 }
1823 pte2p++;
1824 }
1825 if (__predict_false(anychanged))
1826 tlb_flush_range(sva, count * PAGE_SIZE);
1827 }
1828
1829 /*
1830 * This routine tears out page mappings from the
1831 * kernel -- it is meant only for temporary mappings.
1832 * Note: SMP coherent. Uses a ranged shootdown IPI.
1833 */
1834 void
pmap_qremove(vm_offset_t sva,int count)1835 pmap_qremove(vm_offset_t sva, int count)
1836 {
1837 vm_offset_t va;
1838
1839 va = sva;
1840 while (count-- > 0) {
1841 pmap_kremove(va);
1842 va += PAGE_SIZE;
1843 }
1844 tlb_flush_range(sva, va - sva);
1845 }
1846
1847 /*
1848 * Are we current address space or kernel?
1849 */
1850 static __inline int
pmap_is_current(pmap_t pmap)1851 pmap_is_current(pmap_t pmap)
1852 {
1853
1854 return (pmap == kernel_pmap ||
1855 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1856 }
1857
1858 /*
1859 * If the given pmap is not the current or kernel pmap, the returned
1860 * pte2 must be released by passing it to pmap_pte2_release().
1861 */
1862 static pt2_entry_t *
pmap_pte2(pmap_t pmap,vm_offset_t va)1863 pmap_pte2(pmap_t pmap, vm_offset_t va)
1864 {
1865 pt1_entry_t pte1;
1866 vm_paddr_t pt2pg_pa;
1867
1868 pte1 = pte1_load(pmap_pte1(pmap, va));
1869 if (pte1_is_section(pte1))
1870 panic("%s: attempt to map PTE1", __func__);
1871 if (pte1_is_link(pte1)) {
1872 /* Are we current address space or kernel? */
1873 if (pmap_is_current(pmap))
1874 return (pt2map_entry(va));
1875 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1876 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1877 mtx_lock(&PMAP2mutex);
1878 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1879 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1880 tlb_flush((vm_offset_t)PADDR2);
1881 }
1882 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1883 }
1884 return (NULL);
1885 }
1886
1887 /*
1888 * Releases a pte2 that was obtained from pmap_pte2().
1889 * Be prepared for the pte2p being NULL.
1890 */
1891 static __inline void
pmap_pte2_release(pt2_entry_t * pte2p)1892 pmap_pte2_release(pt2_entry_t *pte2p)
1893 {
1894
1895 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1896 mtx_unlock(&PMAP2mutex);
1897 }
1898 }
1899
1900 /*
1901 * Super fast pmap_pte2 routine best used when scanning
1902 * the pv lists. This eliminates many coarse-grained
1903 * invltlb calls. Note that many of the pv list
1904 * scans are across different pmaps. It is very wasteful
1905 * to do an entire tlb flush for checking a single mapping.
1906 *
1907 * If the given pmap is not the current pmap, pvh_global_lock
1908 * must be held and curthread pinned to a CPU.
1909 */
1910 static pt2_entry_t *
pmap_pte2_quick(pmap_t pmap,vm_offset_t va)1911 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1912 {
1913 pt1_entry_t pte1;
1914 vm_paddr_t pt2pg_pa;
1915
1916 pte1 = pte1_load(pmap_pte1(pmap, va));
1917 if (pte1_is_section(pte1))
1918 panic("%s: attempt to map PTE1", __func__);
1919 if (pte1_is_link(pte1)) {
1920 /* Are we current address space or kernel? */
1921 if (pmap_is_current(pmap))
1922 return (pt2map_entry(va));
1923 rw_assert(&pvh_global_lock, RA_WLOCKED);
1924 KASSERT(curthread->td_pinned > 0,
1925 ("%s: curthread not pinned", __func__));
1926 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1927 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1928 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1929 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1930 #ifdef SMP
1931 PMAP1cpu = PCPU_GET(cpuid);
1932 #endif
1933 tlb_flush_local((vm_offset_t)PADDR1);
1934 PMAP1changed++;
1935 } else
1936 #ifdef SMP
1937 if (PMAP1cpu != PCPU_GET(cpuid)) {
1938 PMAP1cpu = PCPU_GET(cpuid);
1939 tlb_flush_local((vm_offset_t)PADDR1);
1940 PMAP1changedcpu++;
1941 } else
1942 #endif
1943 PMAP1unchanged++;
1944 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1945 }
1946 return (NULL);
1947 }
1948
1949 /*
1950 * Routine: pmap_extract
1951 * Function:
1952 * Extract the physical page address associated
1953 * with the given map/virtual_address pair.
1954 */
1955 vm_paddr_t
pmap_extract(pmap_t pmap,vm_offset_t va)1956 pmap_extract(pmap_t pmap, vm_offset_t va)
1957 {
1958 vm_paddr_t pa;
1959 pt1_entry_t pte1;
1960 pt2_entry_t *pte2p;
1961
1962 PMAP_LOCK(pmap);
1963 pte1 = pte1_load(pmap_pte1(pmap, va));
1964 if (pte1_is_section(pte1))
1965 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1966 else if (pte1_is_link(pte1)) {
1967 pte2p = pmap_pte2(pmap, va);
1968 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1969 pmap_pte2_release(pte2p);
1970 } else
1971 pa = 0;
1972 PMAP_UNLOCK(pmap);
1973 return (pa);
1974 }
1975
1976 /*
1977 * Routine: pmap_extract_and_hold
1978 * Function:
1979 * Atomically extract and hold the physical page
1980 * with the given pmap and virtual address pair
1981 * if that mapping permits the given protection.
1982 */
1983 vm_page_t
pmap_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)1984 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1985 {
1986 vm_paddr_t pa;
1987 pt1_entry_t pte1;
1988 pt2_entry_t pte2, *pte2p;
1989 vm_page_t m;
1990
1991 m = NULL;
1992 PMAP_LOCK(pmap);
1993 pte1 = pte1_load(pmap_pte1(pmap, va));
1994 if (pte1_is_section(pte1)) {
1995 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1996 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1997 m = PHYS_TO_VM_PAGE(pa);
1998 if (!vm_page_wire_mapped(m))
1999 m = NULL;
2000 }
2001 } else if (pte1_is_link(pte1)) {
2002 pte2p = pmap_pte2(pmap, va);
2003 pte2 = pte2_load(pte2p);
2004 pmap_pte2_release(pte2p);
2005 if (pte2_is_valid(pte2) &&
2006 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
2007 pa = pte2_pa(pte2);
2008 m = PHYS_TO_VM_PAGE(pa);
2009 if (!vm_page_wire_mapped(m))
2010 m = NULL;
2011 }
2012 }
2013 PMAP_UNLOCK(pmap);
2014 return (m);
2015 }
2016
2017 /*
2018 * Grow the number of kernel L2 page table entries, if needed.
2019 */
2020 void
pmap_growkernel(vm_offset_t addr)2021 pmap_growkernel(vm_offset_t addr)
2022 {
2023 vm_page_t m;
2024 vm_paddr_t pt2pg_pa, pt2_pa;
2025 pt1_entry_t pte1;
2026 pt2_entry_t pte2;
2027
2028 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2029 /*
2030 * All the time kernel_vm_end is first KVA for which underlying
2031 * L2 page table is either not allocated or linked from L1 page table
2032 * (not considering sections). Except for two possible cases:
2033 *
2034 * (1) in the very beginning as long as pmap_growkernel() was
2035 * not called, it could be first unused KVA (which is not
2036 * rounded up to PTE1_SIZE),
2037 *
2038 * (2) when all KVA space is mapped and vm_map_max(kernel_map)
2039 * address is not rounded up to PTE1_SIZE. (For example,
2040 * it could be 0xFFFFFFFF.)
2041 */
2042 kernel_vm_end = pte1_roundup(kernel_vm_end);
2043 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2044 addr = roundup2(addr, PTE1_SIZE);
2045 if (addr - 1 >= vm_map_max(kernel_map))
2046 addr = vm_map_max(kernel_map);
2047 while (kernel_vm_end < addr) {
2048 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2049 if (pte1_is_valid(pte1)) {
2050 kernel_vm_end += PTE1_SIZE;
2051 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2052 kernel_vm_end = vm_map_max(kernel_map);
2053 break;
2054 }
2055 continue;
2056 }
2057
2058 /*
2059 * kernel_vm_end_new is used in pmap_pinit() when kernel
2060 * mappings are entered to new pmap all at once to avoid race
2061 * between pmap_kenter_pte1() and kernel_vm_end increase.
2062 * The same aplies to pmap_kenter_pt2tab().
2063 */
2064 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2065
2066 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2067 if (!pte2_is_valid(pte2)) {
2068 /*
2069 * Install new PT2s page into kernel PT2TAB.
2070 */
2071 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2072 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2073 if (m == NULL)
2074 panic("%s: no memory to grow kernel", __func__);
2075 m->pindex = pte1_index(kernel_vm_end) & ~PT2PG_MASK;
2076
2077 /*
2078 * QQQ: To link all new L2 page tables from L1 page
2079 * table now and so pmap_kenter_pte1() them
2080 * at once together with pmap_kenter_pt2tab()
2081 * could be nice speed up. However,
2082 * pmap_growkernel() does not happen so often...
2083 * QQQ: The other TTBR is another option.
2084 */
2085 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2086 m);
2087 } else
2088 pt2pg_pa = pte2_pa(pte2);
2089
2090 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2091 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2092
2093 kernel_vm_end = kernel_vm_end_new;
2094 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2095 kernel_vm_end = vm_map_max(kernel_map);
2096 break;
2097 }
2098 }
2099 }
2100
2101 static int
kvm_size(SYSCTL_HANDLER_ARGS)2102 kvm_size(SYSCTL_HANDLER_ARGS)
2103 {
2104 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2105
2106 return (sysctl_handle_long(oidp, &ksize, 0, req));
2107 }
2108 SYSCTL_PROC(_vm, OID_AUTO, kvm_size,
2109 CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 0, 0, kvm_size, "IU",
2110 "Size of KVM");
2111
2112 static int
kvm_free(SYSCTL_HANDLER_ARGS)2113 kvm_free(SYSCTL_HANDLER_ARGS)
2114 {
2115 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2116
2117 return (sysctl_handle_long(oidp, &kfree, 0, req));
2118 }
2119 SYSCTL_PROC(_vm, OID_AUTO, kvm_free,
2120 CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 0, 0, kvm_free, "IU",
2121 "Amount of KVM free");
2122
2123 /***********************************************
2124 *
2125 * Pmap allocation/deallocation routines.
2126 *
2127 ***********************************************/
2128
2129 /*
2130 * Initialize the pmap for the swapper process.
2131 */
2132 void
pmap_pinit0(pmap_t pmap)2133 pmap_pinit0(pmap_t pmap)
2134 {
2135 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2136
2137 PMAP_LOCK_INIT(pmap);
2138
2139 /*
2140 * Kernel page table directory and pmap stuff around is already
2141 * initialized, we are using it right now and here. So, finish
2142 * only PMAP structures initialization for process0 ...
2143 *
2144 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2145 * which is already included in the list "allpmaps", this pmap does
2146 * not need to be inserted into that list.
2147 */
2148 pmap->pm_pt1 = kern_pt1;
2149 pmap->pm_pt2tab = kern_pt2tab;
2150 CPU_ZERO(&pmap->pm_active);
2151 PCPU_SET(curpmap, pmap);
2152 TAILQ_INIT(&pmap->pm_pvchunk);
2153 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2154 CPU_SET(0, &pmap->pm_active);
2155 }
2156
2157 static __inline void
pte1_copy_nosync(pt1_entry_t * spte1p,pt1_entry_t * dpte1p,vm_offset_t sva,vm_offset_t eva)2158 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2159 vm_offset_t eva)
2160 {
2161 u_int idx, count;
2162
2163 idx = pte1_index(sva);
2164 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2165 bcopy(spte1p + idx, dpte1p + idx, count);
2166 }
2167
2168 static __inline void
pt2tab_copy_nosync(pt2_entry_t * spte2p,pt2_entry_t * dpte2p,vm_offset_t sva,vm_offset_t eva)2169 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2170 vm_offset_t eva)
2171 {
2172 u_int idx, count;
2173
2174 idx = pt2tab_index(sva);
2175 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2176 bcopy(spte2p + idx, dpte2p + idx, count);
2177 }
2178
2179 /*
2180 * Initialize a preallocated and zeroed pmap structure,
2181 * such as one in a vmspace structure.
2182 */
2183 int
pmap_pinit(pmap_t pmap)2184 pmap_pinit(pmap_t pmap)
2185 {
2186 pt1_entry_t *pte1p;
2187 pt2_entry_t *pte2p;
2188 vm_paddr_t pa, pt2tab_pa;
2189 u_int i;
2190
2191 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2192 pmap->pm_pt1));
2193
2194 /*
2195 * No need to allocate L2 page table space yet but we do need
2196 * a valid L1 page table and PT2TAB table.
2197 *
2198 * Install shared kernel mappings to these tables. It's a little
2199 * tricky as some parts of KVA are reserved for vectors, devices,
2200 * and whatever else. These parts are supposed to be above
2201 * vm_max_kernel_address. Thus two regions should be installed:
2202 *
2203 * (1) <KERNBASE, kernel_vm_end),
2204 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2205 *
2206 * QQQ: The second region should be stable enough to be installed
2207 * only once in time when the tables are allocated.
2208 * QQQ: Maybe copy of both regions at once could be faster ...
2209 * QQQ: Maybe the other TTBR is an option.
2210 *
2211 * Finally, install own PT2TAB table to these tables.
2212 */
2213
2214 if (pmap->pm_pt1 == NULL) {
2215 pmap->pm_pt1 = kmem_alloc_contig(NB_IN_PT1,
2216 M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0, pt_memattr);
2217 if (pmap->pm_pt1 == NULL)
2218 return (0);
2219 }
2220 if (pmap->pm_pt2tab == NULL) {
2221 /*
2222 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2223 * only, what should be the only size for 32 bit systems,
2224 * then we could allocate it with vm_page_alloc() and all
2225 * the stuff needed as other L2 page table pages.
2226 * (2) Note that a process PT2TAB is special L2 page table
2227 * page. Its mapping in kernel_arena is permanent and can
2228 * be used no matter which process is current. Its mapping
2229 * in PT2MAP can be used only for current process.
2230 */
2231 pmap->pm_pt2tab = kmem_alloc_attr(NB_IN_PT2TAB,
2232 M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2233 if (pmap->pm_pt2tab == NULL) {
2234 /*
2235 * QQQ: As struct pmap is allocated from UMA with
2236 * UMA_ZONE_NOFREE flag, it's important to leave
2237 * no allocation in pmap if initialization failed.
2238 */
2239 kmem_free(pmap->pm_pt1, NB_IN_PT1);
2240 pmap->pm_pt1 = NULL;
2241 return (0);
2242 }
2243 /*
2244 * QQQ: Each L2 page table page vm_page_t has pindex set to
2245 * pte1 index of virtual address mapped by this page.
2246 * It's not valid for non kernel PT2TABs themselves.
2247 * The pindex of these pages can not be altered because
2248 * of the way how they are allocated now. However, it
2249 * should not be a problem.
2250 */
2251 }
2252
2253 mtx_lock_spin(&allpmaps_lock);
2254 /*
2255 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2256 * kernel_vm_end_new is used here instead of kernel_vm_end.
2257 */
2258 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2259 kernel_vm_end_new - 1);
2260 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2261 0xFFFFFFFF);
2262 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2263 kernel_vm_end_new - 1);
2264 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2265 0xFFFFFFFF);
2266 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2267 mtx_unlock_spin(&allpmaps_lock);
2268
2269 /*
2270 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2271 * I.e. self reference mapping. The PT2TAB is private, however mapped
2272 * into shared PT2MAP space, so the mapping should be not global.
2273 */
2274 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2275 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2276 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2277 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2278 }
2279
2280 /* Insert PT2MAP PT2s into pmap PT1. */
2281 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2282 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2283 pte1_store(pte1p++, PTE1_LINK(pa));
2284 }
2285
2286 /*
2287 * Now synchronize new mapping which was made above.
2288 */
2289 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2290 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2291
2292 CPU_ZERO(&pmap->pm_active);
2293 TAILQ_INIT(&pmap->pm_pvchunk);
2294 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2295
2296 return (1);
2297 }
2298
2299 #ifdef INVARIANTS
2300 static boolean_t
pt2tab_user_is_empty(pt2_entry_t * tab)2301 pt2tab_user_is_empty(pt2_entry_t *tab)
2302 {
2303 u_int i, end;
2304
2305 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2306 for (i = 0; i < end; i++)
2307 if (tab[i] != 0) return (FALSE);
2308 return (TRUE);
2309 }
2310 #endif
2311 /*
2312 * Release any resources held by the given physical map.
2313 * Called when a pmap initialized by pmap_pinit is being released.
2314 * Should only be called if the map contains no valid mappings.
2315 */
2316 void
pmap_release(pmap_t pmap)2317 pmap_release(pmap_t pmap)
2318 {
2319 #ifdef INVARIANTS
2320 vm_offset_t start, end;
2321 #endif
2322 KASSERT(pmap->pm_stats.resident_count == 0,
2323 ("%s: pmap resident count %ld != 0", __func__,
2324 pmap->pm_stats.resident_count));
2325 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2326 ("%s: has allocated user PT2(s)", __func__));
2327 KASSERT(CPU_EMPTY(&pmap->pm_active),
2328 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2329
2330 mtx_lock_spin(&allpmaps_lock);
2331 LIST_REMOVE(pmap, pm_list);
2332 mtx_unlock_spin(&allpmaps_lock);
2333
2334 #ifdef INVARIANTS
2335 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2336 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2337 bzero((char *)pmap->pm_pt1 + start, end - start);
2338
2339 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2340 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2341 bzero((char *)pmap->pm_pt2tab + start, end - start);
2342 #endif
2343 /*
2344 * We are leaving PT1 and PT2TAB allocated on released pmap,
2345 * so hopefully UMA vmspace_zone will always be inited with
2346 * UMA_ZONE_NOFREE flag.
2347 */
2348 }
2349
2350 /*********************************************************
2351 *
2352 * L2 table pages and their pages management routines.
2353 *
2354 *********************************************************/
2355
2356 /*
2357 * Virtual interface for L2 page table wire counting.
2358 *
2359 * Each L2 page table in a page has own counter which counts a number of
2360 * valid mappings in a table. Global page counter counts mappings in all
2361 * tables in a page plus a single itself mapping in PT2TAB.
2362 *
2363 * During a promotion we leave the associated L2 page table counter
2364 * untouched, so the table (strictly speaking a page which holds it)
2365 * is never freed if promoted.
2366 *
2367 * If a page m->ref_count == 1 then no valid mappings exist in any L2 page
2368 * table in the page and the page itself is only mapped in PT2TAB.
2369 */
2370
2371 static __inline void
pt2_wirecount_init(vm_page_t m)2372 pt2_wirecount_init(vm_page_t m)
2373 {
2374 u_int i;
2375
2376 /*
2377 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2378 * m->ref_count should be already set correctly.
2379 * So, there is no need to set it again herein.
2380 */
2381 for (i = 0; i < NPT2_IN_PG; i++)
2382 m->md.pt2_wirecount[i] = 0;
2383 }
2384
2385 static __inline void
pt2_wirecount_inc(vm_page_t m,uint32_t pte1_idx)2386 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2387 {
2388
2389 /*
2390 * Note: A just modificated pte2 (i.e. already allocated)
2391 * is acquiring one extra reference which must be
2392 * explicitly cleared. It influences the KASSERTs herein.
2393 * All L2 page tables in a page always belong to the same
2394 * pmap, so we allow only one extra reference for the page.
2395 */
2396 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2397 ("%s: PT2 is overflowing ...", __func__));
2398 KASSERT(m->ref_count <= (NPTE2_IN_PG + 1),
2399 ("%s: PT2PG is overflowing ...", __func__));
2400
2401 m->ref_count++;
2402 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2403 }
2404
2405 static __inline void
pt2_wirecount_dec(vm_page_t m,uint32_t pte1_idx)2406 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2407 {
2408
2409 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2410 ("%s: PT2 is underflowing ...", __func__));
2411 KASSERT(m->ref_count > 1,
2412 ("%s: PT2PG is underflowing ...", __func__));
2413
2414 m->ref_count--;
2415 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2416 }
2417
2418 static __inline void
pt2_wirecount_set(vm_page_t m,uint32_t pte1_idx,uint16_t count)2419 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2420 {
2421
2422 KASSERT(count <= NPTE2_IN_PT2,
2423 ("%s: invalid count %u", __func__, count));
2424 KASSERT(m->ref_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2425 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->ref_count,
2426 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2427
2428 m->ref_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2429 m->ref_count += count;
2430 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2431
2432 KASSERT(m->ref_count <= (NPTE2_IN_PG + 1),
2433 ("%s: PT2PG is overflowed (%u) ...", __func__, m->ref_count));
2434 }
2435
2436 static __inline uint32_t
pt2_wirecount_get(vm_page_t m,uint32_t pte1_idx)2437 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2438 {
2439
2440 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2441 }
2442
2443 static __inline boolean_t
pt2_is_empty(vm_page_t m,vm_offset_t va)2444 pt2_is_empty(vm_page_t m, vm_offset_t va)
2445 {
2446
2447 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2448 }
2449
2450 static __inline boolean_t
pt2_is_full(vm_page_t m,vm_offset_t va)2451 pt2_is_full(vm_page_t m, vm_offset_t va)
2452 {
2453
2454 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2455 NPTE2_IN_PT2);
2456 }
2457
2458 static __inline boolean_t
pt2pg_is_empty(vm_page_t m)2459 pt2pg_is_empty(vm_page_t m)
2460 {
2461
2462 return (m->ref_count == 1);
2463 }
2464
2465 /*
2466 * This routine is called if the L2 page table
2467 * is not mapped correctly.
2468 */
2469 static vm_page_t
_pmap_allocpte2(pmap_t pmap,vm_offset_t va,u_int flags)2470 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2471 {
2472 uint32_t pte1_idx;
2473 pt1_entry_t *pte1p;
2474 pt2_entry_t pte2;
2475 vm_page_t m;
2476 vm_paddr_t pt2pg_pa, pt2_pa;
2477
2478 pte1_idx = pte1_index(va);
2479 pte1p = pmap->pm_pt1 + pte1_idx;
2480
2481 KASSERT(pte1_load(pte1p) == 0,
2482 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2483 pte1_load(pte1p)));
2484
2485 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2486 if (!pte2_is_valid(pte2)) {
2487 /*
2488 * Install new PT2s page into pmap PT2TAB.
2489 */
2490 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2491 if (m == NULL) {
2492 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2493 PMAP_UNLOCK(pmap);
2494 rw_wunlock(&pvh_global_lock);
2495 vm_wait(NULL);
2496 rw_wlock(&pvh_global_lock);
2497 PMAP_LOCK(pmap);
2498 }
2499
2500 /*
2501 * Indicate the need to retry. While waiting,
2502 * the L2 page table page may have been allocated.
2503 */
2504 return (NULL);
2505 }
2506 m->pindex = pte1_idx & ~PT2PG_MASK;
2507 pmap->pm_stats.resident_count++;
2508 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2509 } else {
2510 pt2pg_pa = pte2_pa(pte2);
2511 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2512 }
2513
2514 pt2_wirecount_inc(m, pte1_idx);
2515 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2516 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2517
2518 return (m);
2519 }
2520
2521 static vm_page_t
pmap_allocpte2(pmap_t pmap,vm_offset_t va,u_int flags)2522 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2523 {
2524 u_int pte1_idx;
2525 pt1_entry_t *pte1p, pte1;
2526 vm_page_t m;
2527
2528 pte1_idx = pte1_index(va);
2529 retry:
2530 pte1p = pmap->pm_pt1 + pte1_idx;
2531 pte1 = pte1_load(pte1p);
2532
2533 /*
2534 * This supports switching from a 1MB page to a
2535 * normal 4K page.
2536 */
2537 if (pte1_is_section(pte1)) {
2538 (void)pmap_demote_pte1(pmap, pte1p, va);
2539 /*
2540 * Reload pte1 after demotion.
2541 *
2542 * Note: Demotion can even fail as either PT2 is not find for
2543 * the virtual address or PT2PG can not be allocated.
2544 */
2545 pte1 = pte1_load(pte1p);
2546 }
2547
2548 /*
2549 * If the L2 page table page is mapped, we just increment the
2550 * hold count, and activate it.
2551 */
2552 if (pte1_is_link(pte1)) {
2553 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2554 pt2_wirecount_inc(m, pte1_idx);
2555 } else {
2556 /*
2557 * Here if the PT2 isn't mapped, or if it has
2558 * been deallocated.
2559 */
2560 m = _pmap_allocpte2(pmap, va, flags);
2561 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2562 goto retry;
2563 }
2564
2565 return (m);
2566 }
2567
2568 /*
2569 * Schedule the specified unused L2 page table page to be freed. Specifically,
2570 * add the page to the specified list of pages that will be released to the
2571 * physical memory manager after the TLB has been updated.
2572 */
2573 static __inline void
pmap_add_delayed_free_list(vm_page_t m,struct spglist * free)2574 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2575 {
2576
2577 /*
2578 * Put page on a list so that it is released after
2579 * *ALL* TLB shootdown is done
2580 */
2581 #ifdef PMAP_DEBUG
2582 pmap_zero_page_check(m);
2583 #endif
2584 m->flags |= PG_ZERO;
2585 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2586 }
2587
2588 /*
2589 * Unwire L2 page tables page.
2590 */
2591 static void
pmap_unwire_pt2pg(pmap_t pmap,vm_offset_t va,vm_page_t m)2592 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2593 {
2594 pt1_entry_t *pte1p, opte1 __unused;
2595 pt2_entry_t *pte2p;
2596 uint32_t i;
2597
2598 KASSERT(pt2pg_is_empty(m),
2599 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2600
2601 /*
2602 * Unmap all L2 page tables in the page from L1 page table.
2603 *
2604 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2605 * earlier. However, we are doing that this way.
2606 */
2607 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2608 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2609 pte1p = pmap->pm_pt1 + m->pindex;
2610 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2611 KASSERT(m->md.pt2_wirecount[i] == 0,
2612 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2613 opte1 = pte1_load(pte1p);
2614 if (pte1_is_link(opte1)) {
2615 pte1_clear(pte1p);
2616 /*
2617 * Flush intermediate TLB cache.
2618 */
2619 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2620 }
2621 #ifdef INVARIANTS
2622 else
2623 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2624 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2625 pmap, va, opte1, i));
2626 #endif
2627 }
2628
2629 /*
2630 * Unmap the page from PT2TAB.
2631 */
2632 pte2p = pmap_pt2tab_entry(pmap, va);
2633 (void)pt2tab_load_clear(pte2p);
2634 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2635
2636 m->ref_count = 0;
2637 pmap->pm_stats.resident_count--;
2638
2639 /*
2640 * This barrier is so that the ordinary store unmapping
2641 * the L2 page table page is globally performed before TLB shoot-
2642 * down is begun.
2643 */
2644 wmb();
2645 vm_wire_sub(1);
2646 }
2647
2648 /*
2649 * Decrements a L2 page table page's wire count, which is used to record the
2650 * number of valid page table entries within the page. If the wire count
2651 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2652 * page table page was unmapped and FALSE otherwise.
2653 */
2654 static __inline boolean_t
pmap_unwire_pt2(pmap_t pmap,vm_offset_t va,vm_page_t m,struct spglist * free)2655 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2656 {
2657 pt2_wirecount_dec(m, pte1_index(va));
2658 if (pt2pg_is_empty(m)) {
2659 /*
2660 * QQQ: Wire count is zero, so whole page should be zero and
2661 * we can set PG_ZERO flag to it.
2662 * Note that when promotion is enabled, it takes some
2663 * more efforts. See pmap_unwire_pt2_all() below.
2664 */
2665 pmap_unwire_pt2pg(pmap, va, m);
2666 pmap_add_delayed_free_list(m, free);
2667 return (TRUE);
2668 } else
2669 return (FALSE);
2670 }
2671
2672 /*
2673 * Drop a L2 page table page's wire count at once, which is used to record
2674 * the number of valid L2 page table entries within the page. If the wire
2675 * count drops to zero, then the L2 page table page is unmapped.
2676 */
2677 static __inline void
pmap_unwire_pt2_all(pmap_t pmap,vm_offset_t va,vm_page_t m,struct spglist * free)2678 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2679 struct spglist *free)
2680 {
2681 u_int pte1_idx = pte1_index(va);
2682
2683 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2684 ("%s: PT2 page's pindex is wrong", __func__));
2685 KASSERT(m->ref_count > pt2_wirecount_get(m, pte1_idx),
2686 ("%s: bad pt2 wire count %u > %u", __func__, m->ref_count,
2687 pt2_wirecount_get(m, pte1_idx)));
2688
2689 /*
2690 * It's possible that the L2 page table was never used.
2691 * It happened in case that a section was created without promotion.
2692 */
2693 if (pt2_is_full(m, va)) {
2694 pt2_wirecount_set(m, pte1_idx, 0);
2695
2696 /*
2697 * QQQ: We clear L2 page table now, so when L2 page table page
2698 * is going to be freed, we can set it PG_ZERO flag ...
2699 * This function is called only on section mappings, so
2700 * hopefully it's not to big overload.
2701 *
2702 * XXX: If pmap is current, existing PT2MAP mapping could be
2703 * used for zeroing.
2704 */
2705 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2706 }
2707 #ifdef INVARIANTS
2708 else
2709 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2710 __func__, pt2_wirecount_get(m, pte1_idx)));
2711 #endif
2712 if (pt2pg_is_empty(m)) {
2713 pmap_unwire_pt2pg(pmap, va, m);
2714 pmap_add_delayed_free_list(m, free);
2715 }
2716 }
2717
2718 /*
2719 * After removing a L2 page table entry, this routine is used to
2720 * conditionally free the page, and manage the hold/wire counts.
2721 */
2722 static boolean_t
pmap_unuse_pt2(pmap_t pmap,vm_offset_t va,struct spglist * free)2723 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2724 {
2725 pt1_entry_t pte1;
2726 vm_page_t mpte;
2727
2728 if (va >= VM_MAXUSER_ADDRESS)
2729 return (FALSE);
2730 pte1 = pte1_load(pmap_pte1(pmap, va));
2731 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2732 return (pmap_unwire_pt2(pmap, va, mpte, free));
2733 }
2734
2735 /*************************************
2736 *
2737 * Page management routines.
2738 *
2739 *************************************/
2740
2741 static const uint32_t pc_freemask[_NPCM] = {
2742 [0 ... _NPCM - 2] = PC_FREEN,
2743 [_NPCM - 1] = PC_FREEL
2744 };
2745
2746 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2747 "Current number of pv entries");
2748
2749 #ifdef PV_STATS
2750 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2751
2752 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2753 "Current number of pv entry chunks");
2754 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2755 "Current number of pv entry chunks allocated");
2756 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2757 "Current number of pv entry chunks frees");
2758 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2759 0, "Number of times tried to get a chunk page but failed.");
2760
2761 static long pv_entry_frees, pv_entry_allocs;
2762 static int pv_entry_spare;
2763
2764 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2765 "Current number of pv entry frees");
2766 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2767 0, "Current number of pv entry allocs");
2768 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2769 "Current number of spare pv entries");
2770 #endif
2771
2772 /*
2773 * Is given page managed?
2774 */
2775 static __inline bool
is_managed(vm_paddr_t pa)2776 is_managed(vm_paddr_t pa)
2777 {
2778 vm_page_t m;
2779
2780 m = PHYS_TO_VM_PAGE(pa);
2781 if (m == NULL)
2782 return (false);
2783 return ((m->oflags & VPO_UNMANAGED) == 0);
2784 }
2785
2786 static __inline bool
pte1_is_managed(pt1_entry_t pte1)2787 pte1_is_managed(pt1_entry_t pte1)
2788 {
2789
2790 return (is_managed(pte1_pa(pte1)));
2791 }
2792
2793 static __inline bool
pte2_is_managed(pt2_entry_t pte2)2794 pte2_is_managed(pt2_entry_t pte2)
2795 {
2796
2797 return (is_managed(pte2_pa(pte2)));
2798 }
2799
2800 /*
2801 * We are in a serious low memory condition. Resort to
2802 * drastic measures to free some pages so we can allocate
2803 * another pv entry chunk.
2804 */
2805 static vm_page_t
pmap_pv_reclaim(pmap_t locked_pmap)2806 pmap_pv_reclaim(pmap_t locked_pmap)
2807 {
2808 struct pch newtail;
2809 struct pv_chunk *pc;
2810 struct md_page *pvh;
2811 pt1_entry_t *pte1p;
2812 pmap_t pmap;
2813 pt2_entry_t *pte2p, tpte2;
2814 pv_entry_t pv;
2815 vm_offset_t va;
2816 vm_page_t m, m_pc;
2817 struct spglist free;
2818 uint32_t inuse;
2819 int bit, field, freed;
2820
2821 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2822 pmap = NULL;
2823 m_pc = NULL;
2824 SLIST_INIT(&free);
2825 TAILQ_INIT(&newtail);
2826 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2827 SLIST_EMPTY(&free))) {
2828 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2829 if (pmap != pc->pc_pmap) {
2830 if (pmap != NULL) {
2831 if (pmap != locked_pmap)
2832 PMAP_UNLOCK(pmap);
2833 }
2834 pmap = pc->pc_pmap;
2835 /* Avoid deadlock and lock recursion. */
2836 if (pmap > locked_pmap)
2837 PMAP_LOCK(pmap);
2838 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2839 pmap = NULL;
2840 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2841 continue;
2842 }
2843 }
2844
2845 /*
2846 * Destroy every non-wired, 4 KB page mapping in the chunk.
2847 */
2848 freed = 0;
2849 for (field = 0; field < _NPCM; field++) {
2850 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2851 inuse != 0; inuse &= ~(1UL << bit)) {
2852 bit = ffs(inuse) - 1;
2853 pv = &pc->pc_pventry[field * 32 + bit];
2854 va = pv->pv_va;
2855 pte1p = pmap_pte1(pmap, va);
2856 if (pte1_is_section(pte1_load(pte1p)))
2857 continue;
2858 pte2p = pmap_pte2(pmap, va);
2859 tpte2 = pte2_load(pte2p);
2860 if ((tpte2 & PTE2_W) == 0)
2861 tpte2 = pte2_load_clear(pte2p);
2862 pmap_pte2_release(pte2p);
2863 if ((tpte2 & PTE2_W) != 0)
2864 continue;
2865 KASSERT(tpte2 != 0,
2866 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2867 pmap, va));
2868 pmap_tlb_flush(pmap, va);
2869 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2870 if (pte2_is_dirty(tpte2))
2871 vm_page_dirty(m);
2872 if ((tpte2 & PTE2_A) != 0)
2873 vm_page_aflag_set(m, PGA_REFERENCED);
2874 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2875 if (TAILQ_EMPTY(&m->md.pv_list) &&
2876 (m->flags & PG_FICTITIOUS) == 0) {
2877 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2878 if (TAILQ_EMPTY(&pvh->pv_list)) {
2879 vm_page_aflag_clear(m,
2880 PGA_WRITEABLE);
2881 }
2882 }
2883 pc->pc_map[field] |= 1UL << bit;
2884 pmap_unuse_pt2(pmap, va, &free);
2885 freed++;
2886 }
2887 }
2888 if (freed == 0) {
2889 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2890 continue;
2891 }
2892 /* Every freed mapping is for a 4 KB page. */
2893 pmap->pm_stats.resident_count -= freed;
2894 PV_STAT(pv_entry_frees += freed);
2895 PV_STAT(pv_entry_spare += freed);
2896 pv_entry_count -= freed;
2897 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2898 for (field = 0; field < _NPCM; field++)
2899 if (pc->pc_map[field] != pc_freemask[field]) {
2900 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2901 pc_list);
2902 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2903
2904 /*
2905 * One freed pv entry in locked_pmap is
2906 * sufficient.
2907 */
2908 if (pmap == locked_pmap)
2909 goto out;
2910 break;
2911 }
2912 if (field == _NPCM) {
2913 PV_STAT(pv_entry_spare -= _NPCPV);
2914 PV_STAT(pc_chunk_count--);
2915 PV_STAT(pc_chunk_frees++);
2916 /* Entire chunk is free; return it. */
2917 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2918 pmap_qremove((vm_offset_t)pc, 1);
2919 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2920 break;
2921 }
2922 }
2923 out:
2924 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2925 if (pmap != NULL) {
2926 if (pmap != locked_pmap)
2927 PMAP_UNLOCK(pmap);
2928 }
2929 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2930 m_pc = SLIST_FIRST(&free);
2931 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2932 /* Recycle a freed page table page. */
2933 m_pc->ref_count = 1;
2934 vm_wire_add(1);
2935 }
2936 vm_page_free_pages_toq(&free, false);
2937 return (m_pc);
2938 }
2939
2940 static void
free_pv_chunk(struct pv_chunk * pc)2941 free_pv_chunk(struct pv_chunk *pc)
2942 {
2943 vm_page_t m;
2944
2945 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2946 PV_STAT(pv_entry_spare -= _NPCPV);
2947 PV_STAT(pc_chunk_count--);
2948 PV_STAT(pc_chunk_frees++);
2949 /* entire chunk is free, return it */
2950 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2951 pmap_qremove((vm_offset_t)pc, 1);
2952 vm_page_unwire_noq(m);
2953 vm_page_free(m);
2954 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2955 }
2956
2957 /*
2958 * Free the pv_entry back to the free list.
2959 */
2960 static void
free_pv_entry(pmap_t pmap,pv_entry_t pv)2961 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2962 {
2963 struct pv_chunk *pc;
2964 int idx, field, bit;
2965
2966 rw_assert(&pvh_global_lock, RA_WLOCKED);
2967 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2968 PV_STAT(pv_entry_frees++);
2969 PV_STAT(pv_entry_spare++);
2970 pv_entry_count--;
2971 pc = pv_to_chunk(pv);
2972 idx = pv - &pc->pc_pventry[0];
2973 field = idx / 32;
2974 bit = idx % 32;
2975 pc->pc_map[field] |= 1ul << bit;
2976 for (idx = 0; idx < _NPCM; idx++)
2977 if (pc->pc_map[idx] != pc_freemask[idx]) {
2978 /*
2979 * 98% of the time, pc is already at the head of the
2980 * list. If it isn't already, move it to the head.
2981 */
2982 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2983 pc)) {
2984 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2985 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2986 pc_list);
2987 }
2988 return;
2989 }
2990 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2991 free_pv_chunk(pc);
2992 }
2993
2994 /*
2995 * Get a new pv_entry, allocating a block from the system
2996 * when needed.
2997 */
2998 static pv_entry_t
get_pv_entry(pmap_t pmap,boolean_t try)2999 get_pv_entry(pmap_t pmap, boolean_t try)
3000 {
3001 static const struct timeval printinterval = { 60, 0 };
3002 static struct timeval lastprint;
3003 int bit, field;
3004 pv_entry_t pv;
3005 struct pv_chunk *pc;
3006 vm_page_t m;
3007
3008 rw_assert(&pvh_global_lock, RA_WLOCKED);
3009 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3010 PV_STAT(pv_entry_allocs++);
3011 pv_entry_count++;
3012 if (pv_entry_count > pv_entry_high_water)
3013 if (ratecheck(&lastprint, &printinterval))
3014 printf("Approaching the limit on PV entries, consider "
3015 "increasing either the vm.pmap.shpgperproc or the "
3016 "vm.pmap.pv_entry_max tunable.\n");
3017 retry:
3018 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3019 if (pc != NULL) {
3020 for (field = 0; field < _NPCM; field++) {
3021 if (pc->pc_map[field]) {
3022 bit = ffs(pc->pc_map[field]) - 1;
3023 break;
3024 }
3025 }
3026 if (field < _NPCM) {
3027 pv = &pc->pc_pventry[field * 32 + bit];
3028 pc->pc_map[field] &= ~(1ul << bit);
3029 /* If this was the last item, move it to tail */
3030 for (field = 0; field < _NPCM; field++)
3031 if (pc->pc_map[field] != 0) {
3032 PV_STAT(pv_entry_spare--);
3033 return (pv); /* not full, return */
3034 }
3035 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3036 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3037 PV_STAT(pv_entry_spare--);
3038 return (pv);
3039 }
3040 }
3041 /*
3042 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3043 * global lock. If "pv_vafree" is currently non-empty, it will
3044 * remain non-empty until pmap_pte2list_alloc() completes.
3045 */
3046 if (pv_vafree == 0 ||
3047 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
3048 if (try) {
3049 pv_entry_count--;
3050 PV_STAT(pc_chunk_tryfail++);
3051 return (NULL);
3052 }
3053 m = pmap_pv_reclaim(pmap);
3054 if (m == NULL)
3055 goto retry;
3056 }
3057 PV_STAT(pc_chunk_count++);
3058 PV_STAT(pc_chunk_allocs++);
3059 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3060 pmap_qenter((vm_offset_t)pc, &m, 1);
3061 pc->pc_pmap = pmap;
3062 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3063 for (field = 1; field < _NPCM; field++)
3064 pc->pc_map[field] = pc_freemask[field];
3065 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3066 pv = &pc->pc_pventry[0];
3067 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3068 PV_STAT(pv_entry_spare += _NPCPV - 1);
3069 return (pv);
3070 }
3071
3072 /*
3073 * Create a pv entry for page at pa for
3074 * (pmap, va).
3075 */
3076 static void
pmap_insert_entry(pmap_t pmap,vm_offset_t va,vm_page_t m)3077 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3078 {
3079 pv_entry_t pv;
3080
3081 rw_assert(&pvh_global_lock, RA_WLOCKED);
3082 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3083 pv = get_pv_entry(pmap, FALSE);
3084 pv->pv_va = va;
3085 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3086 }
3087
3088 static __inline pv_entry_t
pmap_pvh_remove(struct md_page * pvh,pmap_t pmap,vm_offset_t va)3089 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3090 {
3091 pv_entry_t pv;
3092
3093 rw_assert(&pvh_global_lock, RA_WLOCKED);
3094 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3095 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3096 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3097 break;
3098 }
3099 }
3100 return (pv);
3101 }
3102
3103 static void
pmap_pvh_free(struct md_page * pvh,pmap_t pmap,vm_offset_t va)3104 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3105 {
3106 pv_entry_t pv;
3107
3108 pv = pmap_pvh_remove(pvh, pmap, va);
3109 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3110 free_pv_entry(pmap, pv);
3111 }
3112
3113 static void
pmap_remove_entry(pmap_t pmap,vm_page_t m,vm_offset_t va)3114 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3115 {
3116 struct md_page *pvh;
3117
3118 rw_assert(&pvh_global_lock, RA_WLOCKED);
3119 pmap_pvh_free(&m->md, pmap, va);
3120 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3121 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3122 if (TAILQ_EMPTY(&pvh->pv_list))
3123 vm_page_aflag_clear(m, PGA_WRITEABLE);
3124 }
3125 }
3126
3127 static void
pmap_pv_demote_pte1(pmap_t pmap,vm_offset_t va,vm_paddr_t pa)3128 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3129 {
3130 struct md_page *pvh;
3131 pv_entry_t pv;
3132 vm_offset_t va_last;
3133 vm_page_t m;
3134
3135 rw_assert(&pvh_global_lock, RA_WLOCKED);
3136 KASSERT((pa & PTE1_OFFSET) == 0,
3137 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3138
3139 /*
3140 * Transfer the 1mpage's pv entry for this mapping to the first
3141 * page's pv list.
3142 */
3143 pvh = pa_to_pvh(pa);
3144 va = pte1_trunc(va);
3145 pv = pmap_pvh_remove(pvh, pmap, va);
3146 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3147 m = PHYS_TO_VM_PAGE(pa);
3148 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3149 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3150 va_last = va + PTE1_SIZE - PAGE_SIZE;
3151 do {
3152 m++;
3153 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3154 ("pmap_pv_demote_pte1: page %p is not managed", m));
3155 va += PAGE_SIZE;
3156 pmap_insert_entry(pmap, va, m);
3157 } while (va < va_last);
3158 }
3159
3160 #if VM_NRESERVLEVEL > 0
3161 static void
pmap_pv_promote_pte1(pmap_t pmap,vm_offset_t va,vm_paddr_t pa)3162 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3163 {
3164 struct md_page *pvh;
3165 pv_entry_t pv;
3166 vm_offset_t va_last;
3167 vm_page_t m;
3168
3169 rw_assert(&pvh_global_lock, RA_WLOCKED);
3170 KASSERT((pa & PTE1_OFFSET) == 0,
3171 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3172
3173 /*
3174 * Transfer the first page's pv entry for this mapping to the
3175 * 1mpage's pv list. Aside from avoiding the cost of a call
3176 * to get_pv_entry(), a transfer avoids the possibility that
3177 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3178 * removes one of the mappings that is being promoted.
3179 */
3180 m = PHYS_TO_VM_PAGE(pa);
3181 va = pte1_trunc(va);
3182 pv = pmap_pvh_remove(&m->md, pmap, va);
3183 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3184 pvh = pa_to_pvh(pa);
3185 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3186 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3187 va_last = va + PTE1_SIZE - PAGE_SIZE;
3188 do {
3189 m++;
3190 va += PAGE_SIZE;
3191 pmap_pvh_free(&m->md, pmap, va);
3192 } while (va < va_last);
3193 }
3194 #endif
3195
3196 /*
3197 * Conditionally create a pv entry.
3198 */
3199 static boolean_t
pmap_try_insert_pv_entry(pmap_t pmap,vm_offset_t va,vm_page_t m)3200 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3201 {
3202 pv_entry_t pv;
3203
3204 rw_assert(&pvh_global_lock, RA_WLOCKED);
3205 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3206 if (pv_entry_count < pv_entry_high_water &&
3207 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
3208 pv->pv_va = va;
3209 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3210 return (TRUE);
3211 } else
3212 return (FALSE);
3213 }
3214
3215 /*
3216 * Create the pv entries for each of the pages within a section.
3217 */
3218 static bool
pmap_pv_insert_pte1(pmap_t pmap,vm_offset_t va,pt1_entry_t pte1,u_int flags)3219 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags)
3220 {
3221 struct md_page *pvh;
3222 pv_entry_t pv;
3223 bool noreclaim;
3224
3225 rw_assert(&pvh_global_lock, RA_WLOCKED);
3226 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
3227 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
3228 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
3229 return (false);
3230 pv->pv_va = va;
3231 pvh = pa_to_pvh(pte1_pa(pte1));
3232 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3233 return (true);
3234 }
3235
3236 static inline void
pmap_tlb_flush_pte1(pmap_t pmap,vm_offset_t va,pt1_entry_t npte1)3237 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3238 {
3239
3240 /* Kill all the small mappings or the big one only. */
3241 if (pte1_is_section(npte1))
3242 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3243 else
3244 pmap_tlb_flush(pmap, pte1_trunc(va));
3245 }
3246
3247 /*
3248 * Update kernel pte1 on all pmaps.
3249 *
3250 * The following function is called only on one cpu with disabled interrupts.
3251 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3252 * nobody can invoke explicit hardware table walk during the update of pte1.
3253 * Unsolicited hardware table walk can still happen, invoked by speculative
3254 * data or instruction prefetch or even by speculative hardware table walk.
3255 *
3256 * The break-before-make approach should be implemented here. However, it's
3257 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3258 * itself unexpectedly but voluntarily.
3259 */
3260 static void
pmap_update_pte1_kernel(vm_offset_t va,pt1_entry_t npte1)3261 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3262 {
3263 pmap_t pmap;
3264 pt1_entry_t *pte1p;
3265
3266 /*
3267 * Get current pmap. Interrupts should be disabled here
3268 * so PCPU_GET() is done atomically.
3269 */
3270 pmap = PCPU_GET(curpmap);
3271 if (pmap == NULL)
3272 pmap = kernel_pmap;
3273
3274 /*
3275 * (1) Change pte1 on current pmap.
3276 * (2) Flush all obsolete TLB entries on current CPU.
3277 * (3) Change pte1 on all pmaps.
3278 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3279 */
3280
3281 pte1p = pmap_pte1(pmap, va);
3282 pte1_store(pte1p, npte1);
3283
3284 /* Kill all the small mappings or the big one only. */
3285 if (pte1_is_section(npte1)) {
3286 pmap_pte1_kern_promotions++;
3287 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3288 } else {
3289 pmap_pte1_kern_demotions++;
3290 tlb_flush_local(pte1_trunc(va));
3291 }
3292
3293 /*
3294 * In SMP case, this function is called when all cpus are at smp
3295 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3296 * In UP case, the function is called with this lock locked.
3297 */
3298 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3299 pte1p = pmap_pte1(pmap, va);
3300 pte1_store(pte1p, npte1);
3301 }
3302
3303 #ifdef SMP
3304 /* Kill all the small mappings or the big one only. */
3305 if (pte1_is_section(npte1))
3306 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3307 else
3308 tlb_flush(pte1_trunc(va));
3309 #endif
3310 }
3311
3312 #ifdef SMP
3313 struct pte1_action {
3314 vm_offset_t va;
3315 pt1_entry_t npte1;
3316 u_int update; /* CPU that updates the PTE1 */
3317 };
3318
3319 static void
pmap_update_pte1_action(void * arg)3320 pmap_update_pte1_action(void *arg)
3321 {
3322 struct pte1_action *act = arg;
3323
3324 if (act->update == PCPU_GET(cpuid))
3325 pmap_update_pte1_kernel(act->va, act->npte1);
3326 }
3327
3328 /*
3329 * Change pte1 on current pmap.
3330 * Note that kernel pte1 must be changed on all pmaps.
3331 *
3332 * According to the architecture reference manual published by ARM,
3333 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3334 * According to this manual, UNPREDICTABLE behaviours must never happen in
3335 * a viable system. In contrast, on x86 processors, it is not specified which
3336 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3337 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3338 * Black).
3339 *
3340 * It's a problem when either promotion or demotion is being done. The pte1
3341 * update and appropriate TLB flush must be done atomically in general.
3342 */
3343 static void
pmap_change_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va,pt1_entry_t npte1)3344 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3345 pt1_entry_t npte1)
3346 {
3347
3348 if (pmap == kernel_pmap) {
3349 struct pte1_action act;
3350
3351 sched_pin();
3352 act.va = va;
3353 act.npte1 = npte1;
3354 act.update = PCPU_GET(cpuid);
3355 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3356 pmap_update_pte1_action, NULL, &act);
3357 sched_unpin();
3358 } else {
3359 register_t cspr;
3360
3361 /*
3362 * Use break-before-make approach for changing userland
3363 * mappings. It can cause L1 translation aborts on other
3364 * cores in SMP case. So, special treatment is implemented
3365 * in pmap_fault(). To reduce the likelihood that another core
3366 * will be affected by the broken mapping, disable interrupts
3367 * until the mapping change is completed.
3368 */
3369 cspr = disable_interrupts(PSR_I | PSR_F);
3370 pte1_clear(pte1p);
3371 pmap_tlb_flush_pte1(pmap, va, npte1);
3372 pte1_store(pte1p, npte1);
3373 restore_interrupts(cspr);
3374 }
3375 }
3376 #else
3377 static void
pmap_change_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va,pt1_entry_t npte1)3378 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3379 pt1_entry_t npte1)
3380 {
3381
3382 if (pmap == kernel_pmap) {
3383 mtx_lock_spin(&allpmaps_lock);
3384 pmap_update_pte1_kernel(va, npte1);
3385 mtx_unlock_spin(&allpmaps_lock);
3386 } else {
3387 register_t cspr;
3388
3389 /*
3390 * Use break-before-make approach for changing userland
3391 * mappings. It's absolutely safe in UP case when interrupts
3392 * are disabled.
3393 */
3394 cspr = disable_interrupts(PSR_I | PSR_F);
3395 pte1_clear(pte1p);
3396 pmap_tlb_flush_pte1(pmap, va, npte1);
3397 pte1_store(pte1p, npte1);
3398 restore_interrupts(cspr);
3399 }
3400 }
3401 #endif
3402
3403 #if VM_NRESERVLEVEL > 0
3404 /*
3405 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3406 * within a single page table page (PT2) to a single 1MB page mapping.
3407 * For promotion to occur, two conditions must be met: (1) the 4KB page
3408 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3409 * mappings must have identical characteristics.
3410 *
3411 * Managed (PG_MANAGED) mappings within the kernel address space are not
3412 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3413 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3414 * read the PTE1 from the kernel pmap.
3415 */
3416 static void
pmap_promote_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va)3417 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3418 {
3419 pt1_entry_t npte1;
3420 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3421 pt2_entry_t *pte2p, pte2;
3422 vm_offset_t pteva __unused;
3423 vm_page_t m __unused;
3424
3425 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3426 pmap, va, pte1_load(pte1p), pte1p));
3427
3428 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3429
3430 /*
3431 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3432 * either invalid, unused, or does not map the first 4KB physical page
3433 * within a 1MB page.
3434 */
3435 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3436 fpte2 = pte2_load(fpte2p);
3437 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3438 (PTE2_A | PTE2_V)) {
3439 pmap_pte1_p_failures++;
3440 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3441 __func__, va, pmap);
3442 return;
3443 }
3444 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3445 pmap_pte1_p_failures++;
3446 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3447 __func__, va, pmap);
3448 return;
3449 }
3450 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3451 /*
3452 * When page is not modified, PTE2_RO can be set without
3453 * a TLB invalidation.
3454 */
3455 fpte2 |= PTE2_RO;
3456 pte2_store(fpte2p, fpte2);
3457 }
3458
3459 /*
3460 * Examine each of the other PTE2s in the specified PT2. Abort if this
3461 * PTE2 maps an unexpected 4KB physical page or does not have identical
3462 * characteristics to the first PTE2.
3463 */
3464 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3465 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3466 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3467 pte2 = pte2_load(pte2p);
3468 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3469 pmap_pte1_p_failures++;
3470 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3471 __func__, va, pmap);
3472 return;
3473 }
3474 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3475 /*
3476 * When page is not modified, PTE2_RO can be set
3477 * without a TLB invalidation. See note above.
3478 */
3479 pte2 |= PTE2_RO;
3480 pte2_store(pte2p, pte2);
3481 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3482 PTE2_FRAME);
3483 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3484 __func__, pteva, pmap);
3485 }
3486 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3487 pmap_pte1_p_failures++;
3488 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3489 __func__, va, pmap);
3490 return;
3491 }
3492
3493 fpte2_fav -= PTE2_SIZE;
3494 }
3495 /*
3496 * The page table page in its current state will stay in PT2TAB
3497 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3498 * or destroyed by pmap_remove_pte1().
3499 *
3500 * Note that L2 page table size is not equal to PAGE_SIZE.
3501 */
3502 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3503 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3504 ("%s: PT2 page is out of range", __func__));
3505 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3506 ("%s: PT2 page's pindex is wrong", __func__));
3507
3508 /*
3509 * Get pte1 from pte2 format.
3510 */
3511 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3512
3513 /*
3514 * Promote the pv entries.
3515 */
3516 if (pte2_is_managed(fpte2))
3517 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3518
3519 /*
3520 * Promote the mappings.
3521 */
3522 pmap_change_pte1(pmap, pte1p, va, npte1);
3523
3524 pmap_pte1_promotions++;
3525 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3526 __func__, va, pmap);
3527
3528 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3529 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3530 }
3531 #endif /* VM_NRESERVLEVEL > 0 */
3532
3533 /*
3534 * Zero L2 page table page.
3535 */
3536 static __inline void
pmap_clear_pt2(pt2_entry_t * fpte2p)3537 pmap_clear_pt2(pt2_entry_t *fpte2p)
3538 {
3539 pt2_entry_t *pte2p;
3540
3541 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3542 pte2_clear(pte2p);
3543
3544 }
3545
3546 /*
3547 * Removes a 1MB page mapping from the kernel pmap.
3548 */
3549 static void
pmap_remove_kernel_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va)3550 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3551 {
3552 vm_page_t m;
3553 uint32_t pte1_idx;
3554 pt2_entry_t *fpte2p;
3555 vm_paddr_t pt2_pa;
3556
3557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3558 m = pmap_pt2_page(pmap, va);
3559 if (m == NULL)
3560 /*
3561 * QQQ: Is this function called only on promoted pte1?
3562 * We certainly do section mappings directly
3563 * (without promotion) in kernel !!!
3564 */
3565 panic("%s: missing pt2 page", __func__);
3566
3567 pte1_idx = pte1_index(va);
3568
3569 /*
3570 * Initialize the L2 page table.
3571 */
3572 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3573 pmap_clear_pt2(fpte2p);
3574
3575 /*
3576 * Remove the mapping.
3577 */
3578 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3579 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3580
3581 /*
3582 * QQQ: We do not need to invalidate PT2MAP mapping
3583 * as we did not change it. I.e. the L2 page table page
3584 * was and still is mapped the same way.
3585 */
3586 }
3587
3588 /*
3589 * Do the things to unmap a section in a process
3590 */
3591 static void
pmap_remove_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t sva,struct spglist * free)3592 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3593 struct spglist *free)
3594 {
3595 pt1_entry_t opte1;
3596 struct md_page *pvh;
3597 vm_offset_t eva, va;
3598 vm_page_t m;
3599
3600 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3601 pte1_load(pte1p), pte1p));
3602
3603 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3604 KASSERT((sva & PTE1_OFFSET) == 0,
3605 ("%s: sva is not 1mpage aligned", __func__));
3606
3607 /*
3608 * Clear and invalidate the mapping. It should occupy one and only TLB
3609 * entry. So, pmap_tlb_flush() called with aligned address should be
3610 * sufficient.
3611 */
3612 opte1 = pte1_load_clear(pte1p);
3613 pmap_tlb_flush(pmap, sva);
3614
3615 if (pte1_is_wired(opte1))
3616 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3617 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3618 if (pte1_is_managed(opte1)) {
3619 pvh = pa_to_pvh(pte1_pa(opte1));
3620 pmap_pvh_free(pvh, pmap, sva);
3621 eva = sva + PTE1_SIZE;
3622 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3623 va < eva; va += PAGE_SIZE, m++) {
3624 if (pte1_is_dirty(opte1))
3625 vm_page_dirty(m);
3626 if (opte1 & PTE1_A)
3627 vm_page_aflag_set(m, PGA_REFERENCED);
3628 if (TAILQ_EMPTY(&m->md.pv_list) &&
3629 TAILQ_EMPTY(&pvh->pv_list))
3630 vm_page_aflag_clear(m, PGA_WRITEABLE);
3631 }
3632 }
3633 if (pmap == kernel_pmap) {
3634 /*
3635 * L2 page table(s) can't be removed from kernel map as
3636 * kernel counts on it (stuff around pmap_growkernel()).
3637 */
3638 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3639 } else {
3640 /*
3641 * Get associated L2 page table page.
3642 * It's possible that the page was never allocated.
3643 */
3644 m = pmap_pt2_page(pmap, sva);
3645 if (m != NULL)
3646 pmap_unwire_pt2_all(pmap, sva, m, free);
3647 }
3648 }
3649
3650 /*
3651 * Fills L2 page table page with mappings to consecutive physical pages.
3652 */
3653 static __inline void
pmap_fill_pt2(pt2_entry_t * fpte2p,pt2_entry_t npte2)3654 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3655 {
3656 pt2_entry_t *pte2p;
3657
3658 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3659 pte2_store(pte2p, npte2);
3660 npte2 += PTE2_SIZE;
3661 }
3662 }
3663
3664 /*
3665 * Tries to demote a 1MB page mapping. If demotion fails, the
3666 * 1MB page mapping is invalidated.
3667 */
3668 static boolean_t
pmap_demote_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va)3669 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3670 {
3671 pt1_entry_t opte1, npte1;
3672 pt2_entry_t *fpte2p, npte2;
3673 vm_paddr_t pt2pg_pa, pt2_pa;
3674 vm_page_t m;
3675 struct spglist free;
3676 uint32_t pte1_idx, isnew = 0;
3677
3678 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3679 pmap, va, pte1_load(pte1p), pte1p));
3680
3681 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3682
3683 opte1 = pte1_load(pte1p);
3684 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3685
3686 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3687 KASSERT(!pte1_is_wired(opte1),
3688 ("%s: PT2 page for a wired mapping is missing", __func__));
3689
3690 /*
3691 * Invalidate the 1MB page mapping and return
3692 * "failure" if the mapping was never accessed or the
3693 * allocation of the new page table page fails.
3694 */
3695 if ((opte1 & PTE1_A) == 0 ||
3696 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
3697 SLIST_INIT(&free);
3698 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3699 vm_page_free_pages_toq(&free, false);
3700 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3701 __func__, va, pmap);
3702 return (FALSE);
3703 }
3704 m->pindex = pte1_index(va) & ~PT2PG_MASK;
3705 if (va < VM_MAXUSER_ADDRESS)
3706 pmap->pm_stats.resident_count++;
3707
3708 isnew = 1;
3709
3710 /*
3711 * We init all L2 page tables in the page even if
3712 * we are going to change everything for one L2 page
3713 * table in a while.
3714 */
3715 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3716 } else {
3717 if (va < VM_MAXUSER_ADDRESS) {
3718 if (pt2_is_empty(m, va))
3719 isnew = 1; /* Demoting section w/o promotion. */
3720 #ifdef INVARIANTS
3721 else
3722 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3723 " count %u", __func__,
3724 pt2_wirecount_get(m, pte1_index(va))));
3725 #endif
3726 }
3727 }
3728
3729 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3730 pte1_idx = pte1_index(va);
3731 /*
3732 * If the pmap is current, then the PT2MAP can provide access to
3733 * the page table page (promoted L2 page tables are not unmapped).
3734 * Otherwise, temporarily map the L2 page table page (m) into
3735 * the kernel's address space at either PADDR1 or PADDR2.
3736 *
3737 * Note that L2 page table size is not equal to PAGE_SIZE.
3738 */
3739 if (pmap_is_current(pmap))
3740 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3741 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3742 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3743 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3744 #ifdef SMP
3745 PMAP1cpu = PCPU_GET(cpuid);
3746 #endif
3747 tlb_flush_local((vm_offset_t)PADDR1);
3748 PMAP1changed++;
3749 } else
3750 #ifdef SMP
3751 if (PMAP1cpu != PCPU_GET(cpuid)) {
3752 PMAP1cpu = PCPU_GET(cpuid);
3753 tlb_flush_local((vm_offset_t)PADDR1);
3754 PMAP1changedcpu++;
3755 } else
3756 #endif
3757 PMAP1unchanged++;
3758 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3759 } else {
3760 mtx_lock(&PMAP2mutex);
3761 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3762 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3763 tlb_flush((vm_offset_t)PADDR2);
3764 }
3765 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3766 }
3767 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3768 npte1 = PTE1_LINK(pt2_pa);
3769
3770 KASSERT((opte1 & PTE1_A) != 0,
3771 ("%s: opte1 is missing PTE1_A", __func__));
3772 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3773 ("%s: opte1 has PTE1_NM", __func__));
3774
3775 /*
3776 * Get pte2 from pte1 format.
3777 */
3778 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3779
3780 /*
3781 * If the L2 page table page is new, initialize it. If the mapping
3782 * has changed attributes, update the page table entries.
3783 */
3784 if (isnew != 0) {
3785 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3786 pmap_fill_pt2(fpte2p, npte2);
3787 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3788 (npte2 & PTE2_PROMOTE))
3789 pmap_fill_pt2(fpte2p, npte2);
3790
3791 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3792 ("%s: fpte2p and npte2 map different physical addresses",
3793 __func__));
3794
3795 if (fpte2p == PADDR2)
3796 mtx_unlock(&PMAP2mutex);
3797
3798 /*
3799 * Demote the mapping. This pmap is locked. The old PTE1 has
3800 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3801 * has not PTE1_NM set. Thus, there is no danger of a race with
3802 * another processor changing the setting of PTE1_A and/or PTE1_NM
3803 * between the read above and the store below.
3804 */
3805 pmap_change_pte1(pmap, pte1p, va, npte1);
3806
3807 /*
3808 * Demote the pv entry. This depends on the earlier demotion
3809 * of the mapping. Specifically, the (re)creation of a per-
3810 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3811 * which might reclaim a newly (re)created per-page pv entry
3812 * and destroy the associated mapping. In order to destroy
3813 * the mapping, the PTE1 must have already changed from mapping
3814 * the 1mpage to referencing the page table page.
3815 */
3816 if (pte1_is_managed(opte1))
3817 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3818
3819 pmap_pte1_demotions++;
3820 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3821 __func__, va, pmap);
3822
3823 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3824 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3825 return (TRUE);
3826 }
3827
3828 /*
3829 * Insert the given physical page (p) at
3830 * the specified virtual address (v) in the
3831 * target physical map with the protection requested.
3832 *
3833 * If specified, the page will be wired down, meaning
3834 * that the related pte can not be reclaimed.
3835 *
3836 * NB: This is the only routine which MAY NOT lazy-evaluate
3837 * or lose information. That is, this routine must actually
3838 * insert this page into the given map NOW.
3839 */
3840 int
pmap_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)3841 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3842 u_int flags, int8_t psind)
3843 {
3844 pt1_entry_t *pte1p;
3845 pt2_entry_t *pte2p;
3846 pt2_entry_t npte2, opte2;
3847 pv_entry_t pv;
3848 vm_paddr_t opa, pa;
3849 vm_page_t mpte2, om;
3850 int rv;
3851
3852 va = trunc_page(va);
3853 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3854 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3855 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3856 va));
3857 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va),
3858 ("%s: managed mapping within the clean submap", __func__));
3859 if ((m->oflags & VPO_UNMANAGED) == 0)
3860 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3861 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3862 ("%s: flags %u has reserved bits set", __func__, flags));
3863 pa = VM_PAGE_TO_PHYS(m);
3864 npte2 = PTE2(pa, PTE2_A, vm_page_pte2_attr(m));
3865 if ((flags & VM_PROT_WRITE) == 0)
3866 npte2 |= PTE2_NM;
3867 if ((prot & VM_PROT_WRITE) == 0)
3868 npte2 |= PTE2_RO;
3869 KASSERT((npte2 & (PTE2_NM | PTE2_RO)) != PTE2_RO,
3870 ("%s: flags includes VM_PROT_WRITE but prot doesn't", __func__));
3871 if ((prot & VM_PROT_EXECUTE) == 0)
3872 npte2 |= PTE2_NX;
3873 if ((flags & PMAP_ENTER_WIRED) != 0)
3874 npte2 |= PTE2_W;
3875 if (va < VM_MAXUSER_ADDRESS)
3876 npte2 |= PTE2_U;
3877 if (pmap != kernel_pmap)
3878 npte2 |= PTE2_NG;
3879
3880 rw_wlock(&pvh_global_lock);
3881 PMAP_LOCK(pmap);
3882 sched_pin();
3883 if (psind == 1) {
3884 /* Assert the required virtual and physical alignment. */
3885 KASSERT((va & PTE1_OFFSET) == 0,
3886 ("%s: va unaligned", __func__));
3887 KASSERT(m->psind > 0, ("%s: m->psind < psind", __func__));
3888 rv = pmap_enter_pte1(pmap, va, PTE1_PA(pa) | ATTR_TO_L1(npte2) |
3889 PTE1_V, flags, m);
3890 goto out;
3891 }
3892
3893 /*
3894 * In the case that a page table page is not
3895 * resident, we are creating it here.
3896 */
3897 if (va < VM_MAXUSER_ADDRESS) {
3898 mpte2 = pmap_allocpte2(pmap, va, flags);
3899 if (mpte2 == NULL) {
3900 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3901 ("pmap_allocpte2 failed with sleep allowed"));
3902 rv = KERN_RESOURCE_SHORTAGE;
3903 goto out;
3904 }
3905 } else
3906 mpte2 = NULL;
3907 pte1p = pmap_pte1(pmap, va);
3908 if (pte1_is_section(pte1_load(pte1p)))
3909 panic("%s: attempted on 1MB page", __func__);
3910 pte2p = pmap_pte2_quick(pmap, va);
3911 if (pte2p == NULL)
3912 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3913
3914 om = NULL;
3915 opte2 = pte2_load(pte2p);
3916 opa = pte2_pa(opte2);
3917 /*
3918 * Mapping has not changed, must be protection or wiring change.
3919 */
3920 if (pte2_is_valid(opte2) && (opa == pa)) {
3921 /*
3922 * Wiring change, just update stats. We don't worry about
3923 * wiring PT2 pages as they remain resident as long as there
3924 * are valid mappings in them. Hence, if a user page is wired,
3925 * the PT2 page will be also.
3926 */
3927 if (pte2_is_wired(npte2) && !pte2_is_wired(opte2))
3928 pmap->pm_stats.wired_count++;
3929 else if (!pte2_is_wired(npte2) && pte2_is_wired(opte2))
3930 pmap->pm_stats.wired_count--;
3931
3932 /*
3933 * Remove extra pte2 reference
3934 */
3935 if (mpte2)
3936 pt2_wirecount_dec(mpte2, pte1_index(va));
3937 if ((m->oflags & VPO_UNMANAGED) == 0)
3938 om = m;
3939 goto validate;
3940 }
3941
3942 /*
3943 * QQQ: We think that changing physical address on writeable mapping
3944 * is not safe. Well, maybe on kernel address space with correct
3945 * locking, it can make a sense. However, we have no idea why
3946 * anyone should do that on user address space. Are we wrong?
3947 */
3948 KASSERT((opa == 0) || (opa == pa) ||
3949 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3950 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3951 __func__, pmap, va, opte2, opa, pa, flags, prot));
3952
3953 pv = NULL;
3954
3955 /*
3956 * Mapping has changed, invalidate old range and fall through to
3957 * handle validating new mapping.
3958 */
3959 if (opa) {
3960 if (pte2_is_wired(opte2))
3961 pmap->pm_stats.wired_count--;
3962 om = PHYS_TO_VM_PAGE(opa);
3963 if (om != NULL && (om->oflags & VPO_UNMANAGED) != 0)
3964 om = NULL;
3965 if (om != NULL)
3966 pv = pmap_pvh_remove(&om->md, pmap, va);
3967
3968 /*
3969 * Remove extra pte2 reference
3970 */
3971 if (mpte2 != NULL)
3972 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3973 } else
3974 pmap->pm_stats.resident_count++;
3975
3976 /*
3977 * Enter on the PV list if part of our managed memory.
3978 */
3979 if ((m->oflags & VPO_UNMANAGED) == 0) {
3980 if (pv == NULL) {
3981 pv = get_pv_entry(pmap, FALSE);
3982 pv->pv_va = va;
3983 }
3984 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3985 } else if (pv != NULL)
3986 free_pv_entry(pmap, pv);
3987
3988 /*
3989 * Increment counters
3990 */
3991 if (pte2_is_wired(npte2))
3992 pmap->pm_stats.wired_count++;
3993
3994 validate:
3995 /*
3996 * Now validate mapping with desired protection/wiring.
3997 */
3998 if (prot & VM_PROT_WRITE) {
3999 if ((m->oflags & VPO_UNMANAGED) == 0)
4000 vm_page_aflag_set(m, PGA_WRITEABLE);
4001 }
4002
4003 /*
4004 * If the mapping or permission bits are different, we need
4005 * to update the pte2.
4006 *
4007 * QQQ: Think again and again what to do
4008 * if the mapping is going to be changed!
4009 */
4010 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4011 /*
4012 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4013 * is set. Do it now, before the mapping is stored and made
4014 * valid for hardware table walk. If done later, there is a race
4015 * for other threads of current process in lazy loading case.
4016 * Don't do it for kernel memory which is mapped with exec
4017 * permission even if the memory isn't going to hold executable
4018 * code. The only time when icache sync is needed is after
4019 * kernel module is loaded and the relocation info is processed.
4020 * And it's done in elf_cpu_load_file().
4021 *
4022 * QQQ: (1) Does it exist any better way where
4023 * or how to sync icache?
4024 * (2) Now, we do it on a page basis.
4025 */
4026 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4027 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4028 (opa != pa || (opte2 & PTE2_NX)))
4029 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4030
4031 if (opte2 & PTE2_V) {
4032 /* Change mapping with break-before-make approach. */
4033 opte2 = pte2_load_clear(pte2p);
4034 pmap_tlb_flush(pmap, va);
4035 pte2_store(pte2p, npte2);
4036 if (om != NULL) {
4037 KASSERT((om->oflags & VPO_UNMANAGED) == 0,
4038 ("%s: om %p unmanaged", __func__, om));
4039 if ((opte2 & PTE2_A) != 0)
4040 vm_page_aflag_set(om, PGA_REFERENCED);
4041 if (pte2_is_dirty(opte2))
4042 vm_page_dirty(om);
4043 if (TAILQ_EMPTY(&om->md.pv_list) &&
4044 ((om->flags & PG_FICTITIOUS) != 0 ||
4045 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4046 vm_page_aflag_clear(om, PGA_WRITEABLE);
4047 }
4048 } else
4049 pte2_store(pte2p, npte2);
4050 }
4051 #if 0
4052 else {
4053 /*
4054 * QQQ: In time when both access and not mofified bits are
4055 * emulated by software, this should not happen. Some
4056 * analysis is need, if this really happen. Missing
4057 * tlb flush somewhere could be the reason.
4058 */
4059 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4060 va, opte2, npte2);
4061 }
4062 #endif
4063
4064 #if VM_NRESERVLEVEL > 0
4065 /*
4066 * If both the L2 page table page and the reservation are fully
4067 * populated, then attempt promotion.
4068 */
4069 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4070 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4071 vm_reserv_level_iffullpop(m) == 0)
4072 pmap_promote_pte1(pmap, pte1p, va);
4073 #endif
4074
4075 rv = KERN_SUCCESS;
4076 out:
4077 sched_unpin();
4078 rw_wunlock(&pvh_global_lock);
4079 PMAP_UNLOCK(pmap);
4080 return (rv);
4081 }
4082
4083 /*
4084 * Do the things to unmap a page in a process.
4085 */
4086 static int
pmap_remove_pte2(pmap_t pmap,pt2_entry_t * pte2p,vm_offset_t va,struct spglist * free)4087 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4088 struct spglist *free)
4089 {
4090 pt2_entry_t opte2;
4091 vm_page_t m;
4092
4093 rw_assert(&pvh_global_lock, RA_WLOCKED);
4094 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4095
4096 /* Clear and invalidate the mapping. */
4097 opte2 = pte2_load_clear(pte2p);
4098 pmap_tlb_flush(pmap, va);
4099
4100 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4101 __func__, pmap, va, opte2));
4102
4103 if (opte2 & PTE2_W)
4104 pmap->pm_stats.wired_count -= 1;
4105 pmap->pm_stats.resident_count -= 1;
4106 if (pte2_is_managed(opte2)) {
4107 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4108 if (pte2_is_dirty(opte2))
4109 vm_page_dirty(m);
4110 if (opte2 & PTE2_A)
4111 vm_page_aflag_set(m, PGA_REFERENCED);
4112 pmap_remove_entry(pmap, m, va);
4113 }
4114 return (pmap_unuse_pt2(pmap, va, free));
4115 }
4116
4117 /*
4118 * Remove a single page from a process address space.
4119 */
4120 static void
pmap_remove_page(pmap_t pmap,vm_offset_t va,struct spglist * free)4121 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4122 {
4123 pt2_entry_t *pte2p;
4124
4125 rw_assert(&pvh_global_lock, RA_WLOCKED);
4126 KASSERT(curthread->td_pinned > 0,
4127 ("%s: curthread not pinned", __func__));
4128 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4129 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4130 !pte2_is_valid(pte2_load(pte2p)))
4131 return;
4132 pmap_remove_pte2(pmap, pte2p, va, free);
4133 }
4134
4135 /*
4136 * Remove the given range of addresses from the specified map.
4137 *
4138 * It is assumed that the start and end are properly
4139 * rounded to the page size.
4140 */
4141 void
pmap_remove(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)4142 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4143 {
4144 vm_offset_t nextva;
4145 pt1_entry_t *pte1p, pte1;
4146 pt2_entry_t *pte2p, pte2;
4147 struct spglist free;
4148
4149 /*
4150 * Perform an unsynchronized read. This is, however, safe.
4151 */
4152 if (pmap->pm_stats.resident_count == 0)
4153 return;
4154
4155 SLIST_INIT(&free);
4156
4157 rw_wlock(&pvh_global_lock);
4158 sched_pin();
4159 PMAP_LOCK(pmap);
4160
4161 /*
4162 * Special handling of removing one page. A very common
4163 * operation and easy to short circuit some code.
4164 */
4165 if (sva + PAGE_SIZE == eva) {
4166 pte1 = pte1_load(pmap_pte1(pmap, sva));
4167 if (pte1_is_link(pte1)) {
4168 pmap_remove_page(pmap, sva, &free);
4169 goto out;
4170 }
4171 }
4172
4173 for (; sva < eva; sva = nextva) {
4174 /*
4175 * Calculate address for next L2 page table.
4176 */
4177 nextva = pte1_trunc(sva + PTE1_SIZE);
4178 if (nextva < sva)
4179 nextva = eva;
4180 if (pmap->pm_stats.resident_count == 0)
4181 break;
4182
4183 pte1p = pmap_pte1(pmap, sva);
4184 pte1 = pte1_load(pte1p);
4185
4186 /*
4187 * Weed out invalid mappings. Note: we assume that the L1 page
4188 * table is always allocated, and in kernel virtual.
4189 */
4190 if (pte1 == 0)
4191 continue;
4192
4193 if (pte1_is_section(pte1)) {
4194 /*
4195 * Are we removing the entire large page? If not,
4196 * demote the mapping and fall through.
4197 */
4198 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4199 pmap_remove_pte1(pmap, pte1p, sva, &free);
4200 continue;
4201 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4202 /* The large page mapping was destroyed. */
4203 continue;
4204 }
4205 #ifdef INVARIANTS
4206 else {
4207 /* Update pte1 after demotion. */
4208 pte1 = pte1_load(pte1p);
4209 }
4210 #endif
4211 }
4212
4213 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4214 " is not link", __func__, pmap, sva, pte1, pte1p));
4215
4216 /*
4217 * Limit our scan to either the end of the va represented
4218 * by the current L2 page table page, or to the end of the
4219 * range being removed.
4220 */
4221 if (nextva > eva)
4222 nextva = eva;
4223
4224 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4225 pte2p++, sva += PAGE_SIZE) {
4226 pte2 = pte2_load(pte2p);
4227 if (!pte2_is_valid(pte2))
4228 continue;
4229 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4230 break;
4231 }
4232 }
4233 out:
4234 sched_unpin();
4235 rw_wunlock(&pvh_global_lock);
4236 PMAP_UNLOCK(pmap);
4237 vm_page_free_pages_toq(&free, false);
4238 }
4239
4240 /*
4241 * Routine: pmap_remove_all
4242 * Function:
4243 * Removes this physical page from
4244 * all physical maps in which it resides.
4245 * Reflects back modify bits to the pager.
4246 *
4247 * Notes:
4248 * Original versions of this routine were very
4249 * inefficient because they iteratively called
4250 * pmap_remove (slow...)
4251 */
4252
4253 void
pmap_remove_all(vm_page_t m)4254 pmap_remove_all(vm_page_t m)
4255 {
4256 struct md_page *pvh;
4257 pv_entry_t pv;
4258 pmap_t pmap;
4259 pt2_entry_t *pte2p, opte2;
4260 pt1_entry_t *pte1p;
4261 vm_offset_t va;
4262 struct spglist free;
4263
4264 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4265 ("%s: page %p is not managed", __func__, m));
4266 SLIST_INIT(&free);
4267 rw_wlock(&pvh_global_lock);
4268 sched_pin();
4269 if ((m->flags & PG_FICTITIOUS) != 0)
4270 goto small_mappings;
4271 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4272 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4273 va = pv->pv_va;
4274 pmap = PV_PMAP(pv);
4275 PMAP_LOCK(pmap);
4276 pte1p = pmap_pte1(pmap, va);
4277 (void)pmap_demote_pte1(pmap, pte1p, va);
4278 PMAP_UNLOCK(pmap);
4279 }
4280 small_mappings:
4281 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4282 pmap = PV_PMAP(pv);
4283 PMAP_LOCK(pmap);
4284 pmap->pm_stats.resident_count--;
4285 pte1p = pmap_pte1(pmap, pv->pv_va);
4286 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4287 "a 1mpage in page %p's pv list", __func__, m));
4288 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4289 opte2 = pte2_load_clear(pte2p);
4290 pmap_tlb_flush(pmap, pv->pv_va);
4291 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4292 __func__, pmap, pv->pv_va));
4293 if (pte2_is_wired(opte2))
4294 pmap->pm_stats.wired_count--;
4295 if (opte2 & PTE2_A)
4296 vm_page_aflag_set(m, PGA_REFERENCED);
4297
4298 /*
4299 * Update the vm_page_t clean and reference bits.
4300 */
4301 if (pte2_is_dirty(opte2))
4302 vm_page_dirty(m);
4303 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4304 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4305 free_pv_entry(pmap, pv);
4306 PMAP_UNLOCK(pmap);
4307 }
4308 vm_page_aflag_clear(m, PGA_WRITEABLE);
4309 sched_unpin();
4310 rw_wunlock(&pvh_global_lock);
4311 vm_page_free_pages_toq(&free, false);
4312 }
4313
4314 /*
4315 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4316 * good coding style, a.k.a. 80 character line width limit hell.
4317 */
4318 static __inline void
pmap_remove_pte1_quick(pmap_t pmap,pt1_entry_t pte1,pv_entry_t pv,struct spglist * free)4319 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4320 struct spglist *free)
4321 {
4322 vm_paddr_t pa;
4323 vm_page_t m, mt, mpt2pg;
4324 struct md_page *pvh;
4325
4326 pa = pte1_pa(pte1);
4327 m = PHYS_TO_VM_PAGE(pa);
4328
4329 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4330 __func__, m, m->phys_addr, pa));
4331 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4332 m < &vm_page_array[vm_page_array_size],
4333 ("%s: bad pte1 %#x", __func__, pte1));
4334
4335 if (pte1_is_dirty(pte1)) {
4336 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4337 vm_page_dirty(mt);
4338 }
4339
4340 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4341 pvh = pa_to_pvh(pa);
4342 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4343 if (TAILQ_EMPTY(&pvh->pv_list)) {
4344 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4345 if (TAILQ_EMPTY(&mt->md.pv_list))
4346 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4347 }
4348 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4349 if (mpt2pg != NULL)
4350 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4351 }
4352
4353 /*
4354 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4355 * good coding style, a.k.a. 80 character line width limit hell.
4356 */
4357 static __inline void
pmap_remove_pte2_quick(pmap_t pmap,pt2_entry_t pte2,pv_entry_t pv,struct spglist * free)4358 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4359 struct spglist *free)
4360 {
4361 vm_paddr_t pa;
4362 vm_page_t m;
4363 struct md_page *pvh;
4364
4365 pa = pte2_pa(pte2);
4366 m = PHYS_TO_VM_PAGE(pa);
4367
4368 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4369 __func__, m, m->phys_addr, pa));
4370 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4371 m < &vm_page_array[vm_page_array_size],
4372 ("%s: bad pte2 %#x", __func__, pte2));
4373
4374 if (pte2_is_dirty(pte2))
4375 vm_page_dirty(m);
4376
4377 pmap->pm_stats.resident_count--;
4378 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4379 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4380 pvh = pa_to_pvh(pa);
4381 if (TAILQ_EMPTY(&pvh->pv_list))
4382 vm_page_aflag_clear(m, PGA_WRITEABLE);
4383 }
4384 pmap_unuse_pt2(pmap, pv->pv_va, free);
4385 }
4386
4387 /*
4388 * Remove all pages from specified address space this aids process
4389 * exit speeds. Also, this code is special cased for current process
4390 * only, but can have the more generic (and slightly slower) mode enabled.
4391 * This is much faster than pmap_remove in the case of running down
4392 * an entire address space.
4393 */
4394 void
pmap_remove_pages(pmap_t pmap)4395 pmap_remove_pages(pmap_t pmap)
4396 {
4397 pt1_entry_t *pte1p, pte1;
4398 pt2_entry_t *pte2p, pte2;
4399 pv_entry_t pv;
4400 struct pv_chunk *pc, *npc;
4401 struct spglist free;
4402 int field, idx;
4403 int32_t bit;
4404 uint32_t inuse, bitmask;
4405 boolean_t allfree;
4406
4407 /*
4408 * Assert that the given pmap is only active on the current
4409 * CPU. Unfortunately, we cannot block another CPU from
4410 * activating the pmap while this function is executing.
4411 */
4412 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4413 ("%s: non-current pmap %p", __func__, pmap));
4414 #if defined(SMP) && defined(INVARIANTS)
4415 {
4416 cpuset_t other_cpus;
4417
4418 sched_pin();
4419 other_cpus = pmap->pm_active;
4420 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4421 sched_unpin();
4422 KASSERT(CPU_EMPTY(&other_cpus),
4423 ("%s: pmap %p active on other cpus", __func__, pmap));
4424 }
4425 #endif
4426 SLIST_INIT(&free);
4427 rw_wlock(&pvh_global_lock);
4428 PMAP_LOCK(pmap);
4429 sched_pin();
4430 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4431 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4432 __func__, pmap, pc->pc_pmap));
4433 allfree = TRUE;
4434 for (field = 0; field < _NPCM; field++) {
4435 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4436 while (inuse != 0) {
4437 bit = ffs(inuse) - 1;
4438 bitmask = 1UL << bit;
4439 idx = field * 32 + bit;
4440 pv = &pc->pc_pventry[idx];
4441 inuse &= ~bitmask;
4442
4443 /*
4444 * Note that we cannot remove wired pages
4445 * from a process' mapping at this time
4446 */
4447 pte1p = pmap_pte1(pmap, pv->pv_va);
4448 pte1 = pte1_load(pte1p);
4449 if (pte1_is_section(pte1)) {
4450 if (pte1_is_wired(pte1)) {
4451 allfree = FALSE;
4452 continue;
4453 }
4454 pte1_clear(pte1p);
4455 pmap_remove_pte1_quick(pmap, pte1, pv,
4456 &free);
4457 }
4458 else if (pte1_is_link(pte1)) {
4459 pte2p = pt2map_entry(pv->pv_va);
4460 pte2 = pte2_load(pte2p);
4461
4462 if (!pte2_is_valid(pte2)) {
4463 printf("%s: pmap %p va %#x "
4464 "pte2 %#x\n", __func__,
4465 pmap, pv->pv_va, pte2);
4466 panic("bad pte2");
4467 }
4468
4469 if (pte2_is_wired(pte2)) {
4470 allfree = FALSE;
4471 continue;
4472 }
4473 pte2_clear(pte2p);
4474 pmap_remove_pte2_quick(pmap, pte2, pv,
4475 &free);
4476 } else {
4477 printf("%s: pmap %p va %#x pte1 %#x\n",
4478 __func__, pmap, pv->pv_va, pte1);
4479 panic("bad pte1");
4480 }
4481
4482 /* Mark free */
4483 PV_STAT(pv_entry_frees++);
4484 PV_STAT(pv_entry_spare++);
4485 pv_entry_count--;
4486 pc->pc_map[field] |= bitmask;
4487 }
4488 }
4489 if (allfree) {
4490 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4491 free_pv_chunk(pc);
4492 }
4493 }
4494 tlb_flush_all_ng_local();
4495 sched_unpin();
4496 rw_wunlock(&pvh_global_lock);
4497 PMAP_UNLOCK(pmap);
4498 vm_page_free_pages_toq(&free, false);
4499 }
4500
4501 /*
4502 * This code makes some *MAJOR* assumptions:
4503 * 1. Current pmap & pmap exists.
4504 * 2. Not wired.
4505 * 3. Read access.
4506 * 4. No L2 page table pages.
4507 * but is *MUCH* faster than pmap_enter...
4508 */
4509 static vm_page_t
pmap_enter_quick_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,vm_page_t mpt2pg)4510 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4511 vm_prot_t prot, vm_page_t mpt2pg)
4512 {
4513 pt2_entry_t *pte2p, pte2;
4514 vm_paddr_t pa;
4515 struct spglist free;
4516 uint32_t l2prot;
4517
4518 KASSERT(!VA_IS_CLEANMAP(va) ||
4519 (m->oflags & VPO_UNMANAGED) != 0,
4520 ("%s: managed mapping within the clean submap", __func__));
4521 rw_assert(&pvh_global_lock, RA_WLOCKED);
4522 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4523
4524 /*
4525 * In the case that a L2 page table page is not
4526 * resident, we are creating it here.
4527 */
4528 if (va < VM_MAXUSER_ADDRESS) {
4529 u_int pte1_idx;
4530 pt1_entry_t pte1, *pte1p;
4531 vm_paddr_t pt2_pa;
4532
4533 /*
4534 * Get L1 page table things.
4535 */
4536 pte1_idx = pte1_index(va);
4537 pte1p = pmap_pte1(pmap, va);
4538 pte1 = pte1_load(pte1p);
4539
4540 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4541 /*
4542 * Each of NPT2_IN_PG L2 page tables on the page can
4543 * come here. Make sure that associated L1 page table
4544 * link is established.
4545 *
4546 * QQQ: It comes that we don't establish all links to
4547 * L2 page tables for newly allocated L2 page
4548 * tables page.
4549 */
4550 KASSERT(!pte1_is_section(pte1),
4551 ("%s: pte1 %#x is section", __func__, pte1));
4552 if (!pte1_is_link(pte1)) {
4553 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4554 pte1_idx);
4555 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4556 }
4557 pt2_wirecount_inc(mpt2pg, pte1_idx);
4558 } else {
4559 /*
4560 * If the L2 page table page is mapped, we just
4561 * increment the hold count, and activate it.
4562 */
4563 if (pte1_is_section(pte1)) {
4564 return (NULL);
4565 } else if (pte1_is_link(pte1)) {
4566 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4567 pt2_wirecount_inc(mpt2pg, pte1_idx);
4568 } else {
4569 mpt2pg = _pmap_allocpte2(pmap, va,
4570 PMAP_ENTER_NOSLEEP);
4571 if (mpt2pg == NULL)
4572 return (NULL);
4573 }
4574 }
4575 } else {
4576 mpt2pg = NULL;
4577 }
4578
4579 /*
4580 * This call to pt2map_entry() makes the assumption that we are
4581 * entering the page into the current pmap. In order to support
4582 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4583 * But that isn't as quick as pt2map_entry().
4584 */
4585 pte2p = pt2map_entry(va);
4586 pte2 = pte2_load(pte2p);
4587 if (pte2_is_valid(pte2)) {
4588 if (mpt2pg != NULL) {
4589 /*
4590 * Remove extra pte2 reference
4591 */
4592 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4593 mpt2pg = NULL;
4594 }
4595 return (NULL);
4596 }
4597
4598 /*
4599 * Enter on the PV list if part of our managed memory.
4600 */
4601 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4602 !pmap_try_insert_pv_entry(pmap, va, m)) {
4603 if (mpt2pg != NULL) {
4604 SLIST_INIT(&free);
4605 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4606 pmap_tlb_flush(pmap, va);
4607 vm_page_free_pages_toq(&free, false);
4608 }
4609
4610 mpt2pg = NULL;
4611 }
4612 return (NULL);
4613 }
4614
4615 /*
4616 * Increment counters
4617 */
4618 pmap->pm_stats.resident_count++;
4619
4620 /*
4621 * Now validate mapping with RO protection
4622 */
4623 pa = VM_PAGE_TO_PHYS(m);
4624 l2prot = PTE2_RO | PTE2_NM;
4625 if (va < VM_MAXUSER_ADDRESS)
4626 l2prot |= PTE2_U | PTE2_NG;
4627 if ((prot & VM_PROT_EXECUTE) == 0)
4628 l2prot |= PTE2_NX;
4629 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4630 /*
4631 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4632 * is set. QQQ: For more info, see comments in pmap_enter().
4633 */
4634 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4635 }
4636 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4637
4638 return (mpt2pg);
4639 }
4640
4641 void
pmap_enter_quick(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)4642 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4643 {
4644
4645 rw_wlock(&pvh_global_lock);
4646 PMAP_LOCK(pmap);
4647 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4648 rw_wunlock(&pvh_global_lock);
4649 PMAP_UNLOCK(pmap);
4650 }
4651
4652 /*
4653 * Tries to create a read- and/or execute-only 1 MB page mapping. Returns
4654 * true if successful. Returns false if (1) a mapping already exists at the
4655 * specified virtual address or (2) a PV entry cannot be allocated without
4656 * reclaiming another PV entry.
4657 */
4658 static bool
pmap_enter_1mpage(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)4659 pmap_enter_1mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4660 {
4661 pt1_entry_t pte1;
4662 vm_paddr_t pa;
4663
4664 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4665 pa = VM_PAGE_TO_PHYS(m);
4666 pte1 = PTE1(pa, PTE1_NM | PTE1_RO, ATTR_TO_L1(vm_page_pte2_attr(m)));
4667 if ((prot & VM_PROT_EXECUTE) == 0)
4668 pte1 |= PTE1_NX;
4669 if (va < VM_MAXUSER_ADDRESS)
4670 pte1 |= PTE1_U;
4671 if (pmap != kernel_pmap)
4672 pte1 |= PTE1_NG;
4673 return (pmap_enter_pte1(pmap, va, pte1, PMAP_ENTER_NOSLEEP |
4674 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m) == KERN_SUCCESS);
4675 }
4676
4677 /*
4678 * Tries to create the specified 1 MB page mapping. Returns KERN_SUCCESS if
4679 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4680 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4681 * a mapping already exists at the specified virtual address. Returns
4682 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NORECLAIM was specified and PV entry
4683 * allocation failed.
4684 */
4685 static int
pmap_enter_pte1(pmap_t pmap,vm_offset_t va,pt1_entry_t pte1,u_int flags,vm_page_t m)4686 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags,
4687 vm_page_t m)
4688 {
4689 struct spglist free;
4690 pt1_entry_t opte1, *pte1p;
4691 pt2_entry_t pte2, *pte2p;
4692 vm_offset_t cur, end;
4693 vm_page_t mt;
4694
4695 rw_assert(&pvh_global_lock, RA_WLOCKED);
4696 KASSERT((pte1 & (PTE1_NM | PTE1_RO)) == 0 ||
4697 (pte1 & (PTE1_NM | PTE1_RO)) == (PTE1_NM | PTE1_RO),
4698 ("%s: pte1 has inconsistent NM and RO attributes", __func__));
4699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4700 pte1p = pmap_pte1(pmap, va);
4701 opte1 = pte1_load(pte1p);
4702 if (pte1_is_valid(opte1)) {
4703 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4704 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4705 __func__, va, pmap);
4706 return (KERN_FAILURE);
4707 }
4708 /* Break the existing mapping(s). */
4709 SLIST_INIT(&free);
4710 if (pte1_is_section(opte1)) {
4711 /*
4712 * If the section resulted from a promotion, then a
4713 * reserved PT page could be freed.
4714 */
4715 pmap_remove_pte1(pmap, pte1p, va, &free);
4716 } else {
4717 sched_pin();
4718 end = va + PTE1_SIZE;
4719 for (cur = va, pte2p = pmap_pte2_quick(pmap, va);
4720 cur != end; cur += PAGE_SIZE, pte2p++) {
4721 pte2 = pte2_load(pte2p);
4722 if (!pte2_is_valid(pte2))
4723 continue;
4724 if (pmap_remove_pte2(pmap, pte2p, cur, &free))
4725 break;
4726 }
4727 sched_unpin();
4728 }
4729 vm_page_free_pages_toq(&free, false);
4730 }
4731 if ((m->oflags & VPO_UNMANAGED) == 0) {
4732 /*
4733 * Abort this mapping if its PV entry could not be created.
4734 */
4735 if (!pmap_pv_insert_pte1(pmap, va, pte1, flags)) {
4736 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4737 __func__, va, pmap);
4738 return (KERN_RESOURCE_SHORTAGE);
4739 }
4740 if ((pte1 & PTE1_RO) == 0) {
4741 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4742 vm_page_aflag_set(mt, PGA_WRITEABLE);
4743 }
4744 }
4745
4746 /*
4747 * Increment counters.
4748 */
4749 if (pte1_is_wired(pte1))
4750 pmap->pm_stats.wired_count += PTE1_SIZE / PAGE_SIZE;
4751 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4752
4753 /*
4754 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4755 * is set. QQQ: For more info, see comments in pmap_enter().
4756 */
4757 if ((pte1 & PTE1_NX) == 0 && m->md.pat_mode == VM_MEMATTR_WB_WA &&
4758 pmap != kernel_pmap && (!pte1_is_section(opte1) ||
4759 pte1_pa(opte1) != VM_PAGE_TO_PHYS(m) || (opte1 & PTE2_NX) != 0))
4760 cache_icache_sync_fresh(va, VM_PAGE_TO_PHYS(m), PTE1_SIZE);
4761
4762 /*
4763 * Map the section.
4764 */
4765 pte1_store(pte1p, pte1);
4766
4767 pmap_pte1_mappings++;
4768 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4769 pmap);
4770 return (KERN_SUCCESS);
4771 }
4772
4773 /*
4774 * Maps a sequence of resident pages belonging to the same object.
4775 * The sequence begins with the given page m_start. This page is
4776 * mapped at the given virtual address start. Each subsequent page is
4777 * mapped at a virtual address that is offset from start by the same
4778 * amount as the page is offset from m_start within the object. The
4779 * last page in the sequence is the page with the largest offset from
4780 * m_start that can be mapped at a virtual address less than the given
4781 * virtual address end. Not every virtual page between start and end
4782 * is mapped; only those for which a resident page exists with the
4783 * corresponding offset from m_start are mapped.
4784 */
4785 void
pmap_enter_object(pmap_t pmap,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)4786 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4787 vm_page_t m_start, vm_prot_t prot)
4788 {
4789 vm_offset_t va;
4790 vm_page_t m, mpt2pg;
4791 vm_pindex_t diff, psize;
4792
4793 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4794 __func__, pmap, start, end, m_start, prot));
4795
4796 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4797 psize = atop(end - start);
4798 mpt2pg = NULL;
4799 m = m_start;
4800 rw_wlock(&pvh_global_lock);
4801 PMAP_LOCK(pmap);
4802 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4803 va = start + ptoa(diff);
4804 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4805 m->psind == 1 && sp_enabled &&
4806 pmap_enter_1mpage(pmap, va, m, prot))
4807 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4808 else
4809 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4810 mpt2pg);
4811 m = TAILQ_NEXT(m, listq);
4812 }
4813 rw_wunlock(&pvh_global_lock);
4814 PMAP_UNLOCK(pmap);
4815 }
4816
4817 /*
4818 * This code maps large physical mmap regions into the
4819 * processor address space. Note that some shortcuts
4820 * are taken, but the code works.
4821 */
4822 void
pmap_object_init_pt(pmap_t pmap,vm_offset_t addr,vm_object_t object,vm_pindex_t pindex,vm_size_t size)4823 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4824 vm_pindex_t pindex, vm_size_t size)
4825 {
4826 pt1_entry_t *pte1p;
4827 vm_paddr_t pa, pte2_pa;
4828 vm_page_t p;
4829 vm_memattr_t pat_mode;
4830 u_int l1attr, l1prot;
4831
4832 VM_OBJECT_ASSERT_WLOCKED(object);
4833 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4834 ("%s: non-device object", __func__));
4835 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4836 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4837 return;
4838 p = vm_page_lookup(object, pindex);
4839 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4840 ("%s: invalid page %p", __func__, p));
4841 pat_mode = p->md.pat_mode;
4842
4843 /*
4844 * Abort the mapping if the first page is not physically
4845 * aligned to a 1MB page boundary.
4846 */
4847 pte2_pa = VM_PAGE_TO_PHYS(p);
4848 if (pte2_pa & PTE1_OFFSET)
4849 return;
4850
4851 /*
4852 * Skip the first page. Abort the mapping if the rest of
4853 * the pages are not physically contiguous or have differing
4854 * memory attributes.
4855 */
4856 p = TAILQ_NEXT(p, listq);
4857 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4858 pa += PAGE_SIZE) {
4859 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4860 ("%s: invalid page %p", __func__, p));
4861 if (pa != VM_PAGE_TO_PHYS(p) ||
4862 pat_mode != p->md.pat_mode)
4863 return;
4864 p = TAILQ_NEXT(p, listq);
4865 }
4866
4867 /*
4868 * Map using 1MB pages.
4869 *
4870 * QQQ: Well, we are mapping a section, so same condition must
4871 * be hold like during promotion. It looks that only RW mapping
4872 * is done here, so readonly mapping must be done elsewhere.
4873 */
4874 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4875 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4876 PMAP_LOCK(pmap);
4877 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4878 pte1p = pmap_pte1(pmap, addr);
4879 if (!pte1_is_valid(pte1_load(pte1p))) {
4880 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4881 pmap->pm_stats.resident_count += PTE1_SIZE /
4882 PAGE_SIZE;
4883 pmap_pte1_mappings++;
4884 }
4885 /* Else continue on if the PTE1 is already valid. */
4886 addr += PTE1_SIZE;
4887 }
4888 PMAP_UNLOCK(pmap);
4889 }
4890 }
4891
4892 /*
4893 * Do the things to protect a 1mpage in a process.
4894 */
4895 static void
pmap_protect_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t sva,vm_prot_t prot)4896 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4897 vm_prot_t prot)
4898 {
4899 pt1_entry_t npte1, opte1;
4900 vm_offset_t eva, va;
4901 vm_page_t m;
4902
4903 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4904 KASSERT((sva & PTE1_OFFSET) == 0,
4905 ("%s: sva is not 1mpage aligned", __func__));
4906
4907 opte1 = npte1 = pte1_load(pte1p);
4908 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4909 eva = sva + PTE1_SIZE;
4910 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4911 va < eva; va += PAGE_SIZE, m++)
4912 vm_page_dirty(m);
4913 }
4914 if ((prot & VM_PROT_WRITE) == 0)
4915 npte1 |= PTE1_RO | PTE1_NM;
4916 if ((prot & VM_PROT_EXECUTE) == 0)
4917 npte1 |= PTE1_NX;
4918
4919 /*
4920 * QQQ: Herein, execute permission is never set.
4921 * It only can be cleared. So, no icache
4922 * syncing is needed.
4923 */
4924
4925 if (npte1 != opte1) {
4926 pte1_store(pte1p, npte1);
4927 pmap_tlb_flush(pmap, sva);
4928 }
4929 }
4930
4931 /*
4932 * Set the physical protection on the
4933 * specified range of this map as requested.
4934 */
4935 void
pmap_protect(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)4936 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4937 {
4938 boolean_t pv_lists_locked;
4939 vm_offset_t nextva;
4940 pt1_entry_t *pte1p, pte1;
4941 pt2_entry_t *pte2p, opte2, npte2;
4942
4943 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4944 if (prot == VM_PROT_NONE) {
4945 pmap_remove(pmap, sva, eva);
4946 return;
4947 }
4948
4949 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4950 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4951 return;
4952
4953 if (pmap_is_current(pmap))
4954 pv_lists_locked = FALSE;
4955 else {
4956 pv_lists_locked = TRUE;
4957 resume:
4958 rw_wlock(&pvh_global_lock);
4959 sched_pin();
4960 }
4961
4962 PMAP_LOCK(pmap);
4963 for (; sva < eva; sva = nextva) {
4964 /*
4965 * Calculate address for next L2 page table.
4966 */
4967 nextva = pte1_trunc(sva + PTE1_SIZE);
4968 if (nextva < sva)
4969 nextva = eva;
4970
4971 pte1p = pmap_pte1(pmap, sva);
4972 pte1 = pte1_load(pte1p);
4973
4974 /*
4975 * Weed out invalid mappings. Note: we assume that L1 page
4976 * page table is always allocated, and in kernel virtual.
4977 */
4978 if (pte1 == 0)
4979 continue;
4980
4981 if (pte1_is_section(pte1)) {
4982 /*
4983 * Are we protecting the entire large page? If not,
4984 * demote the mapping and fall through.
4985 */
4986 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4987 pmap_protect_pte1(pmap, pte1p, sva, prot);
4988 continue;
4989 } else {
4990 if (!pv_lists_locked) {
4991 pv_lists_locked = TRUE;
4992 if (!rw_try_wlock(&pvh_global_lock)) {
4993 PMAP_UNLOCK(pmap);
4994 goto resume;
4995 }
4996 sched_pin();
4997 }
4998 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4999 /*
5000 * The large page mapping
5001 * was destroyed.
5002 */
5003 continue;
5004 }
5005 #ifdef INVARIANTS
5006 else {
5007 /* Update pte1 after demotion */
5008 pte1 = pte1_load(pte1p);
5009 }
5010 #endif
5011 }
5012 }
5013
5014 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5015 " is not link", __func__, pmap, sva, pte1, pte1p));
5016
5017 /*
5018 * Limit our scan to either the end of the va represented
5019 * by the current L2 page table page, or to the end of the
5020 * range being protected.
5021 */
5022 if (nextva > eva)
5023 nextva = eva;
5024
5025 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5026 sva += PAGE_SIZE) {
5027 vm_page_t m;
5028
5029 opte2 = npte2 = pte2_load(pte2p);
5030 if (!pte2_is_valid(opte2))
5031 continue;
5032
5033 if ((prot & VM_PROT_WRITE) == 0) {
5034 if (pte2_is_managed(opte2) &&
5035 pte2_is_dirty(opte2)) {
5036 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
5037 vm_page_dirty(m);
5038 }
5039 npte2 |= PTE2_RO | PTE2_NM;
5040 }
5041
5042 if ((prot & VM_PROT_EXECUTE) == 0)
5043 npte2 |= PTE2_NX;
5044
5045 /*
5046 * QQQ: Herein, execute permission is never set.
5047 * It only can be cleared. So, no icache
5048 * syncing is needed.
5049 */
5050
5051 if (npte2 != opte2) {
5052 pte2_store(pte2p, npte2);
5053 pmap_tlb_flush(pmap, sva);
5054 }
5055 }
5056 }
5057 if (pv_lists_locked) {
5058 sched_unpin();
5059 rw_wunlock(&pvh_global_lock);
5060 }
5061 PMAP_UNLOCK(pmap);
5062 }
5063
5064 /*
5065 * pmap_pvh_wired_mappings:
5066 *
5067 * Return the updated number "count" of managed mappings that are wired.
5068 */
5069 static int
pmap_pvh_wired_mappings(struct md_page * pvh,int count)5070 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5071 {
5072 pmap_t pmap;
5073 pt1_entry_t pte1;
5074 pt2_entry_t pte2;
5075 pv_entry_t pv;
5076
5077 rw_assert(&pvh_global_lock, RA_WLOCKED);
5078 sched_pin();
5079 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5080 pmap = PV_PMAP(pv);
5081 PMAP_LOCK(pmap);
5082 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5083 if (pte1_is_section(pte1)) {
5084 if (pte1_is_wired(pte1))
5085 count++;
5086 } else {
5087 KASSERT(pte1_is_link(pte1),
5088 ("%s: pte1 %#x is not link", __func__, pte1));
5089 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5090 if (pte2_is_wired(pte2))
5091 count++;
5092 }
5093 PMAP_UNLOCK(pmap);
5094 }
5095 sched_unpin();
5096 return (count);
5097 }
5098
5099 /*
5100 * pmap_page_wired_mappings:
5101 *
5102 * Return the number of managed mappings to the given physical page
5103 * that are wired.
5104 */
5105 int
pmap_page_wired_mappings(vm_page_t m)5106 pmap_page_wired_mappings(vm_page_t m)
5107 {
5108 int count;
5109
5110 count = 0;
5111 if ((m->oflags & VPO_UNMANAGED) != 0)
5112 return (count);
5113 rw_wlock(&pvh_global_lock);
5114 count = pmap_pvh_wired_mappings(&m->md, count);
5115 if ((m->flags & PG_FICTITIOUS) == 0) {
5116 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5117 count);
5118 }
5119 rw_wunlock(&pvh_global_lock);
5120 return (count);
5121 }
5122
5123 /*
5124 * Returns TRUE if any of the given mappings were used to modify
5125 * physical memory. Otherwise, returns FALSE. Both page and 1mpage
5126 * mappings are supported.
5127 */
5128 static boolean_t
pmap_is_modified_pvh(struct md_page * pvh)5129 pmap_is_modified_pvh(struct md_page *pvh)
5130 {
5131 pv_entry_t pv;
5132 pt1_entry_t pte1;
5133 pt2_entry_t pte2;
5134 pmap_t pmap;
5135 boolean_t rv;
5136
5137 rw_assert(&pvh_global_lock, RA_WLOCKED);
5138 rv = FALSE;
5139 sched_pin();
5140 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5141 pmap = PV_PMAP(pv);
5142 PMAP_LOCK(pmap);
5143 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5144 if (pte1_is_section(pte1)) {
5145 rv = pte1_is_dirty(pte1);
5146 } else {
5147 KASSERT(pte1_is_link(pte1),
5148 ("%s: pte1 %#x is not link", __func__, pte1));
5149 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5150 rv = pte2_is_dirty(pte2);
5151 }
5152 PMAP_UNLOCK(pmap);
5153 if (rv)
5154 break;
5155 }
5156 sched_unpin();
5157 return (rv);
5158 }
5159
5160 /*
5161 * pmap_is_modified:
5162 *
5163 * Return whether or not the specified physical page was modified
5164 * in any physical maps.
5165 */
5166 boolean_t
pmap_is_modified(vm_page_t m)5167 pmap_is_modified(vm_page_t m)
5168 {
5169 boolean_t rv;
5170
5171 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5172 ("%s: page %p is not managed", __func__, m));
5173
5174 /*
5175 * If the page is not busied then this check is racy.
5176 */
5177 if (!pmap_page_is_write_mapped(m))
5178 return (FALSE);
5179 rw_wlock(&pvh_global_lock);
5180 rv = pmap_is_modified_pvh(&m->md) ||
5181 ((m->flags & PG_FICTITIOUS) == 0 &&
5182 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5183 rw_wunlock(&pvh_global_lock);
5184 return (rv);
5185 }
5186
5187 /*
5188 * pmap_is_prefaultable:
5189 *
5190 * Return whether or not the specified virtual address is eligible
5191 * for prefault.
5192 */
5193 boolean_t
pmap_is_prefaultable(pmap_t pmap,vm_offset_t addr)5194 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5195 {
5196 pt1_entry_t pte1;
5197 pt2_entry_t pte2;
5198 boolean_t rv;
5199
5200 rv = FALSE;
5201 PMAP_LOCK(pmap);
5202 pte1 = pte1_load(pmap_pte1(pmap, addr));
5203 if (pte1_is_link(pte1)) {
5204 pte2 = pte2_load(pt2map_entry(addr));
5205 rv = !pte2_is_valid(pte2) ;
5206 }
5207 PMAP_UNLOCK(pmap);
5208 return (rv);
5209 }
5210
5211 /*
5212 * Returns TRUE if any of the given mappings were referenced and FALSE
5213 * otherwise. Both page and 1mpage mappings are supported.
5214 */
5215 static boolean_t
pmap_is_referenced_pvh(struct md_page * pvh)5216 pmap_is_referenced_pvh(struct md_page *pvh)
5217 {
5218
5219 pv_entry_t pv;
5220 pt1_entry_t pte1;
5221 pt2_entry_t pte2;
5222 pmap_t pmap;
5223 boolean_t rv;
5224
5225 rw_assert(&pvh_global_lock, RA_WLOCKED);
5226 rv = FALSE;
5227 sched_pin();
5228 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5229 pmap = PV_PMAP(pv);
5230 PMAP_LOCK(pmap);
5231 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5232 if (pte1_is_section(pte1)) {
5233 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5234 } else {
5235 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5236 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5237 }
5238 PMAP_UNLOCK(pmap);
5239 if (rv)
5240 break;
5241 }
5242 sched_unpin();
5243 return (rv);
5244 }
5245
5246 /*
5247 * pmap_is_referenced:
5248 *
5249 * Return whether or not the specified physical page was referenced
5250 * in any physical maps.
5251 */
5252 boolean_t
pmap_is_referenced(vm_page_t m)5253 pmap_is_referenced(vm_page_t m)
5254 {
5255 boolean_t rv;
5256
5257 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5258 ("%s: page %p is not managed", __func__, m));
5259 rw_wlock(&pvh_global_lock);
5260 rv = pmap_is_referenced_pvh(&m->md) ||
5261 ((m->flags & PG_FICTITIOUS) == 0 &&
5262 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5263 rw_wunlock(&pvh_global_lock);
5264 return (rv);
5265 }
5266
5267 /*
5268 * pmap_ts_referenced:
5269 *
5270 * Return a count of reference bits for a page, clearing those bits.
5271 * It is not necessary for every reference bit to be cleared, but it
5272 * is necessary that 0 only be returned when there are truly no
5273 * reference bits set.
5274 *
5275 * As an optimization, update the page's dirty field if a modified bit is
5276 * found while counting reference bits. This opportunistic update can be
5277 * performed at low cost and can eliminate the need for some future calls
5278 * to pmap_is_modified(). However, since this function stops after
5279 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5280 * dirty pages. Those dirty pages will only be detected by a future call
5281 * to pmap_is_modified().
5282 */
5283 int
pmap_ts_referenced(vm_page_t m)5284 pmap_ts_referenced(vm_page_t m)
5285 {
5286 struct md_page *pvh;
5287 pv_entry_t pv, pvf;
5288 pmap_t pmap;
5289 pt1_entry_t *pte1p, opte1;
5290 pt2_entry_t *pte2p, opte2;
5291 vm_paddr_t pa;
5292 int rtval = 0;
5293
5294 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5295 ("%s: page %p is not managed", __func__, m));
5296 pa = VM_PAGE_TO_PHYS(m);
5297 pvh = pa_to_pvh(pa);
5298 rw_wlock(&pvh_global_lock);
5299 sched_pin();
5300 if ((m->flags & PG_FICTITIOUS) != 0 ||
5301 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5302 goto small_mappings;
5303 pv = pvf;
5304 do {
5305 pmap = PV_PMAP(pv);
5306 PMAP_LOCK(pmap);
5307 pte1p = pmap_pte1(pmap, pv->pv_va);
5308 opte1 = pte1_load(pte1p);
5309 if (pte1_is_dirty(opte1)) {
5310 /*
5311 * Although "opte1" is mapping a 1MB page, because
5312 * this function is called at a 4KB page granularity,
5313 * we only update the 4KB page under test.
5314 */
5315 vm_page_dirty(m);
5316 }
5317 if ((opte1 & PTE1_A) != 0) {
5318 /*
5319 * Since this reference bit is shared by 256 4KB pages,
5320 * it should not be cleared every time it is tested.
5321 * Apply a simple "hash" function on the physical page
5322 * number, the virtual section number, and the pmap
5323 * address to select one 4KB page out of the 256
5324 * on which testing the reference bit will result
5325 * in clearing that bit. This function is designed
5326 * to avoid the selection of the same 4KB page
5327 * for every 1MB page mapping.
5328 *
5329 * On demotion, a mapping that hasn't been referenced
5330 * is simply destroyed. To avoid the possibility of a
5331 * subsequent page fault on a demoted wired mapping,
5332 * always leave its reference bit set. Moreover,
5333 * since the section is wired, the current state of
5334 * its reference bit won't affect page replacement.
5335 */
5336 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5337 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5338 !pte1_is_wired(opte1)) {
5339 pte1_clear_bit(pte1p, PTE1_A);
5340 pmap_tlb_flush(pmap, pv->pv_va);
5341 }
5342 rtval++;
5343 }
5344 PMAP_UNLOCK(pmap);
5345 /* Rotate the PV list if it has more than one entry. */
5346 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5347 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5348 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5349 }
5350 if (rtval >= PMAP_TS_REFERENCED_MAX)
5351 goto out;
5352 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5353 small_mappings:
5354 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5355 goto out;
5356 pv = pvf;
5357 do {
5358 pmap = PV_PMAP(pv);
5359 PMAP_LOCK(pmap);
5360 pte1p = pmap_pte1(pmap, pv->pv_va);
5361 KASSERT(pte1_is_link(pte1_load(pte1p)),
5362 ("%s: not found a link in page %p's pv list", __func__, m));
5363
5364 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5365 opte2 = pte2_load(pte2p);
5366 if (pte2_is_dirty(opte2))
5367 vm_page_dirty(m);
5368 if ((opte2 & PTE2_A) != 0) {
5369 pte2_clear_bit(pte2p, PTE2_A);
5370 pmap_tlb_flush(pmap, pv->pv_va);
5371 rtval++;
5372 }
5373 PMAP_UNLOCK(pmap);
5374 /* Rotate the PV list if it has more than one entry. */
5375 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5376 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5377 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5378 }
5379 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5380 PMAP_TS_REFERENCED_MAX);
5381 out:
5382 sched_unpin();
5383 rw_wunlock(&pvh_global_lock);
5384 return (rtval);
5385 }
5386
5387 /*
5388 * Clear the wired attribute from the mappings for the specified range of
5389 * addresses in the given pmap. Every valid mapping within that range
5390 * must have the wired attribute set. In contrast, invalid mappings
5391 * cannot have the wired attribute set, so they are ignored.
5392 *
5393 * The wired attribute of the page table entry is not a hardware feature,
5394 * so there is no need to invalidate any TLB entries.
5395 */
5396 void
pmap_unwire(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)5397 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5398 {
5399 vm_offset_t nextva;
5400 pt1_entry_t *pte1p, pte1;
5401 pt2_entry_t *pte2p, pte2;
5402 boolean_t pv_lists_locked;
5403
5404 if (pmap_is_current(pmap))
5405 pv_lists_locked = FALSE;
5406 else {
5407 pv_lists_locked = TRUE;
5408 resume:
5409 rw_wlock(&pvh_global_lock);
5410 sched_pin();
5411 }
5412 PMAP_LOCK(pmap);
5413 for (; sva < eva; sva = nextva) {
5414 nextva = pte1_trunc(sva + PTE1_SIZE);
5415 if (nextva < sva)
5416 nextva = eva;
5417
5418 pte1p = pmap_pte1(pmap, sva);
5419 pte1 = pte1_load(pte1p);
5420
5421 /*
5422 * Weed out invalid mappings. Note: we assume that L1 page
5423 * page table is always allocated, and in kernel virtual.
5424 */
5425 if (pte1 == 0)
5426 continue;
5427
5428 if (pte1_is_section(pte1)) {
5429 if (!pte1_is_wired(pte1))
5430 panic("%s: pte1 %#x not wired", __func__, pte1);
5431
5432 /*
5433 * Are we unwiring the entire large page? If not,
5434 * demote the mapping and fall through.
5435 */
5436 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5437 pte1_clear_bit(pte1p, PTE1_W);
5438 pmap->pm_stats.wired_count -= PTE1_SIZE /
5439 PAGE_SIZE;
5440 continue;
5441 } else {
5442 if (!pv_lists_locked) {
5443 pv_lists_locked = TRUE;
5444 if (!rw_try_wlock(&pvh_global_lock)) {
5445 PMAP_UNLOCK(pmap);
5446 /* Repeat sva. */
5447 goto resume;
5448 }
5449 sched_pin();
5450 }
5451 if (!pmap_demote_pte1(pmap, pte1p, sva))
5452 panic("%s: demotion failed", __func__);
5453 #ifdef INVARIANTS
5454 else {
5455 /* Update pte1 after demotion */
5456 pte1 = pte1_load(pte1p);
5457 }
5458 #endif
5459 }
5460 }
5461
5462 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5463 " is not link", __func__, pmap, sva, pte1, pte1p));
5464
5465 /*
5466 * Limit our scan to either the end of the va represented
5467 * by the current L2 page table page, or to the end of the
5468 * range being protected.
5469 */
5470 if (nextva > eva)
5471 nextva = eva;
5472
5473 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5474 sva += PAGE_SIZE) {
5475 pte2 = pte2_load(pte2p);
5476 if (!pte2_is_valid(pte2))
5477 continue;
5478 if (!pte2_is_wired(pte2))
5479 panic("%s: pte2 %#x is missing PTE2_W",
5480 __func__, pte2);
5481
5482 /*
5483 * PTE2_W must be cleared atomically. Although the pmap
5484 * lock synchronizes access to PTE2_W, another processor
5485 * could be changing PTE2_NM and/or PTE2_A concurrently.
5486 */
5487 pte2_clear_bit(pte2p, PTE2_W);
5488 pmap->pm_stats.wired_count--;
5489 }
5490 }
5491 if (pv_lists_locked) {
5492 sched_unpin();
5493 rw_wunlock(&pvh_global_lock);
5494 }
5495 PMAP_UNLOCK(pmap);
5496 }
5497
5498 /*
5499 * Clear the write and modified bits in each of the given page's mappings.
5500 */
5501 void
pmap_remove_write(vm_page_t m)5502 pmap_remove_write(vm_page_t m)
5503 {
5504 struct md_page *pvh;
5505 pv_entry_t next_pv, pv;
5506 pmap_t pmap;
5507 pt1_entry_t *pte1p;
5508 pt2_entry_t *pte2p, opte2;
5509 vm_offset_t va;
5510
5511 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5512 ("%s: page %p is not managed", __func__, m));
5513 vm_page_assert_busied(m);
5514
5515 if (!pmap_page_is_write_mapped(m))
5516 return;
5517 rw_wlock(&pvh_global_lock);
5518 sched_pin();
5519 if ((m->flags & PG_FICTITIOUS) != 0)
5520 goto small_mappings;
5521 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5522 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5523 va = pv->pv_va;
5524 pmap = PV_PMAP(pv);
5525 PMAP_LOCK(pmap);
5526 pte1p = pmap_pte1(pmap, va);
5527 if (!(pte1_load(pte1p) & PTE1_RO))
5528 (void)pmap_demote_pte1(pmap, pte1p, va);
5529 PMAP_UNLOCK(pmap);
5530 }
5531 small_mappings:
5532 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5533 pmap = PV_PMAP(pv);
5534 PMAP_LOCK(pmap);
5535 pte1p = pmap_pte1(pmap, pv->pv_va);
5536 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5537 " a section in page %p's pv list", __func__, m));
5538 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5539 opte2 = pte2_load(pte2p);
5540 if (!(opte2 & PTE2_RO)) {
5541 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5542 if (pte2_is_dirty(opte2))
5543 vm_page_dirty(m);
5544 pmap_tlb_flush(pmap, pv->pv_va);
5545 }
5546 PMAP_UNLOCK(pmap);
5547 }
5548 vm_page_aflag_clear(m, PGA_WRITEABLE);
5549 sched_unpin();
5550 rw_wunlock(&pvh_global_lock);
5551 }
5552
5553 /*
5554 * Apply the given advice to the specified range of addresses within the
5555 * given pmap. Depending on the advice, clear the referenced and/or
5556 * modified flags in each mapping and set the mapped page's dirty field.
5557 */
5558 void
pmap_advise(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,int advice)5559 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5560 {
5561 pt1_entry_t *pte1p, opte1;
5562 pt2_entry_t *pte2p, pte2;
5563 vm_offset_t pdnxt;
5564 vm_page_t m;
5565 boolean_t pv_lists_locked;
5566
5567 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5568 return;
5569 if (pmap_is_current(pmap))
5570 pv_lists_locked = FALSE;
5571 else {
5572 pv_lists_locked = TRUE;
5573 resume:
5574 rw_wlock(&pvh_global_lock);
5575 sched_pin();
5576 }
5577 PMAP_LOCK(pmap);
5578 for (; sva < eva; sva = pdnxt) {
5579 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5580 if (pdnxt < sva)
5581 pdnxt = eva;
5582 pte1p = pmap_pte1(pmap, sva);
5583 opte1 = pte1_load(pte1p);
5584 if (!pte1_is_valid(opte1)) /* XXX */
5585 continue;
5586 else if (pte1_is_section(opte1)) {
5587 if (!pte1_is_managed(opte1))
5588 continue;
5589 if (!pv_lists_locked) {
5590 pv_lists_locked = TRUE;
5591 if (!rw_try_wlock(&pvh_global_lock)) {
5592 PMAP_UNLOCK(pmap);
5593 goto resume;
5594 }
5595 sched_pin();
5596 }
5597 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5598 /*
5599 * The large page mapping was destroyed.
5600 */
5601 continue;
5602 }
5603
5604 /*
5605 * Unless the page mappings are wired, remove the
5606 * mapping to a single page so that a subsequent
5607 * access may repromote. Since the underlying L2 page
5608 * table is fully populated, this removal never
5609 * frees a L2 page table page.
5610 */
5611 if (!pte1_is_wired(opte1)) {
5612 pte2p = pmap_pte2_quick(pmap, sva);
5613 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5614 ("%s: invalid PTE2", __func__));
5615 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5616 }
5617 }
5618 if (pdnxt > eva)
5619 pdnxt = eva;
5620 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5621 sva += PAGE_SIZE) {
5622 pte2 = pte2_load(pte2p);
5623 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5624 continue;
5625 else if (pte2_is_dirty(pte2)) {
5626 if (advice == MADV_DONTNEED) {
5627 /*
5628 * Future calls to pmap_is_modified()
5629 * can be avoided by making the page
5630 * dirty now.
5631 */
5632 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5633 vm_page_dirty(m);
5634 }
5635 pte2_set_bit(pte2p, PTE2_NM);
5636 pte2_clear_bit(pte2p, PTE2_A);
5637 } else if ((pte2 & PTE2_A) != 0)
5638 pte2_clear_bit(pte2p, PTE2_A);
5639 else
5640 continue;
5641 pmap_tlb_flush(pmap, sva);
5642 }
5643 }
5644 if (pv_lists_locked) {
5645 sched_unpin();
5646 rw_wunlock(&pvh_global_lock);
5647 }
5648 PMAP_UNLOCK(pmap);
5649 }
5650
5651 /*
5652 * Clear the modify bits on the specified physical page.
5653 */
5654 void
pmap_clear_modify(vm_page_t m)5655 pmap_clear_modify(vm_page_t m)
5656 {
5657 struct md_page *pvh;
5658 pv_entry_t next_pv, pv;
5659 pmap_t pmap;
5660 pt1_entry_t *pte1p, opte1;
5661 pt2_entry_t *pte2p, opte2;
5662 vm_offset_t va;
5663
5664 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5665 ("%s: page %p is not managed", __func__, m));
5666 vm_page_assert_busied(m);
5667
5668 if (!pmap_page_is_write_mapped(m))
5669 return;
5670 rw_wlock(&pvh_global_lock);
5671 sched_pin();
5672 if ((m->flags & PG_FICTITIOUS) != 0)
5673 goto small_mappings;
5674 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5675 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5676 va = pv->pv_va;
5677 pmap = PV_PMAP(pv);
5678 PMAP_LOCK(pmap);
5679 pte1p = pmap_pte1(pmap, va);
5680 opte1 = pte1_load(pte1p);
5681 if (!(opte1 & PTE1_RO)) {
5682 if (pmap_demote_pte1(pmap, pte1p, va) &&
5683 !pte1_is_wired(opte1)) {
5684 /*
5685 * Write protect the mapping to a
5686 * single page so that a subsequent
5687 * write access may repromote.
5688 */
5689 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5690 pte2p = pmap_pte2_quick(pmap, va);
5691 opte2 = pte2_load(pte2p);
5692 if ((opte2 & PTE2_V)) {
5693 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5694 vm_page_dirty(m);
5695 pmap_tlb_flush(pmap, va);
5696 }
5697 }
5698 }
5699 PMAP_UNLOCK(pmap);
5700 }
5701 small_mappings:
5702 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5703 pmap = PV_PMAP(pv);
5704 PMAP_LOCK(pmap);
5705 pte1p = pmap_pte1(pmap, pv->pv_va);
5706 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5707 " a section in page %p's pv list", __func__, m));
5708 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5709 if (pte2_is_dirty(pte2_load(pte2p))) {
5710 pte2_set_bit(pte2p, PTE2_NM);
5711 pmap_tlb_flush(pmap, pv->pv_va);
5712 }
5713 PMAP_UNLOCK(pmap);
5714 }
5715 sched_unpin();
5716 rw_wunlock(&pvh_global_lock);
5717 }
5718
5719 /*
5720 * Sets the memory attribute for the specified page.
5721 */
5722 void
pmap_page_set_memattr(vm_page_t m,vm_memattr_t ma)5723 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5724 {
5725 pt2_entry_t *cmap2_pte2p;
5726 vm_memattr_t oma;
5727 vm_paddr_t pa;
5728 struct pcpu *pc;
5729
5730 oma = m->md.pat_mode;
5731 m->md.pat_mode = ma;
5732
5733 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5734 VM_PAGE_TO_PHYS(m), oma, ma);
5735 if ((m->flags & PG_FICTITIOUS) != 0)
5736 return;
5737 #if 0
5738 /*
5739 * If "m" is a normal page, flush it from the cache.
5740 *
5741 * First, try to find an existing mapping of the page by sf
5742 * buffer. sf_buf_invalidate_cache() modifies mapping and
5743 * flushes the cache.
5744 */
5745 if (sf_buf_invalidate_cache(m, oma))
5746 return;
5747 #endif
5748 /*
5749 * If page is not mapped by sf buffer, map the page
5750 * transient and do invalidation.
5751 */
5752 if (ma != oma) {
5753 pa = VM_PAGE_TO_PHYS(m);
5754 sched_pin();
5755 pc = get_pcpu();
5756 cmap2_pte2p = pc->pc_cmap2_pte2p;
5757 mtx_lock(&pc->pc_cmap_lock);
5758 if (pte2_load(cmap2_pte2p) != 0)
5759 panic("%s: CMAP2 busy", __func__);
5760 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5761 vm_memattr_to_pte2(ma)));
5762 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5763 pte2_clear(cmap2_pte2p);
5764 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5765 sched_unpin();
5766 mtx_unlock(&pc->pc_cmap_lock);
5767 }
5768 }
5769
5770 /*
5771 * Miscellaneous support routines follow
5772 */
5773
5774 /*
5775 * Returns TRUE if the given page is mapped individually or as part of
5776 * a 1mpage. Otherwise, returns FALSE.
5777 */
5778 boolean_t
pmap_page_is_mapped(vm_page_t m)5779 pmap_page_is_mapped(vm_page_t m)
5780 {
5781 boolean_t rv;
5782
5783 if ((m->oflags & VPO_UNMANAGED) != 0)
5784 return (FALSE);
5785 rw_wlock(&pvh_global_lock);
5786 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5787 ((m->flags & PG_FICTITIOUS) == 0 &&
5788 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5789 rw_wunlock(&pvh_global_lock);
5790 return (rv);
5791 }
5792
5793 /*
5794 * Returns true if the pmap's pv is one of the first
5795 * 16 pvs linked to from this page. This count may
5796 * be changed upwards or downwards in the future; it
5797 * is only necessary that true be returned for a small
5798 * subset of pmaps for proper page aging.
5799 */
5800 boolean_t
pmap_page_exists_quick(pmap_t pmap,vm_page_t m)5801 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5802 {
5803 struct md_page *pvh;
5804 pv_entry_t pv;
5805 int loops = 0;
5806 boolean_t rv;
5807
5808 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5809 ("%s: page %p is not managed", __func__, m));
5810 rv = FALSE;
5811 rw_wlock(&pvh_global_lock);
5812 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5813 if (PV_PMAP(pv) == pmap) {
5814 rv = TRUE;
5815 break;
5816 }
5817 loops++;
5818 if (loops >= 16)
5819 break;
5820 }
5821 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5822 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5823 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5824 if (PV_PMAP(pv) == pmap) {
5825 rv = TRUE;
5826 break;
5827 }
5828 loops++;
5829 if (loops >= 16)
5830 break;
5831 }
5832 }
5833 rw_wunlock(&pvh_global_lock);
5834 return (rv);
5835 }
5836
5837 /*
5838 * pmap_zero_page zeros the specified hardware page by mapping
5839 * the page into KVM and using bzero to clear its contents.
5840 */
5841 void
pmap_zero_page(vm_page_t m)5842 pmap_zero_page(vm_page_t m)
5843 {
5844 pt2_entry_t *cmap2_pte2p;
5845 struct pcpu *pc;
5846
5847 sched_pin();
5848 pc = get_pcpu();
5849 cmap2_pte2p = pc->pc_cmap2_pte2p;
5850 mtx_lock(&pc->pc_cmap_lock);
5851 if (pte2_load(cmap2_pte2p) != 0)
5852 panic("%s: CMAP2 busy", __func__);
5853 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5854 vm_page_pte2_attr(m)));
5855 pagezero(pc->pc_cmap2_addr);
5856 pte2_clear(cmap2_pte2p);
5857 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5858 sched_unpin();
5859 mtx_unlock(&pc->pc_cmap_lock);
5860 }
5861
5862 /*
5863 * pmap_zero_page_area zeros the specified hardware page by mapping
5864 * the page into KVM and using bzero to clear its contents.
5865 *
5866 * off and size may not cover an area beyond a single hardware page.
5867 */
5868 void
pmap_zero_page_area(vm_page_t m,int off,int size)5869 pmap_zero_page_area(vm_page_t m, int off, int size)
5870 {
5871 pt2_entry_t *cmap2_pte2p;
5872 struct pcpu *pc;
5873
5874 sched_pin();
5875 pc = get_pcpu();
5876 cmap2_pte2p = pc->pc_cmap2_pte2p;
5877 mtx_lock(&pc->pc_cmap_lock);
5878 if (pte2_load(cmap2_pte2p) != 0)
5879 panic("%s: CMAP2 busy", __func__);
5880 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5881 vm_page_pte2_attr(m)));
5882 if (off == 0 && size == PAGE_SIZE)
5883 pagezero(pc->pc_cmap2_addr);
5884 else
5885 bzero(pc->pc_cmap2_addr + off, size);
5886 pte2_clear(cmap2_pte2p);
5887 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5888 sched_unpin();
5889 mtx_unlock(&pc->pc_cmap_lock);
5890 }
5891
5892 /*
5893 * pmap_copy_page copies the specified (machine independent)
5894 * page by mapping the page into virtual memory and using
5895 * bcopy to copy the page, one machine dependent page at a
5896 * time.
5897 */
5898 void
pmap_copy_page(vm_page_t src,vm_page_t dst)5899 pmap_copy_page(vm_page_t src, vm_page_t dst)
5900 {
5901 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5902 struct pcpu *pc;
5903
5904 sched_pin();
5905 pc = get_pcpu();
5906 cmap1_pte2p = pc->pc_cmap1_pte2p;
5907 cmap2_pte2p = pc->pc_cmap2_pte2p;
5908 mtx_lock(&pc->pc_cmap_lock);
5909 if (pte2_load(cmap1_pte2p) != 0)
5910 panic("%s: CMAP1 busy", __func__);
5911 if (pte2_load(cmap2_pte2p) != 0)
5912 panic("%s: CMAP2 busy", __func__);
5913 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5914 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5915 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5916 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5917 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5918 pte2_clear(cmap1_pte2p);
5919 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5920 pte2_clear(cmap2_pte2p);
5921 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5922 sched_unpin();
5923 mtx_unlock(&pc->pc_cmap_lock);
5924 }
5925
5926 int unmapped_buf_allowed = 1;
5927
5928 void
pmap_copy_pages(vm_page_t ma[],vm_offset_t a_offset,vm_page_t mb[],vm_offset_t b_offset,int xfersize)5929 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5930 vm_offset_t b_offset, int xfersize)
5931 {
5932 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5933 vm_page_t a_pg, b_pg;
5934 char *a_cp, *b_cp;
5935 vm_offset_t a_pg_offset, b_pg_offset;
5936 struct pcpu *pc;
5937 int cnt;
5938
5939 sched_pin();
5940 pc = get_pcpu();
5941 cmap1_pte2p = pc->pc_cmap1_pte2p;
5942 cmap2_pte2p = pc->pc_cmap2_pte2p;
5943 mtx_lock(&pc->pc_cmap_lock);
5944 if (pte2_load(cmap1_pte2p) != 0)
5945 panic("pmap_copy_pages: CMAP1 busy");
5946 if (pte2_load(cmap2_pte2p) != 0)
5947 panic("pmap_copy_pages: CMAP2 busy");
5948 while (xfersize > 0) {
5949 a_pg = ma[a_offset >> PAGE_SHIFT];
5950 a_pg_offset = a_offset & PAGE_MASK;
5951 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5952 b_pg = mb[b_offset >> PAGE_SHIFT];
5953 b_pg_offset = b_offset & PAGE_MASK;
5954 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5955 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5956 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5957 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
5958 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5959 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5960 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
5961 a_cp = pc->pc_cmap1_addr + a_pg_offset;
5962 b_cp = pc->pc_cmap2_addr + b_pg_offset;
5963 bcopy(a_cp, b_cp, cnt);
5964 a_offset += cnt;
5965 b_offset += cnt;
5966 xfersize -= cnt;
5967 }
5968 pte2_clear(cmap1_pte2p);
5969 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5970 pte2_clear(cmap2_pte2p);
5971 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5972 sched_unpin();
5973 mtx_unlock(&pc->pc_cmap_lock);
5974 }
5975
5976 vm_offset_t
pmap_quick_enter_page(vm_page_t m)5977 pmap_quick_enter_page(vm_page_t m)
5978 {
5979 struct pcpu *pc;
5980 pt2_entry_t *pte2p;
5981
5982 critical_enter();
5983 pc = get_pcpu();
5984 pte2p = pc->pc_qmap_pte2p;
5985
5986 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5987
5988 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5989 vm_page_pte2_attr(m)));
5990 return (pc->pc_qmap_addr);
5991 }
5992
5993 void
pmap_quick_remove_page(vm_offset_t addr)5994 pmap_quick_remove_page(vm_offset_t addr)
5995 {
5996 struct pcpu *pc;
5997 pt2_entry_t *pte2p;
5998
5999 pc = get_pcpu();
6000 pte2p = pc->pc_qmap_pte2p;
6001
6002 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
6003 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
6004
6005 pte2_clear(pte2p);
6006 tlb_flush(pc->pc_qmap_addr);
6007 critical_exit();
6008 }
6009
6010 /*
6011 * Copy the range specified by src_addr/len
6012 * from the source map to the range dst_addr/len
6013 * in the destination map.
6014 *
6015 * This routine is only advisory and need not do anything.
6016 */
6017 void
pmap_copy(pmap_t dst_pmap,pmap_t src_pmap,vm_offset_t dst_addr,vm_size_t len,vm_offset_t src_addr)6018 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6019 vm_offset_t src_addr)
6020 {
6021 struct spglist free;
6022 vm_offset_t addr;
6023 vm_offset_t end_addr = src_addr + len;
6024 vm_offset_t nextva;
6025
6026 if (dst_addr != src_addr)
6027 return;
6028
6029 if (!pmap_is_current(src_pmap))
6030 return;
6031
6032 rw_wlock(&pvh_global_lock);
6033 if (dst_pmap < src_pmap) {
6034 PMAP_LOCK(dst_pmap);
6035 PMAP_LOCK(src_pmap);
6036 } else {
6037 PMAP_LOCK(src_pmap);
6038 PMAP_LOCK(dst_pmap);
6039 }
6040 sched_pin();
6041 for (addr = src_addr; addr < end_addr; addr = nextva) {
6042 pt2_entry_t *src_pte2p, *dst_pte2p;
6043 vm_page_t dst_mpt2pg, src_mpt2pg;
6044 pt1_entry_t src_pte1;
6045 u_int pte1_idx;
6046
6047 KASSERT(addr < VM_MAXUSER_ADDRESS,
6048 ("%s: invalid to pmap_copy page tables", __func__));
6049
6050 nextva = pte1_trunc(addr + PTE1_SIZE);
6051 if (nextva < addr)
6052 nextva = end_addr;
6053
6054 pte1_idx = pte1_index(addr);
6055 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6056 if (pte1_is_section(src_pte1)) {
6057 if ((addr & PTE1_OFFSET) != 0 ||
6058 (addr + PTE1_SIZE) > end_addr)
6059 continue;
6060 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6061 (!pte1_is_managed(src_pte1) ||
6062 pmap_pv_insert_pte1(dst_pmap, addr, src_pte1,
6063 PMAP_ENTER_NORECLAIM))) {
6064 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6065 ~PTE1_W;
6066 dst_pmap->pm_stats.resident_count +=
6067 PTE1_SIZE / PAGE_SIZE;
6068 pmap_pte1_mappings++;
6069 }
6070 continue;
6071 } else if (!pte1_is_link(src_pte1))
6072 continue;
6073
6074 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6075
6076 /*
6077 * We leave PT2s to be linked from PT1 even if they are not
6078 * referenced until all PT2s in a page are without reference.
6079 *
6080 * QQQ: It could be changed ...
6081 */
6082 #if 0 /* single_pt2_link_is_cleared */
6083 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6084 ("%s: source page table page is unused", __func__));
6085 #else
6086 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6087 continue;
6088 #endif
6089 if (nextva > end_addr)
6090 nextva = end_addr;
6091
6092 src_pte2p = pt2map_entry(addr);
6093 while (addr < nextva) {
6094 pt2_entry_t temp_pte2;
6095 temp_pte2 = pte2_load(src_pte2p);
6096 /*
6097 * we only virtual copy managed pages
6098 */
6099 if (pte2_is_managed(temp_pte2)) {
6100 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6101 PMAP_ENTER_NOSLEEP);
6102 if (dst_mpt2pg == NULL)
6103 goto out;
6104 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6105 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6106 pmap_try_insert_pv_entry(dst_pmap, addr,
6107 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6108 /*
6109 * Clear the wired, modified, and
6110 * accessed (referenced) bits
6111 * during the copy.
6112 */
6113 temp_pte2 &= ~(PTE2_W | PTE2_A);
6114 temp_pte2 |= PTE2_NM;
6115 pte2_store(dst_pte2p, temp_pte2);
6116 dst_pmap->pm_stats.resident_count++;
6117 } else {
6118 SLIST_INIT(&free);
6119 if (pmap_unwire_pt2(dst_pmap, addr,
6120 dst_mpt2pg, &free)) {
6121 pmap_tlb_flush(dst_pmap, addr);
6122 vm_page_free_pages_toq(&free,
6123 false);
6124 }
6125 goto out;
6126 }
6127 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6128 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6129 break;
6130 }
6131 addr += PAGE_SIZE;
6132 src_pte2p++;
6133 }
6134 }
6135 out:
6136 sched_unpin();
6137 rw_wunlock(&pvh_global_lock);
6138 PMAP_UNLOCK(src_pmap);
6139 PMAP_UNLOCK(dst_pmap);
6140 }
6141
6142 /*
6143 * Increase the starting virtual address of the given mapping if a
6144 * different alignment might result in more section mappings.
6145 */
6146 void
pmap_align_superpage(vm_object_t object,vm_ooffset_t offset,vm_offset_t * addr,vm_size_t size)6147 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6148 vm_offset_t *addr, vm_size_t size)
6149 {
6150 vm_offset_t pte1_offset;
6151
6152 if (size < PTE1_SIZE)
6153 return;
6154 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6155 offset += ptoa(object->pg_color);
6156 pte1_offset = offset & PTE1_OFFSET;
6157 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6158 (*addr & PTE1_OFFSET) == pte1_offset)
6159 return;
6160 if ((*addr & PTE1_OFFSET) < pte1_offset)
6161 *addr = pte1_trunc(*addr) + pte1_offset;
6162 else
6163 *addr = pte1_roundup(*addr) + pte1_offset;
6164 }
6165
6166 void
pmap_activate(struct thread * td)6167 pmap_activate(struct thread *td)
6168 {
6169 pmap_t pmap, oldpmap;
6170 u_int cpuid, ttb;
6171
6172 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6173
6174 critical_enter();
6175 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6176 oldpmap = PCPU_GET(curpmap);
6177 cpuid = PCPU_GET(cpuid);
6178
6179 #if defined(SMP)
6180 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6181 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6182 #else
6183 CPU_CLR(cpuid, &oldpmap->pm_active);
6184 CPU_SET(cpuid, &pmap->pm_active);
6185 #endif
6186
6187 ttb = pmap_ttb_get(pmap);
6188
6189 /*
6190 * pmap_activate is for the current thread on the current cpu
6191 */
6192 td->td_pcb->pcb_pagedir = ttb;
6193 cp15_ttbr_set(ttb);
6194 PCPU_SET(curpmap, pmap);
6195 critical_exit();
6196 }
6197
6198 void
pmap_active_cpus(pmap_t pmap,cpuset_t * res)6199 pmap_active_cpus(pmap_t pmap, cpuset_t *res)
6200 {
6201 *res = pmap->pm_active;
6202 }
6203
6204 /*
6205 * Perform the pmap work for mincore(2). If the page is not both referenced and
6206 * modified by this pmap, returns its physical address so that the caller can
6207 * find other mappings.
6208 */
6209 int
pmap_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)6210 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6211 {
6212 pt1_entry_t *pte1p, pte1;
6213 pt2_entry_t *pte2p, pte2;
6214 vm_paddr_t pa;
6215 bool managed;
6216 int val;
6217
6218 PMAP_LOCK(pmap);
6219 pte1p = pmap_pte1(pmap, addr);
6220 pte1 = pte1_load(pte1p);
6221 if (pte1_is_section(pte1)) {
6222 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6223 managed = pte1_is_managed(pte1);
6224 val = MINCORE_PSIND(1) | MINCORE_INCORE;
6225 if (pte1_is_dirty(pte1))
6226 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6227 if (pte1 & PTE1_A)
6228 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6229 } else if (pte1_is_link(pte1)) {
6230 pte2p = pmap_pte2(pmap, addr);
6231 pte2 = pte2_load(pte2p);
6232 pmap_pte2_release(pte2p);
6233 pa = pte2_pa(pte2);
6234 managed = pte2_is_managed(pte2);
6235 val = MINCORE_INCORE;
6236 if (pte2_is_dirty(pte2))
6237 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6238 if (pte2 & PTE2_A)
6239 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6240 } else {
6241 managed = false;
6242 val = 0;
6243 }
6244 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6245 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6246 *pap = pa;
6247 }
6248 PMAP_UNLOCK(pmap);
6249 return (val);
6250 }
6251
6252 void
pmap_kenter_device(vm_offset_t va,vm_size_t size,vm_paddr_t pa)6253 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6254 {
6255 vm_offset_t sva;
6256 uint32_t l2attr;
6257
6258 KASSERT((size & PAGE_MASK) == 0,
6259 ("%s: device mapping not page-sized", __func__));
6260
6261 sva = va;
6262 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6263 while (size != 0) {
6264 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6265 va += PAGE_SIZE;
6266 pa += PAGE_SIZE;
6267 size -= PAGE_SIZE;
6268 }
6269 tlb_flush_range(sva, va - sva);
6270 }
6271
6272 void
pmap_kremove_device(vm_offset_t va,vm_size_t size)6273 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6274 {
6275 vm_offset_t sva;
6276
6277 KASSERT((size & PAGE_MASK) == 0,
6278 ("%s: device mapping not page-sized", __func__));
6279
6280 sva = va;
6281 while (size != 0) {
6282 pmap_kremove(va);
6283 va += PAGE_SIZE;
6284 size -= PAGE_SIZE;
6285 }
6286 tlb_flush_range(sva, va - sva);
6287 }
6288
6289 void
pmap_set_pcb_pagedir(pmap_t pmap,struct pcb * pcb)6290 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6291 {
6292
6293 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6294 }
6295
6296 /*
6297 * Clean L1 data cache range by physical address.
6298 * The range must be within a single page.
6299 */
6300 static void
pmap_dcache_wb_pou(vm_paddr_t pa,vm_size_t size,uint32_t attr)6301 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6302 {
6303 pt2_entry_t *cmap2_pte2p;
6304 struct pcpu *pc;
6305
6306 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6307 ("%s: not on single page", __func__));
6308
6309 sched_pin();
6310 pc = get_pcpu();
6311 cmap2_pte2p = pc->pc_cmap2_pte2p;
6312 mtx_lock(&pc->pc_cmap_lock);
6313 if (pte2_load(cmap2_pte2p) != 0)
6314 panic("%s: CMAP2 busy", __func__);
6315 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6316 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6317 pte2_clear(cmap2_pte2p);
6318 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6319 sched_unpin();
6320 mtx_unlock(&pc->pc_cmap_lock);
6321 }
6322
6323 /*
6324 * Sync instruction cache range which is not mapped yet.
6325 */
6326 void
cache_icache_sync_fresh(vm_offset_t va,vm_paddr_t pa,vm_size_t size)6327 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6328 {
6329 uint32_t len, offset;
6330 vm_page_t m;
6331
6332 /* Write back d-cache on given address range. */
6333 offset = pa & PAGE_MASK;
6334 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6335 len = min(PAGE_SIZE - offset, size);
6336 m = PHYS_TO_VM_PAGE(pa);
6337 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6338 __func__, pa));
6339 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6340 }
6341 /*
6342 * I-cache is VIPT. Only way how to flush all virtual mappings
6343 * on given physical address is to invalidate all i-cache.
6344 */
6345 icache_inv_all();
6346 }
6347
6348 void
pmap_sync_icache(pmap_t pmap,vm_offset_t va,vm_size_t size)6349 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6350 {
6351
6352 /* Write back d-cache on given address range. */
6353 if (va >= VM_MIN_KERNEL_ADDRESS) {
6354 dcache_wb_pou(va, size);
6355 } else {
6356 uint32_t len, offset;
6357 vm_paddr_t pa;
6358 vm_page_t m;
6359
6360 offset = va & PAGE_MASK;
6361 for ( ; size != 0; size -= len, va += len, offset = 0) {
6362 pa = pmap_extract(pmap, va); /* offset is preserved */
6363 len = min(PAGE_SIZE - offset, size);
6364 m = PHYS_TO_VM_PAGE(pa);
6365 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6366 __func__, pa));
6367 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6368 }
6369 }
6370 /*
6371 * I-cache is VIPT. Only way how to flush all virtual mappings
6372 * on given physical address is to invalidate all i-cache.
6373 */
6374 icache_inv_all();
6375 }
6376
6377 /*
6378 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6379 * depends on the fact that given range size is a power of 2.
6380 */
6381 CTASSERT(powerof2(NB_IN_PT1));
6382 CTASSERT(powerof2(PT2MAP_SIZE));
6383
6384 #define IN_RANGE2(addr, start, size) \
6385 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6386
6387 /*
6388 * Handle access and R/W emulation faults.
6389 */
6390 int
pmap_fault(pmap_t pmap,vm_offset_t far,uint32_t fsr,int idx,bool usermode)6391 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6392 {
6393 pt1_entry_t *pte1p, pte1;
6394 pt2_entry_t *pte2p, pte2;
6395
6396 if (pmap == NULL)
6397 pmap = kernel_pmap;
6398
6399 /*
6400 * In kernel, we should never get abort with FAR which is in range of
6401 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6402 * and print out a useful abort message and even get to the debugger
6403 * otherwise it likely ends with never ending loop of aborts.
6404 */
6405 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6406 /*
6407 * All L1 tables should always be mapped and present.
6408 * However, we check only current one herein. For user mode,
6409 * only permission abort from malicious user is not fatal.
6410 * And alignment abort as it may have higher priority.
6411 */
6412 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6413 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6414 __func__, pmap, pmap->pm_pt1, far);
6415 panic("%s: pm_pt1 abort", __func__);
6416 }
6417 return (KERN_INVALID_ADDRESS);
6418 }
6419 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6420 /*
6421 * PT2MAP should be always mapped and present in current
6422 * L1 table. However, only existing L2 tables are mapped
6423 * in PT2MAP. For user mode, only L2 translation abort and
6424 * permission abort from malicious user is not fatal.
6425 * And alignment abort as it may have higher priority.
6426 */
6427 if (!usermode || (idx != FAULT_ALIGN &&
6428 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6429 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6430 __func__, pmap, PT2MAP, far);
6431 panic("%s: PT2MAP abort", __func__);
6432 }
6433 return (KERN_INVALID_ADDRESS);
6434 }
6435
6436 /*
6437 * A pmap lock is used below for handling of access and R/W emulation
6438 * aborts. They were handled by atomic operations before so some
6439 * analysis of new situation is needed to answer the following question:
6440 * Is it safe to use the lock even for these aborts?
6441 *
6442 * There may happen two cases in general:
6443 *
6444 * (1) Aborts while the pmap lock is locked already - this should not
6445 * happen as pmap lock is not recursive. However, under pmap lock only
6446 * internal kernel data should be accessed and such data should be
6447 * mapped with A bit set and NM bit cleared. If double abort happens,
6448 * then a mapping of data which has caused it must be fixed. Further,
6449 * all new mappings are always made with A bit set and the bit can be
6450 * cleared only on managed mappings.
6451 *
6452 * (2) Aborts while another lock(s) is/are locked - this already can
6453 * happen. However, there is no difference here if it's either access or
6454 * R/W emulation abort, or if it's some other abort.
6455 */
6456
6457 PMAP_LOCK(pmap);
6458 #ifdef INVARIANTS
6459 pte1 = pte1_load(pmap_pte1(pmap, far));
6460 if (pte1_is_link(pte1)) {
6461 /*
6462 * Check in advance that associated L2 page table is mapped into
6463 * PT2MAP space. Note that faulty access to not mapped L2 page
6464 * table is caught in more general check above where "far" is
6465 * checked that it does not lay in PT2MAP space. Note also that
6466 * L1 page table and PT2TAB always exist and are mapped.
6467 */
6468 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6469 if (!pte2_is_valid(pte2))
6470 panic("%s: missing L2 page table (%p, %#x)",
6471 __func__, pmap, far);
6472 }
6473 #endif
6474 #ifdef SMP
6475 /*
6476 * Special treatment is due to break-before-make approach done when
6477 * pte1 is updated for userland mapping during section promotion or
6478 * demotion. If not caught here, pmap_enter() can find a section
6479 * mapping on faulting address. That is not allowed.
6480 */
6481 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6482 PMAP_UNLOCK(pmap);
6483 return (KERN_SUCCESS);
6484 }
6485 #endif
6486 /*
6487 * Accesss bits for page and section. Note that the entry
6488 * is not in TLB yet, so TLB flush is not necessary.
6489 *
6490 * QQQ: This is hardware emulation, we do not call userret()
6491 * for aborts from user mode.
6492 */
6493 if (idx == FAULT_ACCESS_L2) {
6494 pte1 = pte1_load(pmap_pte1(pmap, far));
6495 if (pte1_is_link(pte1)) {
6496 /* L2 page table should exist and be mapped. */
6497 pte2p = pt2map_entry(far);
6498 pte2 = pte2_load(pte2p);
6499 if (pte2_is_valid(pte2)) {
6500 pte2_store(pte2p, pte2 | PTE2_A);
6501 PMAP_UNLOCK(pmap);
6502 return (KERN_SUCCESS);
6503 }
6504 } else {
6505 /*
6506 * We got L2 access fault but PTE1 is not a link.
6507 * Probably some race happened, do nothing.
6508 */
6509 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6510 __func__, pmap, far);
6511 PMAP_UNLOCK(pmap);
6512 return (KERN_SUCCESS);
6513 }
6514 }
6515 if (idx == FAULT_ACCESS_L1) {
6516 pte1p = pmap_pte1(pmap, far);
6517 pte1 = pte1_load(pte1p);
6518 if (pte1_is_section(pte1)) {
6519 pte1_store(pte1p, pte1 | PTE1_A);
6520 PMAP_UNLOCK(pmap);
6521 return (KERN_SUCCESS);
6522 } else {
6523 /*
6524 * We got L1 access fault but PTE1 is not section
6525 * mapping. Probably some race happened, do nothing.
6526 */
6527 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6528 __func__, pmap, far);
6529 PMAP_UNLOCK(pmap);
6530 return (KERN_SUCCESS);
6531 }
6532 }
6533
6534 /*
6535 * Handle modify bits for page and section. Note that the modify
6536 * bit is emulated by software. So PTEx_RO is software read only
6537 * bit and PTEx_NM flag is real hardware read only bit.
6538 *
6539 * QQQ: This is hardware emulation, we do not call userret()
6540 * for aborts from user mode.
6541 */
6542 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6543 pte1 = pte1_load(pmap_pte1(pmap, far));
6544 if (pte1_is_link(pte1)) {
6545 /* L2 page table should exist and be mapped. */
6546 pte2p = pt2map_entry(far);
6547 pte2 = pte2_load(pte2p);
6548 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6549 (pte2 & PTE2_NM)) {
6550 pte2_store(pte2p, pte2 & ~PTE2_NM);
6551 tlb_flush(trunc_page(far));
6552 PMAP_UNLOCK(pmap);
6553 return (KERN_SUCCESS);
6554 }
6555 } else {
6556 /*
6557 * We got L2 permission fault but PTE1 is not a link.
6558 * Probably some race happened, do nothing.
6559 */
6560 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6561 __func__, pmap, far);
6562 PMAP_UNLOCK(pmap);
6563 return (KERN_SUCCESS);
6564 }
6565 }
6566 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6567 pte1p = pmap_pte1(pmap, far);
6568 pte1 = pte1_load(pte1p);
6569 if (pte1_is_section(pte1)) {
6570 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6571 pte1_store(pte1p, pte1 & ~PTE1_NM);
6572 tlb_flush(pte1_trunc(far));
6573 PMAP_UNLOCK(pmap);
6574 return (KERN_SUCCESS);
6575 }
6576 } else {
6577 /*
6578 * We got L1 permission fault but PTE1 is not section
6579 * mapping. Probably some race happened, do nothing.
6580 */
6581 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6582 __func__, pmap, far);
6583 PMAP_UNLOCK(pmap);
6584 return (KERN_SUCCESS);
6585 }
6586 }
6587
6588 /*
6589 * QQQ: The previous code, mainly fast handling of access and
6590 * modify bits aborts, could be moved to ASM. Now we are
6591 * starting to deal with not fast aborts.
6592 */
6593 PMAP_UNLOCK(pmap);
6594 return (KERN_FAILURE);
6595 }
6596
6597 #if defined(PMAP_DEBUG)
6598 /*
6599 * Reusing of KVA used in pmap_zero_page function !!!
6600 */
6601 static void
pmap_zero_page_check(vm_page_t m)6602 pmap_zero_page_check(vm_page_t m)
6603 {
6604 pt2_entry_t *cmap2_pte2p;
6605 uint32_t *p, *end;
6606 struct pcpu *pc;
6607
6608 sched_pin();
6609 pc = get_pcpu();
6610 cmap2_pte2p = pc->pc_cmap2_pte2p;
6611 mtx_lock(&pc->pc_cmap_lock);
6612 if (pte2_load(cmap2_pte2p) != 0)
6613 panic("%s: CMAP2 busy", __func__);
6614 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6615 vm_page_pte2_attr(m)));
6616 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6617 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6618 if (*p != 0)
6619 panic("%s: page %p not zero, va: %p", __func__, m,
6620 pc->pc_cmap2_addr);
6621 pte2_clear(cmap2_pte2p);
6622 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6623 sched_unpin();
6624 mtx_unlock(&pc->pc_cmap_lock);
6625 }
6626
6627 int
pmap_pid_dump(int pid)6628 pmap_pid_dump(int pid)
6629 {
6630 pmap_t pmap;
6631 struct proc *p;
6632 int npte2 = 0;
6633 int i, j, index;
6634
6635 sx_slock(&allproc_lock);
6636 FOREACH_PROC_IN_SYSTEM(p) {
6637 if (p->p_pid != pid || p->p_vmspace == NULL)
6638 continue;
6639 index = 0;
6640 pmap = vmspace_pmap(p->p_vmspace);
6641 for (i = 0; i < NPTE1_IN_PT1; i++) {
6642 pt1_entry_t pte1;
6643 pt2_entry_t *pte2p, pte2;
6644 vm_offset_t base, va;
6645 vm_paddr_t pa;
6646 vm_page_t m;
6647
6648 base = i << PTE1_SHIFT;
6649 pte1 = pte1_load(&pmap->pm_pt1[i]);
6650
6651 if (pte1_is_section(pte1)) {
6652 /*
6653 * QQQ: Do something here!
6654 */
6655 } else if (pte1_is_link(pte1)) {
6656 for (j = 0; j < NPTE2_IN_PT2; j++) {
6657 va = base + (j << PAGE_SHIFT);
6658 if (va >= VM_MIN_KERNEL_ADDRESS) {
6659 if (index) {
6660 index = 0;
6661 printf("\n");
6662 }
6663 sx_sunlock(&allproc_lock);
6664 return (npte2);
6665 }
6666 pte2p = pmap_pte2(pmap, va);
6667 pte2 = pte2_load(pte2p);
6668 pmap_pte2_release(pte2p);
6669 if (!pte2_is_valid(pte2))
6670 continue;
6671
6672 pa = pte2_pa(pte2);
6673 m = PHYS_TO_VM_PAGE(pa);
6674 printf("va: 0x%x, pa: 0x%x, w: %d, "
6675 "f: 0x%x", va, pa,
6676 m->ref_count, m->flags);
6677 npte2++;
6678 index++;
6679 if (index >= 2) {
6680 index = 0;
6681 printf("\n");
6682 } else {
6683 printf(" ");
6684 }
6685 }
6686 }
6687 }
6688 }
6689 sx_sunlock(&allproc_lock);
6690 return (npte2);
6691 }
6692
6693 #endif
6694
6695 #ifdef DDB
6696 static pt2_entry_t *
pmap_pte2_ddb(pmap_t pmap,vm_offset_t va)6697 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6698 {
6699 pt1_entry_t pte1;
6700 vm_paddr_t pt2pg_pa;
6701
6702 pte1 = pte1_load(pmap_pte1(pmap, va));
6703 if (!pte1_is_link(pte1))
6704 return (NULL);
6705
6706 if (pmap_is_current(pmap))
6707 return (pt2map_entry(va));
6708
6709 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6710 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6711 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6712 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6713 #ifdef SMP
6714 PMAP3cpu = PCPU_GET(cpuid);
6715 #endif
6716 tlb_flush_local((vm_offset_t)PADDR3);
6717 }
6718 #ifdef SMP
6719 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6720 PMAP3cpu = PCPU_GET(cpuid);
6721 tlb_flush_local((vm_offset_t)PADDR3);
6722 }
6723 #endif
6724 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6725 }
6726
6727 static void
dump_pmap(pmap_t pmap)6728 dump_pmap(pmap_t pmap)
6729 {
6730
6731 printf("pmap %p\n", pmap);
6732 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6733 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6734 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6735 }
6736
DB_SHOW_COMMAND(pmaps,pmap_list_pmaps)6737 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6738 {
6739
6740 pmap_t pmap;
6741 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6742 dump_pmap(pmap);
6743 }
6744 }
6745
6746 static int
pte2_class(pt2_entry_t pte2)6747 pte2_class(pt2_entry_t pte2)
6748 {
6749 int cls;
6750
6751 cls = (pte2 >> 2) & 0x03;
6752 cls |= (pte2 >> 4) & 0x04;
6753 return (cls);
6754 }
6755
6756 static void
dump_section(pmap_t pmap,uint32_t pte1_idx)6757 dump_section(pmap_t pmap, uint32_t pte1_idx)
6758 {
6759 }
6760
6761 static void
dump_link(pmap_t pmap,uint32_t pte1_idx,boolean_t invalid_ok)6762 dump_link(pmap_t pmap, uint32_t pte1_idx, boolean_t invalid_ok)
6763 {
6764 uint32_t i;
6765 vm_offset_t va;
6766 pt2_entry_t *pte2p, pte2;
6767 vm_page_t m;
6768
6769 va = pte1_idx << PTE1_SHIFT;
6770 pte2p = pmap_pte2_ddb(pmap, va);
6771 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6772 pte2 = pte2_load(pte2p);
6773 if (pte2 == 0)
6774 continue;
6775 if (!pte2_is_valid(pte2)) {
6776 printf(" 0x%08X: 0x%08X", va, pte2);
6777 if (!invalid_ok)
6778 printf(" - not valid !!!");
6779 printf("\n");
6780 continue;
6781 }
6782 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6783 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6784 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6785 if (m != NULL) {
6786 printf(" v:%d w:%d f:0x%04X\n", m->valid,
6787 m->ref_count, m->flags);
6788 } else {
6789 printf("\n");
6790 }
6791 }
6792 }
6793
6794 static __inline boolean_t
is_pv_chunk_space(vm_offset_t va)6795 is_pv_chunk_space(vm_offset_t va)
6796 {
6797
6798 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6799 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6800 return (TRUE);
6801 return (FALSE);
6802 }
6803
DB_SHOW_COMMAND(pmap,pmap_pmap_print)6804 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6805 {
6806 /* XXX convert args. */
6807 pmap_t pmap = (pmap_t)addr;
6808 pt1_entry_t pte1;
6809 pt2_entry_t pte2;
6810 vm_offset_t va, eva;
6811 vm_page_t m;
6812 uint32_t i;
6813 boolean_t invalid_ok, dump_link_ok, dump_pv_chunk;
6814
6815 if (have_addr) {
6816 pmap_t pm;
6817
6818 LIST_FOREACH(pm, &allpmaps, pm_list)
6819 if (pm == pmap) break;
6820 if (pm == NULL) {
6821 printf("given pmap %p is not in allpmaps list\n", pmap);
6822 return;
6823 }
6824 } else
6825 pmap = PCPU_GET(curpmap);
6826
6827 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6828 dump_pv_chunk = FALSE; /* XXX evaluate from modif[] */
6829
6830 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6831 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6832 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6833
6834 for(i = 0; i < NPTE1_IN_PT1; i++) {
6835 pte1 = pte1_load(&pmap->pm_pt1[i]);
6836 if (pte1 == 0)
6837 continue;
6838 va = i << PTE1_SHIFT;
6839 if (va >= eva)
6840 break;
6841
6842 if (pte1_is_section(pte1)) {
6843 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6844 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6845 dump_section(pmap, i);
6846 } else if (pte1_is_link(pte1)) {
6847 dump_link_ok = TRUE;
6848 invalid_ok = FALSE;
6849 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6850 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6851 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6852 va, pte1, pte2, m);
6853 if (is_pv_chunk_space(va)) {
6854 printf(" - pv_chunk space");
6855 if (dump_pv_chunk)
6856 invalid_ok = TRUE;
6857 else
6858 dump_link_ok = FALSE;
6859 }
6860 else if (m != NULL)
6861 printf(" w:%d w2:%u", m->ref_count,
6862 pt2_wirecount_get(m, pte1_index(va)));
6863 if (pte2 == 0)
6864 printf(" !!! pt2tab entry is ZERO");
6865 else if (pte2_pa(pte1) != pte2_pa(pte2))
6866 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6867 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6868 printf("\n");
6869 if (dump_link_ok)
6870 dump_link(pmap, i, invalid_ok);
6871 } else
6872 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6873 }
6874 }
6875
6876 static void
dump_pt2tab(pmap_t pmap)6877 dump_pt2tab(pmap_t pmap)
6878 {
6879 uint32_t i;
6880 pt2_entry_t pte2;
6881 vm_offset_t va;
6882 vm_paddr_t pa;
6883 vm_page_t m;
6884
6885 printf("PT2TAB:\n");
6886 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6887 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6888 if (!pte2_is_valid(pte2))
6889 continue;
6890 va = i << PT2TAB_SHIFT;
6891 pa = pte2_pa(pte2);
6892 m = PHYS_TO_VM_PAGE(pa);
6893 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6894 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6895 if (m != NULL)
6896 printf(" , w: %d, f: 0x%04X pidx: %lld",
6897 m->ref_count, m->flags, m->pindex);
6898 printf("\n");
6899 }
6900 }
6901
DB_SHOW_COMMAND(pmap_pt2tab,pmap_pt2tab_print)6902 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6903 {
6904 /* XXX convert args. */
6905 pmap_t pmap = (pmap_t)addr;
6906 pt1_entry_t pte1;
6907 pt2_entry_t pte2;
6908 vm_offset_t va;
6909 uint32_t i, start;
6910
6911 if (have_addr) {
6912 printf("supported only on current pmap\n");
6913 return;
6914 }
6915
6916 pmap = PCPU_GET(curpmap);
6917 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6918 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6919 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6920
6921 start = pte1_index((vm_offset_t)PT2MAP);
6922 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6923 pte1 = pte1_load(&pmap->pm_pt1[i]);
6924 if (pte1 == 0)
6925 continue;
6926 va = i << PTE1_SHIFT;
6927 if (pte1_is_section(pte1)) {
6928 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6929 !!(pte1 & PTE1_S));
6930 dump_section(pmap, i);
6931 } else if (pte1_is_link(pte1)) {
6932 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6933 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6934 pte1, pte2);
6935 if (pte2 == 0)
6936 printf(" !!! pt2tab entry is ZERO\n");
6937 } else
6938 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6939 }
6940 dump_pt2tab(pmap);
6941 }
6942 #endif
6943