1 /*-
2 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * Driver for the AMD Family 15h and 17h CPU System Management Network.
29 */
30
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/conf.h>
35 #include <sys/lock.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
40 #include <sys/systm.h>
41
42 #include <machine/cpufunc.h>
43 #include <machine/cputypes.h>
44 #include <machine/md_var.h>
45 #include <machine/specialreg.h>
46
47 #include <dev/pci/pcivar.h>
48 #include <x86/pci_cfgreg.h>
49
50 #include <dev/amdsmn/amdsmn.h>
51
52 #define F15H_SMN_ADDR_REG 0xb8
53 #define F15H_SMN_DATA_REG 0xbc
54 #define F17H_SMN_ADDR_REG 0x60
55 #define F17H_SMN_DATA_REG 0x64
56
57 #define PCI_DEVICE_ID_AMD_15H_M60H_ROOT 0x1576
58 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
59 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
60 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
61 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
62 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
63 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
64 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
65 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
66
67 struct pciid;
68 struct amdsmn_softc {
69 struct mtx smn_lock;
70 const struct pciid *smn_pciid;
71 };
72
73 static const struct pciid {
74 uint16_t amdsmn_vendorid;
75 uint16_t amdsmn_deviceid;
76 uint8_t amdsmn_addr_reg;
77 uint8_t amdsmn_data_reg;
78 } amdsmn_ids[] = {
79 {
80 .amdsmn_vendorid = CPU_VENDOR_AMD,
81 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_15H_M60H_ROOT,
82 .amdsmn_addr_reg = F15H_SMN_ADDR_REG,
83 .amdsmn_data_reg = F15H_SMN_DATA_REG,
84 },
85 {
86 .amdsmn_vendorid = CPU_VENDOR_AMD,
87 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_ROOT,
88 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
89 .amdsmn_data_reg = F17H_SMN_DATA_REG,
90 },
91 {
92 .amdsmn_vendorid = CPU_VENDOR_AMD,
93 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M10H_ROOT,
94 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
95 .amdsmn_data_reg = F17H_SMN_DATA_REG,
96 },
97 {
98 .amdsmn_vendorid = CPU_VENDOR_AMD,
99 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M30H_ROOT,
100 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
101 .amdsmn_data_reg = F17H_SMN_DATA_REG,
102 },
103 {
104 .amdsmn_vendorid = CPU_VENDOR_AMD,
105 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M60H_ROOT,
106 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
107 .amdsmn_data_reg = F17H_SMN_DATA_REG,
108 },
109 {
110 .amdsmn_vendorid = CPU_VENDOR_AMD,
111 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M10H_ROOT,
112 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
113 .amdsmn_data_reg = F17H_SMN_DATA_REG,
114 },
115 {
116 .amdsmn_vendorid = CPU_VENDOR_AMD,
117 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M40H_ROOT,
118 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
119 .amdsmn_data_reg = F17H_SMN_DATA_REG,
120 },
121 {
122 .amdsmn_vendorid = CPU_VENDOR_AMD,
123 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT,
124 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
125 .amdsmn_data_reg = F17H_SMN_DATA_REG,
126 },
127 {
128 .amdsmn_vendorid = CPU_VENDOR_AMD,
129 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M70H_ROOT,
130 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
131 .amdsmn_data_reg = F17H_SMN_DATA_REG,
132 },
133 };
134
135 /*
136 * Device methods.
137 */
138 static void amdsmn_identify(driver_t *driver, device_t parent);
139 static int amdsmn_probe(device_t dev);
140 static int amdsmn_attach(device_t dev);
141 static int amdsmn_detach(device_t dev);
142
143 static device_method_t amdsmn_methods[] = {
144 /* Device interface */
145 DEVMETHOD(device_identify, amdsmn_identify),
146 DEVMETHOD(device_probe, amdsmn_probe),
147 DEVMETHOD(device_attach, amdsmn_attach),
148 DEVMETHOD(device_detach, amdsmn_detach),
149 DEVMETHOD_END
150 };
151
152 static driver_t amdsmn_driver = {
153 "amdsmn",
154 amdsmn_methods,
155 sizeof(struct amdsmn_softc),
156 };
157
158 DRIVER_MODULE(amdsmn, hostb, amdsmn_driver, NULL, NULL);
159 MODULE_VERSION(amdsmn, 1);
160 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdsmn, amdsmn_ids,
161 nitems(amdsmn_ids));
162
163 static bool
amdsmn_match(device_t parent,const struct pciid ** pciid_out)164 amdsmn_match(device_t parent, const struct pciid **pciid_out)
165 {
166 uint16_t vendor, device;
167 size_t i;
168
169 vendor = pci_get_vendor(parent);
170 device = pci_get_device(parent);
171
172 for (i = 0; i < nitems(amdsmn_ids); i++) {
173 if (vendor == amdsmn_ids[i].amdsmn_vendorid &&
174 device == amdsmn_ids[i].amdsmn_deviceid) {
175 if (pciid_out != NULL)
176 *pciid_out = &amdsmn_ids[i];
177 return (true);
178 }
179 }
180 return (false);
181 }
182
183 static void
amdsmn_identify(driver_t * driver,device_t parent)184 amdsmn_identify(driver_t *driver, device_t parent)
185 {
186 device_t child;
187
188 /* Make sure we're not being doubly invoked. */
189 if (device_find_child(parent, "amdsmn", -1) != NULL)
190 return;
191 if (!amdsmn_match(parent, NULL))
192 return;
193
194 child = device_add_child(parent, "amdsmn", -1);
195 if (child == NULL)
196 device_printf(parent, "add amdsmn child failed\n");
197 }
198
199 static int
amdsmn_probe(device_t dev)200 amdsmn_probe(device_t dev)
201 {
202 uint32_t family;
203
204 if (resource_disabled("amdsmn", 0))
205 return (ENXIO);
206 if (!amdsmn_match(device_get_parent(dev), NULL))
207 return (ENXIO);
208
209 family = CPUID_TO_FAMILY(cpu_id);
210
211 switch (family) {
212 case 0x15:
213 case 0x17:
214 case 0x19:
215 break;
216 default:
217 return (ENXIO);
218 }
219 device_set_descf(dev, "AMD Family %xh System Management Network",
220 family);
221
222 return (BUS_PROBE_GENERIC);
223 }
224
225 static int
amdsmn_attach(device_t dev)226 amdsmn_attach(device_t dev)
227 {
228 struct amdsmn_softc *sc = device_get_softc(dev);
229
230 if (!amdsmn_match(device_get_parent(dev), &sc->smn_pciid))
231 return (ENXIO);
232
233 mtx_init(&sc->smn_lock, "SMN mtx", "SMN", MTX_DEF);
234 return (0);
235 }
236
237 int
amdsmn_detach(device_t dev)238 amdsmn_detach(device_t dev)
239 {
240 struct amdsmn_softc *sc = device_get_softc(dev);
241
242 mtx_destroy(&sc->smn_lock);
243 return (0);
244 }
245
246 int
amdsmn_read(device_t dev,uint32_t addr,uint32_t * value)247 amdsmn_read(device_t dev, uint32_t addr, uint32_t *value)
248 {
249 struct amdsmn_softc *sc = device_get_softc(dev);
250 device_t parent;
251
252 parent = device_get_parent(dev);
253
254 mtx_lock(&sc->smn_lock);
255 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4);
256 *value = pci_read_config(parent, sc->smn_pciid->amdsmn_data_reg, 4);
257 mtx_unlock(&sc->smn_lock);
258
259 return (0);
260 }
261
262 int
amdsmn_write(device_t dev,uint32_t addr,uint32_t value)263 amdsmn_write(device_t dev, uint32_t addr, uint32_t value)
264 {
265 struct amdsmn_softc *sc = device_get_softc(dev);
266 device_t parent;
267
268 parent = device_get_parent(dev);
269
270 mtx_lock(&sc->smn_lock);
271 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4);
272 pci_write_config(parent, sc->smn_pciid->amdsmn_data_reg, value, 4);
273 mtx_unlock(&sc->smn_lock);
274
275 return (0);
276 }
277