1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * Marvell Xenon SDHCI controller driver.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
43 #include <sys/rman.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49
50 #include <dev/extres/regulator/regulator.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include <dev/mmc/bridge.h>
56 #include <dev/mmc/mmcbrvar.h>
57 #include <dev/mmc/mmcreg.h>
58
59 #include <dev/sdhci/sdhci.h>
60 #include <dev/sdhci/sdhci_fdt_gpio.h>
61 #include <dev/sdhci/sdhci_xenon.h>
62
63 #include "mmcbr_if.h"
64 #include "sdhci_if.h"
65
66 #include "opt_mmccam.h"
67 #include "opt_soc.h"
68
69 #define MAX_SLOTS 6
70
71 static struct ofw_compat_data compat_data[] = {
72 { "marvell,armada-3700-sdhci", 1 },
73 #ifdef SOC_MARVELL_8K
74 { "marvell,armada-cp110-sdhci", 1 },
75 { "marvell,armada-ap806-sdhci", 1 },
76 #endif
77 { NULL, 0 }
78 };
79
80 struct sdhci_xenon_softc {
81 device_t dev; /* Controller device */
82 int slot_id; /* Controller ID */
83 phandle_t node; /* FDT node */
84 uint32_t quirks; /* Chip specific quirks */
85 uint32_t caps; /* If we override SDHCI_CAPABILITIES */
86 uint32_t max_clk; /* Max possible freq */
87 struct resource *irq_res; /* IRQ resource */
88 void *intrhand; /* Interrupt handle */
89 struct sdhci_fdt_gpio *gpio; /* GPIO pins for CD detection. */
90
91 struct sdhci_slot *slot; /* SDHCI internal data */
92 struct resource *mem_res; /* Memory resource */
93
94 regulator_t reg_vqmmc; /* vqmmc-supply regulator */
95 uint8_t znr; /* PHY ZNR */
96 uint8_t zpr; /* PHY ZPR */
97 bool no_18v; /* No 1.8V support */
98 bool slow_mode; /* PHY slow mode */
99 bool wp_inverted; /* WP pin is inverted */
100 };
101
102 static uint8_t
sdhci_xenon_read_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)103 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused,
104 bus_size_t off)
105 {
106 struct sdhci_xenon_softc *sc = device_get_softc(dev);
107
108 return (bus_read_1(sc->mem_res, off));
109 }
110
111 static void
sdhci_xenon_write_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint8_t val)112 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused,
113 bus_size_t off, uint8_t val)
114 {
115 struct sdhci_xenon_softc *sc = device_get_softc(dev);
116
117 bus_write_1(sc->mem_res, off, val);
118 }
119
120 static uint16_t
sdhci_xenon_read_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)121 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused,
122 bus_size_t off)
123 {
124 struct sdhci_xenon_softc *sc = device_get_softc(dev);
125
126 return (bus_read_2(sc->mem_res, off));
127 }
128
129 static void
sdhci_xenon_write_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint16_t val)130 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused,
131 bus_size_t off, uint16_t val)
132 {
133 struct sdhci_xenon_softc *sc = device_get_softc(dev);
134
135 bus_write_2(sc->mem_res, off, val);
136 }
137
138 static uint32_t
sdhci_xenon_read_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)139 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused,
140 bus_size_t off)
141 {
142 struct sdhci_xenon_softc *sc = device_get_softc(dev);
143 uint32_t val32;
144
145 val32 = bus_read_4(sc->mem_res, off);
146 if (off == SDHCI_CAPABILITIES && sc->no_18v)
147 val32 &= ~SDHCI_CAN_VDD_180;
148
149 return (val32);
150 }
151
152 static void
sdhci_xenon_write_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t val)153 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused,
154 bus_size_t off, uint32_t val)
155 {
156 struct sdhci_xenon_softc *sc = device_get_softc(dev);
157
158 bus_write_4(sc->mem_res, off, val);
159 }
160
161 static void
sdhci_xenon_read_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)162 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
163 bus_size_t off, uint32_t *data, bus_size_t count)
164 {
165 struct sdhci_xenon_softc *sc = device_get_softc(dev);
166
167 bus_read_multi_4(sc->mem_res, off, data, count);
168 }
169
170 static void
sdhci_xenon_write_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)171 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
172 bus_size_t off, uint32_t *data, bus_size_t count)
173 {
174 struct sdhci_xenon_softc *sc = device_get_softc(dev);
175
176 bus_write_multi_4(sc->mem_res, off, data, count);
177 }
178
179 static void
sdhci_xenon_intr(void * arg)180 sdhci_xenon_intr(void *arg)
181 {
182 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg;
183
184 sdhci_generic_intr(sc->slot);
185 }
186
187 static int
sdhci_xenon_get_ro(device_t bus,device_t dev)188 sdhci_xenon_get_ro(device_t bus, device_t dev)
189 {
190 struct sdhci_xenon_softc *sc = device_get_softc(bus);
191
192 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
193 }
194
195 static bool
sdhci_xenon_get_card_present(device_t dev,struct sdhci_slot * slot)196 sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot)
197 {
198 struct sdhci_xenon_softc *sc = device_get_softc(dev);
199
200 return (sdhci_fdt_gpio_get_present(sc->gpio));
201 }
202
203 static int
sdhci_xenon_phy_init(device_t brdev,struct mmc_ios * ios)204 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
205 {
206 int i;
207 struct sdhci_xenon_softc *sc;
208 uint32_t reg;
209
210 sc = device_get_softc(brdev);
211 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
212 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT;
213 switch (ios->timing) {
214 case bus_timing_normal:
215 case bus_timing_hs:
216 case bus_timing_uhs_sdr12:
217 case bus_timing_uhs_sdr25:
218 case bus_timing_uhs_sdr50:
219 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
220 break;
221 default:
222 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
223 }
224 if (sc->slow_mode)
225 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
226 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
227
228 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
229 reg |= XENON_PHY_INITIALIZATION;
230 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
231
232 /* Wait for the eMMC PHY init. */
233 for (i = 100; i > 0; i--) {
234 DELAY(100);
235
236 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
237 if ((reg & XENON_PHY_INITIALIZATION) == 0)
238 break;
239 }
240
241 if (i == 0) {
242 device_printf(brdev, "eMMC PHY failed to initialize\n");
243 return (ETIMEDOUT);
244 }
245
246 return (0);
247 }
248
249 static int
sdhci_xenon_phy_set(device_t brdev,struct mmc_ios * ios)250 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios)
251 {
252 struct sdhci_xenon_softc *sc;
253 uint32_t reg;
254
255 sc = device_get_softc(brdev);
256 /* Setup pad, set bit[28] and bits[26:24] */
257 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);
258 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
259 XENON_FC_QSP_RECEN | XENON_OEN_QSN);
260 /* All FC_XX_RECEIVCE should be set as CMOS Type */
261 reg |= XENON_FC_ALL_CMOS_RECEIVER;
262 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);
263
264 /* Set CMD and DQ Pull Up */
265 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
266 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU);
267 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD);
268 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
269
270 if (ios->timing == bus_timing_normal)
271 return (sdhci_xenon_phy_init(brdev, ios));
272
273 /* Clear SDIO mode, no SDIO support for now. */
274 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
275 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
276 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
277
278 /*
279 * Set preferred ZNR and ZPR value.
280 * The ZNR and ZPR value vary between different boards.
281 * Define them both in the DTS for the board!
282 */
283 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);
284 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
285 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr);
286 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);
287
288 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */
289 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
290 reg &= ~SDHCI_CLOCK_CARD_EN;
291 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
292
293 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);
294 switch (ios->timing) {
295 case bus_timing_mmc_hs400:
296 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
297 XENON_CMD_DDR_MODE;
298 reg &= ~XENON_DQ_ASYNC_MODE;
299 break;
300 case bus_timing_uhs_ddr50:
301 case bus_timing_mmc_ddr52:
302 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
303 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
304 break;
305 default:
306 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
307 XENON_CMD_DDR_MODE);
308 reg |= XENON_DQ_ASYNC_MODE;
309 }
310 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);
311
312 /* Enable SD clock. */
313 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
314 reg |= SDHCI_CLOCK_CARD_EN;
315 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
316
317 if (ios->timing == bus_timing_mmc_hs400)
318 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
319 XENON_LOGIC_TIMING_VALUE);
320 else {
321 /* Disable both SDHC Data Strobe and Enhanced Strobe. */
322 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);
323 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
324 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);
325
326 /* Clear Strobe line Pull down or Pull up. */
327 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
328 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU);
329 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
330 }
331
332 return (sdhci_xenon_phy_init(brdev, ios));
333 }
334
335 static int
sdhci_xenon_update_ios(device_t brdev,device_t reqdev)336 sdhci_xenon_update_ios(device_t brdev, device_t reqdev)
337 {
338 int err;
339 struct sdhci_xenon_softc *sc;
340 struct mmc_ios *ios;
341 struct sdhci_slot *slot;
342 uint32_t reg;
343
344 err = sdhci_generic_update_ios(brdev, reqdev);
345 if (err != 0)
346 return (err);
347
348 sc = device_get_softc(brdev);
349 slot = device_get_ivars(reqdev);
350 ios = &slot->host.ios;
351
352 switch (ios->power_mode) {
353 case power_on:
354 break;
355 case power_off:
356 if (bootverbose)
357 device_printf(sc->dev, "Powering down sd/mmc\n");
358
359 if (sc->reg_vqmmc)
360 regulator_disable(sc->reg_vqmmc);
361 break;
362 case power_up:
363 if (bootverbose)
364 device_printf(sc->dev, "Powering up sd/mmc\n");
365
366 if (sc->reg_vqmmc)
367 regulator_enable(sc->reg_vqmmc);
368 break;
369 };
370
371 /* Update the PHY settings. */
372 if (ios->clock != 0)
373 sdhci_xenon_phy_set(brdev, ios);
374
375 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) {
376 /* Enable SDCLK_IDLEOFF. */
377 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
378 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id);
379 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
380 }
381
382 return (0);
383 }
384
385 static int
sdhci_xenon_switch_vccq(device_t brdev,device_t reqdev)386 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev)
387 {
388 struct sdhci_xenon_softc *sc;
389 struct sdhci_slot *slot;
390 int uvolt, err;
391
392 sc = device_get_softc(brdev);
393
394 if (sc->reg_vqmmc == NULL)
395 return EOPNOTSUPP;
396
397 slot = device_get_ivars(reqdev);
398 switch (slot->host.ios.vccq) {
399 case vccq_180:
400 uvolt = 1800000;
401 break;
402 case vccq_330:
403 uvolt = 3300000;
404 break;
405 default:
406 return EINVAL;
407 }
408
409 err = regulator_set_voltage(sc->reg_vqmmc, uvolt, uvolt);
410 if (err != 0) {
411 device_printf(sc->dev,
412 "Cannot set vqmmc to %d<->%d\n",
413 uvolt,
414 uvolt);
415 return (err);
416 }
417
418 return (0);
419 }
420
421 static int
sdhci_xenon_probe(device_t dev)422 sdhci_xenon_probe(device_t dev)
423 {
424 struct sdhci_xenon_softc *sc = device_get_softc(dev);
425 pcell_t cid;
426
427 sc->quirks = 0;
428 sc->slot_id = 0;
429 sc->max_clk = XENON_MMC_MAX_CLK;
430
431 if (!ofw_bus_status_okay(dev))
432 return (ENXIO);
433
434 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
435 return (ENXIO);
436
437 sc->node = ofw_bus_get_node(dev);
438 device_set_desc(dev, "Armada Xenon SDHCI controller");
439
440 /* Allow dts to patch quirks, slots, and max-frequency. */
441 if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0)
442 sc->quirks = cid;
443 if ((OF_getencprop(sc->node, "max-frequency", &cid, sizeof(cid))) > 0)
444 sc->max_clk = cid;
445 if (OF_hasprop(sc->node, "no-1-8-v"))
446 sc->no_18v = true;
447 if (OF_hasprop(sc->node, "wp-inverted"))
448 sc->wp_inverted = true;
449 if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode"))
450 sc->slow_mode = true;
451 sc->znr = XENON_ZNR_DEF_VALUE;
452 if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid,
453 sizeof(cid))) > 0)
454 sc->znr = cid & XENON_ZNR_MASK;
455 sc->zpr = XENON_ZPR_DEF_VALUE;
456 if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid,
457 sizeof(cid))) > 0)
458 sc->zpr = cid & XENON_ZPR_MASK;
459 if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply",
460 &sc->reg_vqmmc) == 0 && bootverbose) {
461 if (bootverbose)
462 device_printf(dev, "vqmmc-supply regulator found\n");
463 }
464
465 return (0);
466 }
467
468 static int
sdhci_xenon_attach(device_t dev)469 sdhci_xenon_attach(device_t dev)
470 {
471 struct sdhci_xenon_softc *sc = device_get_softc(dev);
472 struct sdhci_slot *slot;
473 int err, rid;
474 uint32_t reg;
475
476 sc->dev = dev;
477
478 /* Allocate IRQ. */
479 rid = 0;
480 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
481 RF_ACTIVE);
482 if (sc->irq_res == NULL) {
483 device_printf(dev, "Can't allocate IRQ\n");
484 return (ENOMEM);
485 }
486
487 /* Allocate memory. */
488 rid = 0;
489 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
490 &rid, RF_ACTIVE);
491 if (sc->mem_res == NULL) {
492 bus_release_resource(dev, SYS_RES_IRQ,
493 rman_get_rid(sc->irq_res), sc->irq_res);
494 device_printf(dev, "Can't allocate memory for slot\n");
495 return (ENOMEM);
496 }
497
498 slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK);
499
500 /* Check if the device is flagged as non-removable. */
501 if (OF_hasprop(sc->node, "non-removable")) {
502 slot->opt |= SDHCI_NON_REMOVABLE;
503 if (bootverbose)
504 device_printf(dev, "Non-removable media\n");
505 }
506
507 slot->quirks = sc->quirks;
508 slot->caps = sc->caps;
509 slot->max_clk = sc->max_clk;
510 sc->slot = slot;
511
512 /*
513 * Set up any gpio pin handling described in the FDT data. This cannot
514 * fail; see comments in sdhci_fdt_gpio.h for details.
515 */
516 sc->gpio = sdhci_fdt_gpio_setup(dev, slot);
517
518 if (sdhci_init_slot(dev, sc->slot, 0))
519 goto fail;
520
521 /* Activate the interrupt */
522 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
523 NULL, sdhci_xenon_intr, sc, &sc->intrhand);
524 if (err) {
525 device_printf(dev, "Cannot setup IRQ\n");
526 goto fail;
527 }
528
529 /* Disable Auto Clock Gating. */
530 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
531 reg |= XENON_AUTO_CLKGATE_DISABLE;
532 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
533
534 /* Enable this SD controller. */
535 reg |= (1 << sc->slot_id);
536 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
537
538 /* Enable Parallel Transfer. */
539 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
540 reg |= (1 << sc->slot_id);
541 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
542
543 /* Enable Auto Clock Gating. */
544 reg &= ~XENON_AUTO_CLKGATE_DISABLE;
545 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
546
547 /* Disable SDCLK_IDLEOFF before the card initialization. */
548 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
549 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id));
550 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
551
552 /* Mask command conflict errors. */
553 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
554 reg |= XENON_MASK_CMD_CONFLICT_ERR;
555 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
556
557 /* Process cards detection. */
558 sdhci_start_slot(sc->slot);
559
560 return (0);
561
562 fail:
563 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
564 sc->irq_res);
565 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
566 sc->mem_res);
567 free(sc->slot, M_DEVBUF);
568 sc->slot = NULL;
569
570 return (ENXIO);
571 }
572
573 static int
sdhci_xenon_detach(device_t dev)574 sdhci_xenon_detach(device_t dev)
575 {
576 struct sdhci_xenon_softc *sc = device_get_softc(dev);
577
578 if (sc->gpio != NULL)
579 sdhci_fdt_gpio_teardown(sc->gpio);
580
581 bus_generic_detach(dev);
582 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
583 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
584 sc->irq_res);
585 sdhci_cleanup_slot(sc->slot);
586 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
587 sc->mem_res);
588 free(sc->slot, M_DEVBUF);
589 sc->slot = NULL;
590
591 return (0);
592 }
593
594 static device_method_t sdhci_xenon_methods[] = {
595 /* device_if */
596 DEVMETHOD(device_probe, sdhci_xenon_probe),
597 DEVMETHOD(device_attach, sdhci_xenon_attach),
598 DEVMETHOD(device_detach, sdhci_xenon_detach),
599
600 /* Bus interface */
601 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
602 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
603
604 /* mmcbr_if */
605 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios),
606 DEVMETHOD(mmcbr_request, sdhci_generic_request),
607 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro),
608 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
609 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
610 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq),
611
612 /* SDHCI registers accessors */
613 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1),
614 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2),
615 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4),
616 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4),
617 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1),
618 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2),
619 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4),
620 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4),
621 DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present),
622
623 DEVMETHOD_END
624 };
625
626 static driver_t sdhci_xenon_driver = {
627 "sdhci_xenon",
628 sdhci_xenon_methods,
629 sizeof(struct sdhci_xenon_softc),
630 };
631 static devclass_t sdhci_xenon_devclass;
632
633 DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass,
634 NULL, NULL);
635
636 SDHCI_DEPEND(sdhci_xenon);
637 #ifndef MMCCAM
638 MMC_DECLARE_BRIDGE(sdhci_xenon);
639 #endif
640