1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_IMPL_H 36 #define _SYS_EFX_IMPL_H 37 38 #include "efx.h" 39 #include "efx_regs.h" 40 #include "efx_regs_ef10.h" 41 42 /* FIXME: Add definition for driver generated software events */ 43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 45 #endif 46 47 48 #if EFSYS_OPT_SIENA 49 #include "siena_impl.h" 50 #endif /* EFSYS_OPT_SIENA */ 51 52 #if EFSYS_OPT_HUNTINGTON 53 #include "hunt_impl.h" 54 #endif /* EFSYS_OPT_HUNTINGTON */ 55 56 #if EFSYS_OPT_MEDFORD 57 #include "medford_impl.h" 58 #endif /* EFSYS_OPT_MEDFORD */ 59 60 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 61 #include "ef10_impl.h" 62 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif 67 68 #define EFX_MOD_MCDI 0x00000001 69 #define EFX_MOD_PROBE 0x00000002 70 #define EFX_MOD_NVRAM 0x00000004 71 #define EFX_MOD_VPD 0x00000008 72 #define EFX_MOD_NIC 0x00000010 73 #define EFX_MOD_INTR 0x00000020 74 #define EFX_MOD_EV 0x00000040 75 #define EFX_MOD_RX 0x00000080 76 #define EFX_MOD_TX 0x00000100 77 #define EFX_MOD_PORT 0x00000200 78 #define EFX_MOD_MON 0x00000400 79 #define EFX_MOD_FILTER 0x00001000 80 #define EFX_MOD_LIC 0x00002000 81 82 #define EFX_RESET_PHY 0x00000001 83 #define EFX_RESET_RXQ_ERR 0x00000002 84 #define EFX_RESET_TXQ_ERR 0x00000004 85 86 typedef enum efx_mac_type_e { 87 EFX_MAC_INVALID = 0, 88 EFX_MAC_SIENA, 89 EFX_MAC_HUNTINGTON, 90 EFX_MAC_MEDFORD, 91 EFX_MAC_NTYPES 92 } efx_mac_type_t; 93 94 typedef struct efx_ev_ops_s { 95 efx_rc_t (*eevo_init)(efx_nic_t *); 96 void (*eevo_fini)(efx_nic_t *); 97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 98 efsys_mem_t *, size_t, uint32_t, 99 uint32_t, uint32_t, efx_evq_t *); 100 void (*eevo_qdestroy)(efx_evq_t *); 101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 102 void (*eevo_qpost)(efx_evq_t *, uint16_t); 103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 104 #if EFSYS_OPT_QSTATS 105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 106 #endif 107 } efx_ev_ops_t; 108 109 typedef struct efx_tx_ops_s { 110 efx_rc_t (*etxo_init)(efx_nic_t *); 111 void (*etxo_fini)(efx_nic_t *); 112 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 113 unsigned int, unsigned int, 114 efsys_mem_t *, size_t, 115 uint32_t, uint16_t, 116 efx_evq_t *, efx_txq_t *, 117 unsigned int *); 118 void (*etxo_qdestroy)(efx_txq_t *); 119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 120 unsigned int, unsigned int, 121 unsigned int *); 122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 124 efx_rc_t (*etxo_qflush)(efx_txq_t *); 125 void (*etxo_qenable)(efx_txq_t *); 126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 127 void (*etxo_qpio_disable)(efx_txq_t *); 128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 129 size_t); 130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 131 unsigned int *); 132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 133 unsigned int, unsigned int, 134 unsigned int *); 135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 136 size_t, boolean_t, 137 efx_desc_t *); 138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 139 uint32_t, uint8_t, 140 efx_desc_t *); 141 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 142 uint32_t, uint16_t, 143 efx_desc_t *, int); 144 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 145 efx_desc_t *); 146 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 147 efx_desc_t *); 148 #if EFSYS_OPT_QSTATS 149 void (*etxo_qstats_update)(efx_txq_t *, 150 efsys_stat_t *); 151 #endif 152 } efx_tx_ops_t; 153 154 typedef struct efx_rx_ops_s { 155 efx_rc_t (*erxo_init)(efx_nic_t *); 156 void (*erxo_fini)(efx_nic_t *); 157 #if EFSYS_OPT_RX_SCATTER 158 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 159 #endif 160 #if EFSYS_OPT_RX_SCALE 161 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, 162 efx_rx_hash_type_t, boolean_t); 163 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); 164 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, 165 size_t); 166 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 167 uint8_t *); 168 #endif /* EFSYS_OPT_RX_SCALE */ 169 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 170 uint16_t *); 171 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 172 unsigned int, unsigned int, 173 unsigned int); 174 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 175 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 176 void (*erxo_qenable)(efx_rxq_t *); 177 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 178 unsigned int, efx_rxq_type_t, 179 efsys_mem_t *, size_t, uint32_t, 180 efx_evq_t *, efx_rxq_t *); 181 void (*erxo_qdestroy)(efx_rxq_t *); 182 } efx_rx_ops_t; 183 184 typedef struct efx_mac_ops_s { 185 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 186 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 187 efx_rc_t (*emo_addr_set)(efx_nic_t *); 188 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 189 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 190 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 191 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 192 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 193 efx_rxq_t *, boolean_t); 194 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 195 #if EFSYS_OPT_LOOPBACK 196 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 197 efx_loopback_type_t); 198 #endif /* EFSYS_OPT_LOOPBACK */ 199 #if EFSYS_OPT_MAC_STATS 200 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 201 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 202 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 203 uint16_t, boolean_t); 204 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 205 efsys_stat_t *, uint32_t *); 206 #endif /* EFSYS_OPT_MAC_STATS */ 207 } efx_mac_ops_t; 208 209 typedef struct efx_phy_ops_s { 210 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 211 efx_rc_t (*epo_reset)(efx_nic_t *); 212 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 213 efx_rc_t (*epo_verify)(efx_nic_t *); 214 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 215 #if EFSYS_OPT_PHY_STATS 216 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 217 uint32_t *); 218 #endif /* EFSYS_OPT_PHY_STATS */ 219 #if EFSYS_OPT_BIST 220 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 221 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 222 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 223 efx_bist_result_t *, uint32_t *, 224 unsigned long *, size_t); 225 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 226 #endif /* EFSYS_OPT_BIST */ 227 } efx_phy_ops_t; 228 229 #if EFSYS_OPT_FILTER 230 typedef struct efx_filter_ops_s { 231 efx_rc_t (*efo_init)(efx_nic_t *); 232 void (*efo_fini)(efx_nic_t *); 233 efx_rc_t (*efo_restore)(efx_nic_t *); 234 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 235 boolean_t may_replace); 236 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 237 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 238 size_t, size_t *); 239 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 240 boolean_t, boolean_t, boolean_t, 241 uint8_t const *, uint32_t); 242 } efx_filter_ops_t; 243 244 extern __checkReturn efx_rc_t 245 efx_filter_reconfigure( 246 __in efx_nic_t *enp, 247 __in_ecount(6) uint8_t const *mac_addr, 248 __in boolean_t all_unicst, 249 __in boolean_t mulcst, 250 __in boolean_t all_mulcst, 251 __in boolean_t brdcst, 252 __in_ecount(6*count) uint8_t const *addrs, 253 __in uint32_t count); 254 255 #endif /* EFSYS_OPT_FILTER */ 256 257 258 typedef struct efx_port_s { 259 efx_mac_type_t ep_mac_type; 260 uint32_t ep_phy_type; 261 uint8_t ep_port; 262 uint32_t ep_mac_pdu; 263 uint8_t ep_mac_addr[6]; 264 efx_link_mode_t ep_link_mode; 265 boolean_t ep_all_unicst; 266 boolean_t ep_mulcst; 267 boolean_t ep_all_mulcst; 268 boolean_t ep_brdcst; 269 unsigned int ep_fcntl; 270 boolean_t ep_fcntl_autoneg; 271 efx_oword_t ep_multicst_hash[2]; 272 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 273 EFX_MAC_MULTICAST_LIST_MAX]; 274 uint32_t ep_mulcst_addr_count; 275 #if EFSYS_OPT_LOOPBACK 276 efx_loopback_type_t ep_loopback_type; 277 efx_link_mode_t ep_loopback_link_mode; 278 #endif /* EFSYS_OPT_LOOPBACK */ 279 #if EFSYS_OPT_PHY_FLAGS 280 uint32_t ep_phy_flags; 281 #endif /* EFSYS_OPT_PHY_FLAGS */ 282 #if EFSYS_OPT_PHY_LED_CONTROL 283 efx_phy_led_mode_t ep_phy_led_mode; 284 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 285 efx_phy_media_type_t ep_fixed_port_type; 286 efx_phy_media_type_t ep_module_type; 287 uint32_t ep_adv_cap_mask; 288 uint32_t ep_lp_cap_mask; 289 uint32_t ep_default_adv_cap_mask; 290 uint32_t ep_phy_cap_mask; 291 boolean_t ep_mac_drain; 292 #if EFSYS_OPT_BIST 293 efx_bist_type_t ep_current_bist; 294 #endif 295 const efx_mac_ops_t *ep_emop; 296 const efx_phy_ops_t *ep_epop; 297 } efx_port_t; 298 299 typedef struct efx_mon_ops_s { 300 #if EFSYS_OPT_MON_STATS 301 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 302 efx_mon_stat_value_t *); 303 #endif /* EFSYS_OPT_MON_STATS */ 304 } efx_mon_ops_t; 305 306 typedef struct efx_mon_s { 307 efx_mon_type_t em_type; 308 const efx_mon_ops_t *em_emop; 309 } efx_mon_t; 310 311 typedef struct efx_intr_ops_s { 312 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 313 void (*eio_enable)(efx_nic_t *); 314 void (*eio_disable)(efx_nic_t *); 315 void (*eio_disable_unlocked)(efx_nic_t *); 316 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 317 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 318 void (*eio_status_message)(efx_nic_t *, unsigned int, 319 boolean_t *); 320 void (*eio_fatal)(efx_nic_t *); 321 void (*eio_fini)(efx_nic_t *); 322 } efx_intr_ops_t; 323 324 typedef struct efx_intr_s { 325 const efx_intr_ops_t *ei_eiop; 326 efsys_mem_t *ei_esmp; 327 efx_intr_type_t ei_type; 328 unsigned int ei_level; 329 } efx_intr_t; 330 331 typedef struct efx_nic_ops_s { 332 efx_rc_t (*eno_probe)(efx_nic_t *); 333 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 334 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 335 efx_rc_t (*eno_reset)(efx_nic_t *); 336 efx_rc_t (*eno_init)(efx_nic_t *); 337 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 338 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 339 uint32_t *, size_t *); 340 #if EFSYS_OPT_DIAG 341 efx_rc_t (*eno_register_test)(efx_nic_t *); 342 #endif /* EFSYS_OPT_DIAG */ 343 void (*eno_fini)(efx_nic_t *); 344 void (*eno_unprobe)(efx_nic_t *); 345 } efx_nic_ops_t; 346 347 #ifndef EFX_TXQ_LIMIT_TARGET 348 #define EFX_TXQ_LIMIT_TARGET 259 349 #endif 350 #ifndef EFX_RXQ_LIMIT_TARGET 351 #define EFX_RXQ_LIMIT_TARGET 512 352 #endif 353 #ifndef EFX_TXQ_DC_SIZE 354 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 355 #endif 356 #ifndef EFX_RXQ_DC_SIZE 357 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 358 #endif 359 360 #if EFSYS_OPT_FILTER 361 362 typedef struct siena_filter_spec_s { 363 uint8_t sfs_type; 364 uint32_t sfs_flags; 365 uint32_t sfs_dmaq_id; 366 uint32_t sfs_dword[3]; 367 } siena_filter_spec_t; 368 369 typedef enum siena_filter_type_e { 370 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 371 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 372 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 373 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 374 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 375 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 376 377 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 378 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 379 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 380 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 381 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 382 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 383 384 EFX_SIENA_FILTER_NTYPES 385 } siena_filter_type_t; 386 387 typedef enum siena_filter_tbl_id_e { 388 EFX_SIENA_FILTER_TBL_RX_IP = 0, 389 EFX_SIENA_FILTER_TBL_RX_MAC, 390 EFX_SIENA_FILTER_TBL_TX_IP, 391 EFX_SIENA_FILTER_TBL_TX_MAC, 392 EFX_SIENA_FILTER_NTBLS 393 } siena_filter_tbl_id_t; 394 395 typedef struct siena_filter_tbl_s { 396 int sft_size; /* number of entries */ 397 int sft_used; /* active count */ 398 uint32_t *sft_bitmap; /* active bitmap */ 399 siena_filter_spec_t *sft_spec; /* array of saved specs */ 400 } siena_filter_tbl_t; 401 402 typedef struct siena_filter_s { 403 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 404 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 405 } siena_filter_t; 406 407 typedef struct efx_filter_s { 408 #if EFSYS_OPT_SIENA 409 siena_filter_t *ef_siena_filter; 410 #endif /* EFSYS_OPT_SIENA */ 411 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 412 ef10_filter_table_t *ef_ef10_filter_table; 413 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 414 } efx_filter_t; 415 416 extern void 417 siena_filter_tbl_clear( 418 __in efx_nic_t *enp, 419 __in siena_filter_tbl_id_t tbl); 420 421 #endif /* EFSYS_OPT_FILTER */ 422 423 #if EFSYS_OPT_MCDI 424 425 typedef struct efx_mcdi_ops_s { 426 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 427 void (*emco_send_request)(efx_nic_t *, void *, size_t, 428 void *, size_t); 429 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 430 boolean_t (*emco_poll_response)(efx_nic_t *); 431 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 432 void (*emco_fini)(efx_nic_t *); 433 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 434 efx_mcdi_feature_id_t, boolean_t *); 435 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 436 uint32_t *); 437 } efx_mcdi_ops_t; 438 439 typedef struct efx_mcdi_s { 440 const efx_mcdi_ops_t *em_emcop; 441 const efx_mcdi_transport_t *em_emtp; 442 efx_mcdi_iface_t em_emip; 443 } efx_mcdi_t; 444 445 #endif /* EFSYS_OPT_MCDI */ 446 447 #if EFSYS_OPT_NVRAM 448 typedef struct efx_nvram_ops_s { 449 #if EFSYS_OPT_DIAG 450 efx_rc_t (*envo_test)(efx_nic_t *); 451 #endif /* EFSYS_OPT_DIAG */ 452 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 453 uint32_t *); 454 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 455 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 456 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 457 unsigned int, caddr_t, size_t); 458 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 459 unsigned int, size_t); 460 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 461 unsigned int, caddr_t, size_t); 462 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t); 463 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 464 uint32_t *, uint16_t *); 465 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 466 uint16_t *); 467 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t, 468 caddr_t, size_t); 469 } efx_nvram_ops_t; 470 #endif /* EFSYS_OPT_NVRAM */ 471 472 #if EFSYS_OPT_VPD 473 typedef struct efx_vpd_ops_s { 474 efx_rc_t (*evpdo_init)(efx_nic_t *); 475 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 476 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 477 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 478 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 479 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 480 efx_vpd_value_t *); 481 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 482 efx_vpd_value_t *); 483 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 484 efx_vpd_value_t *, unsigned int *); 485 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 486 void (*evpdo_fini)(efx_nic_t *); 487 } efx_vpd_ops_t; 488 #endif /* EFSYS_OPT_VPD */ 489 490 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 491 492 __checkReturn efx_rc_t 493 efx_mcdi_nvram_partitions( 494 __in efx_nic_t *enp, 495 __out_bcount(size) caddr_t data, 496 __in size_t size, 497 __out unsigned int *npartnp); 498 499 __checkReturn efx_rc_t 500 efx_mcdi_nvram_metadata( 501 __in efx_nic_t *enp, 502 __in uint32_t partn, 503 __out uint32_t *subtypep, 504 __out_ecount(4) uint16_t version[4], 505 __out_bcount_opt(size) char *descp, 506 __in size_t size); 507 508 __checkReturn efx_rc_t 509 efx_mcdi_nvram_info( 510 __in efx_nic_t *enp, 511 __in uint32_t partn, 512 __out_opt size_t *sizep, 513 __out_opt uint32_t *addressp, 514 __out_opt uint32_t *erase_sizep, 515 __out_opt uint32_t *write_sizep); 516 517 __checkReturn efx_rc_t 518 efx_mcdi_nvram_update_start( 519 __in efx_nic_t *enp, 520 __in uint32_t partn); 521 522 __checkReturn efx_rc_t 523 efx_mcdi_nvram_read( 524 __in efx_nic_t *enp, 525 __in uint32_t partn, 526 __in uint32_t offset, 527 __out_bcount(size) caddr_t data, 528 __in size_t size, 529 __in uint32_t mode); 530 531 __checkReturn efx_rc_t 532 efx_mcdi_nvram_erase( 533 __in efx_nic_t *enp, 534 __in uint32_t partn, 535 __in uint32_t offset, 536 __in size_t size); 537 538 __checkReturn efx_rc_t 539 efx_mcdi_nvram_write( 540 __in efx_nic_t *enp, 541 __in uint32_t partn, 542 __in uint32_t offset, 543 __in_bcount(size) caddr_t data, 544 __in size_t size); 545 546 __checkReturn efx_rc_t 547 efx_mcdi_nvram_update_finish( 548 __in efx_nic_t *enp, 549 __in uint32_t partn, 550 __in boolean_t reboot, 551 __out_opt uint32_t *resultp); 552 553 #if EFSYS_OPT_DIAG 554 555 __checkReturn efx_rc_t 556 efx_mcdi_nvram_test( 557 __in efx_nic_t *enp, 558 __in uint32_t partn); 559 560 #endif /* EFSYS_OPT_DIAG */ 561 562 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 563 564 #if EFSYS_OPT_LICENSING 565 566 typedef struct efx_lic_ops_s { 567 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 568 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 569 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 570 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 571 size_t *, uint8_t *); 572 efx_rc_t (*elo_find_start) 573 (efx_nic_t *, caddr_t, size_t, uint32_t *); 574 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 575 uint32_t, uint32_t *); 576 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 577 uint32_t, uint32_t *, uint32_t *); 578 boolean_t (*elo_validate_key)(efx_nic_t *, 579 caddr_t, uint32_t); 580 efx_rc_t (*elo_read_key)(efx_nic_t *, 581 caddr_t, size_t, uint32_t, uint32_t, 582 caddr_t, size_t, uint32_t *); 583 efx_rc_t (*elo_write_key)(efx_nic_t *, 584 caddr_t, size_t, uint32_t, 585 caddr_t, uint32_t, uint32_t *); 586 efx_rc_t (*elo_delete_key)(efx_nic_t *, 587 caddr_t, size_t, uint32_t, 588 uint32_t, uint32_t, uint32_t *); 589 efx_rc_t (*elo_create_partition)(efx_nic_t *, 590 caddr_t, size_t); 591 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 592 caddr_t, size_t); 593 } efx_lic_ops_t; 594 595 #endif 596 597 typedef struct efx_drv_cfg_s { 598 uint32_t edc_min_vi_count; 599 uint32_t edc_max_vi_count; 600 601 uint32_t edc_max_piobuf_count; 602 uint32_t edc_pio_alloc_size; 603 } efx_drv_cfg_t; 604 605 struct efx_nic_s { 606 uint32_t en_magic; 607 efx_family_t en_family; 608 uint32_t en_features; 609 efsys_identifier_t *en_esip; 610 efsys_lock_t *en_eslp; 611 efsys_bar_t *en_esbp; 612 unsigned int en_mod_flags; 613 unsigned int en_reset_flags; 614 efx_nic_cfg_t en_nic_cfg; 615 efx_drv_cfg_t en_drv_cfg; 616 efx_port_t en_port; 617 efx_mon_t en_mon; 618 efx_intr_t en_intr; 619 uint32_t en_ev_qcount; 620 uint32_t en_rx_qcount; 621 uint32_t en_tx_qcount; 622 const efx_nic_ops_t *en_enop; 623 const efx_ev_ops_t *en_eevop; 624 const efx_tx_ops_t *en_etxop; 625 const efx_rx_ops_t *en_erxop; 626 #if EFSYS_OPT_FILTER 627 efx_filter_t en_filter; 628 const efx_filter_ops_t *en_efop; 629 #endif /* EFSYS_OPT_FILTER */ 630 #if EFSYS_OPT_MCDI 631 efx_mcdi_t en_mcdi; 632 #endif /* EFSYS_OPT_MCDI */ 633 #if EFSYS_OPT_NVRAM 634 efx_nvram_type_t en_nvram_locked; 635 const efx_nvram_ops_t *en_envop; 636 #endif /* EFSYS_OPT_NVRAM */ 637 #if EFSYS_OPT_VPD 638 const efx_vpd_ops_t *en_evpdop; 639 #endif /* EFSYS_OPT_VPD */ 640 #if EFSYS_OPT_RX_SCALE 641 efx_rx_hash_support_t en_hash_support; 642 efx_rx_scale_support_t en_rss_support; 643 uint32_t en_rss_context; 644 #endif /* EFSYS_OPT_RX_SCALE */ 645 uint32_t en_vport_id; 646 #if EFSYS_OPT_LICENSING 647 const efx_lic_ops_t *en_elop; 648 boolean_t en_licensing_supported; 649 #endif 650 union { 651 #if EFSYS_OPT_SIENA 652 struct { 653 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 654 unsigned int enu_partn_mask; 655 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 656 #if EFSYS_OPT_VPD 657 caddr_t enu_svpd; 658 size_t enu_svpd_length; 659 #endif /* EFSYS_OPT_VPD */ 660 int enu_unused; 661 } siena; 662 #endif /* EFSYS_OPT_SIENA */ 663 int enu_unused; 664 } en_u; 665 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 666 union en_arch { 667 struct { 668 int ena_vi_base; 669 int ena_vi_count; 670 int ena_vi_shift; 671 #if EFSYS_OPT_VPD 672 caddr_t ena_svpd; 673 size_t ena_svpd_length; 674 #endif /* EFSYS_OPT_VPD */ 675 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 676 uint32_t ena_piobuf_count; 677 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 678 uint32_t ena_pio_write_vi_base; 679 /* Memory BAR mapping regions */ 680 uint32_t ena_uc_mem_map_offset; 681 size_t ena_uc_mem_map_size; 682 uint32_t ena_wc_mem_map_offset; 683 size_t ena_wc_mem_map_size; 684 } ef10; 685 } en_arch; 686 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 687 }; 688 689 690 #define EFX_NIC_MAGIC 0x02121996 691 692 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 693 const efx_ev_callbacks_t *, void *); 694 695 typedef struct efx_evq_rxq_state_s { 696 unsigned int eers_rx_read_ptr; 697 unsigned int eers_rx_mask; 698 } efx_evq_rxq_state_t; 699 700 struct efx_evq_s { 701 uint32_t ee_magic; 702 efx_nic_t *ee_enp; 703 unsigned int ee_index; 704 unsigned int ee_mask; 705 efsys_mem_t *ee_esmp; 706 #if EFSYS_OPT_QSTATS 707 uint32_t ee_stat[EV_NQSTATS]; 708 #endif /* EFSYS_OPT_QSTATS */ 709 710 efx_ev_handler_t ee_rx; 711 efx_ev_handler_t ee_tx; 712 efx_ev_handler_t ee_driver; 713 efx_ev_handler_t ee_global; 714 efx_ev_handler_t ee_drv_gen; 715 #if EFSYS_OPT_MCDI 716 efx_ev_handler_t ee_mcdi; 717 #endif /* EFSYS_OPT_MCDI */ 718 719 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 720 721 uint32_t ee_flags; 722 }; 723 724 #define EFX_EVQ_MAGIC 0x08081997 725 726 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 727 728 struct efx_rxq_s { 729 uint32_t er_magic; 730 efx_nic_t *er_enp; 731 efx_evq_t *er_eep; 732 unsigned int er_index; 733 unsigned int er_label; 734 unsigned int er_mask; 735 efsys_mem_t *er_esmp; 736 }; 737 738 #define EFX_RXQ_MAGIC 0x15022005 739 740 struct efx_txq_s { 741 uint32_t et_magic; 742 efx_nic_t *et_enp; 743 unsigned int et_index; 744 unsigned int et_mask; 745 efsys_mem_t *et_esmp; 746 #if EFSYS_OPT_HUNTINGTON 747 uint32_t et_pio_bufnum; 748 uint32_t et_pio_blknum; 749 uint32_t et_pio_write_offset; 750 uint32_t et_pio_offset; 751 size_t et_pio_size; 752 #endif 753 #if EFSYS_OPT_QSTATS 754 uint32_t et_stat[TX_NQSTATS]; 755 #endif /* EFSYS_OPT_QSTATS */ 756 }; 757 758 #define EFX_TXQ_MAGIC 0x05092005 759 760 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 761 do { \ 762 (_dst)[0] = (_src)[0]; \ 763 (_dst)[1] = (_src)[1]; \ 764 (_dst)[2] = (_src)[2]; \ 765 (_dst)[3] = (_src)[3]; \ 766 (_dst)[4] = (_src)[4]; \ 767 (_dst)[5] = (_src)[5]; \ 768 _NOTE(CONSTANTCONDITION) \ 769 } while (B_FALSE) 770 771 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 772 do { \ 773 uint16_t *_d = (uint16_t *)(_dst); \ 774 _d[0] = 0xffff; \ 775 _d[1] = 0xffff; \ 776 _d[2] = 0xffff; \ 777 _NOTE(CONSTANTCONDITION) \ 778 } while (B_FALSE) 779 780 #if EFSYS_OPT_CHECK_REG 781 #define EFX_CHECK_REG(_enp, _reg) \ 782 do { \ 783 const char *name = #_reg; \ 784 char min = name[4]; \ 785 char max = name[5]; \ 786 char rev; \ 787 \ 788 switch ((_enp)->en_family) { \ 789 case EFX_FAMILY_SIENA: \ 790 rev = 'C'; \ 791 break; \ 792 \ 793 case EFX_FAMILY_HUNTINGTON: \ 794 rev = 'D'; \ 795 break; \ 796 \ 797 case EFX_FAMILY_MEDFORD: \ 798 rev = 'E'; \ 799 break; \ 800 \ 801 default: \ 802 rev = '?'; \ 803 break; \ 804 } \ 805 \ 806 EFSYS_ASSERT3S(rev, >=, min); \ 807 EFSYS_ASSERT3S(rev, <=, max); \ 808 \ 809 _NOTE(CONSTANTCONDITION) \ 810 } while (B_FALSE) 811 #else 812 #define EFX_CHECK_REG(_enp, _reg) do { \ 813 _NOTE(CONSTANTCONDITION) \ 814 } while (B_FALSE) 815 #endif 816 817 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 818 do { \ 819 EFX_CHECK_REG((_enp), (_reg)); \ 820 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 821 (_edp), (_lock)); \ 822 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 823 uint32_t, _reg ## _OFST, \ 824 uint32_t, (_edp)->ed_u32[0]); \ 825 _NOTE(CONSTANTCONDITION) \ 826 } while (B_FALSE) 827 828 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 829 do { \ 830 EFX_CHECK_REG((_enp), (_reg)); \ 831 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 832 uint32_t, _reg ## _OFST, \ 833 uint32_t, (_edp)->ed_u32[0]); \ 834 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 835 (_edp), (_lock)); \ 836 _NOTE(CONSTANTCONDITION) \ 837 } while (B_FALSE) 838 839 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 840 do { \ 841 EFX_CHECK_REG((_enp), (_reg)); \ 842 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 843 (_eqp)); \ 844 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 845 uint32_t, _reg ## _OFST, \ 846 uint32_t, (_eqp)->eq_u32[1], \ 847 uint32_t, (_eqp)->eq_u32[0]); \ 848 _NOTE(CONSTANTCONDITION) \ 849 } while (B_FALSE) 850 851 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 852 do { \ 853 EFX_CHECK_REG((_enp), (_reg)); \ 854 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 855 uint32_t, _reg ## _OFST, \ 856 uint32_t, (_eqp)->eq_u32[1], \ 857 uint32_t, (_eqp)->eq_u32[0]); \ 858 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 859 (_eqp)); \ 860 _NOTE(CONSTANTCONDITION) \ 861 } while (B_FALSE) 862 863 #define EFX_BAR_READO(_enp, _reg, _eop) \ 864 do { \ 865 EFX_CHECK_REG((_enp), (_reg)); \ 866 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 867 (_eop), B_TRUE); \ 868 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 869 uint32_t, _reg ## _OFST, \ 870 uint32_t, (_eop)->eo_u32[3], \ 871 uint32_t, (_eop)->eo_u32[2], \ 872 uint32_t, (_eop)->eo_u32[1], \ 873 uint32_t, (_eop)->eo_u32[0]); \ 874 _NOTE(CONSTANTCONDITION) \ 875 } while (B_FALSE) 876 877 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 878 do { \ 879 EFX_CHECK_REG((_enp), (_reg)); \ 880 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 881 uint32_t, _reg ## _OFST, \ 882 uint32_t, (_eop)->eo_u32[3], \ 883 uint32_t, (_eop)->eo_u32[2], \ 884 uint32_t, (_eop)->eo_u32[1], \ 885 uint32_t, (_eop)->eo_u32[0]); \ 886 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 887 (_eop), B_TRUE); \ 888 _NOTE(CONSTANTCONDITION) \ 889 } while (B_FALSE) 890 891 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 892 do { \ 893 EFX_CHECK_REG((_enp), (_reg)); \ 894 EFSYS_BAR_READD((_enp)->en_esbp, \ 895 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 896 (_edp), (_lock)); \ 897 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 898 uint32_t, (_index), \ 899 uint32_t, _reg ## _OFST, \ 900 uint32_t, (_edp)->ed_u32[0]); \ 901 _NOTE(CONSTANTCONDITION) \ 902 } while (B_FALSE) 903 904 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 905 do { \ 906 EFX_CHECK_REG((_enp), (_reg)); \ 907 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 908 uint32_t, (_index), \ 909 uint32_t, _reg ## _OFST, \ 910 uint32_t, (_edp)->ed_u32[0]); \ 911 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 912 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 913 (_edp), (_lock)); \ 914 _NOTE(CONSTANTCONDITION) \ 915 } while (B_FALSE) 916 917 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 918 do { \ 919 EFX_CHECK_REG((_enp), (_reg)); \ 920 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 921 uint32_t, (_index), \ 922 uint32_t, _reg ## _OFST, \ 923 uint32_t, (_edp)->ed_u32[0]); \ 924 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 925 (_reg ## _OFST + \ 926 (2 * sizeof (efx_dword_t)) + \ 927 ((_index) * _reg ## _STEP)), \ 928 (_edp), (_lock)); \ 929 _NOTE(CONSTANTCONDITION) \ 930 } while (B_FALSE) 931 932 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 933 do { \ 934 EFX_CHECK_REG((_enp), (_reg)); \ 935 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 936 uint32_t, (_index), \ 937 uint32_t, _reg ## _OFST, \ 938 uint32_t, (_edp)->ed_u32[0]); \ 939 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 940 (_reg ## _OFST + \ 941 (3 * sizeof (efx_dword_t)) + \ 942 ((_index) * _reg ## _STEP)), \ 943 (_edp), (_lock)); \ 944 _NOTE(CONSTANTCONDITION) \ 945 } while (B_FALSE) 946 947 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 948 do { \ 949 EFX_CHECK_REG((_enp), (_reg)); \ 950 EFSYS_BAR_READQ((_enp)->en_esbp, \ 951 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 952 (_eqp)); \ 953 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 954 uint32_t, (_index), \ 955 uint32_t, _reg ## _OFST, \ 956 uint32_t, (_eqp)->eq_u32[1], \ 957 uint32_t, (_eqp)->eq_u32[0]); \ 958 _NOTE(CONSTANTCONDITION) \ 959 } while (B_FALSE) 960 961 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 962 do { \ 963 EFX_CHECK_REG((_enp), (_reg)); \ 964 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 965 uint32_t, (_index), \ 966 uint32_t, _reg ## _OFST, \ 967 uint32_t, (_eqp)->eq_u32[1], \ 968 uint32_t, (_eqp)->eq_u32[0]); \ 969 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 970 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 971 (_eqp)); \ 972 _NOTE(CONSTANTCONDITION) \ 973 } while (B_FALSE) 974 975 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 976 do { \ 977 EFX_CHECK_REG((_enp), (_reg)); \ 978 EFSYS_BAR_READO((_enp)->en_esbp, \ 979 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 980 (_eop), (_lock)); \ 981 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 982 uint32_t, (_index), \ 983 uint32_t, _reg ## _OFST, \ 984 uint32_t, (_eop)->eo_u32[3], \ 985 uint32_t, (_eop)->eo_u32[2], \ 986 uint32_t, (_eop)->eo_u32[1], \ 987 uint32_t, (_eop)->eo_u32[0]); \ 988 _NOTE(CONSTANTCONDITION) \ 989 } while (B_FALSE) 990 991 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 992 do { \ 993 EFX_CHECK_REG((_enp), (_reg)); \ 994 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 995 uint32_t, (_index), \ 996 uint32_t, _reg ## _OFST, \ 997 uint32_t, (_eop)->eo_u32[3], \ 998 uint32_t, (_eop)->eo_u32[2], \ 999 uint32_t, (_eop)->eo_u32[1], \ 1000 uint32_t, (_eop)->eo_u32[0]); \ 1001 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1002 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1003 (_eop), (_lock)); \ 1004 _NOTE(CONSTANTCONDITION) \ 1005 } while (B_FALSE) 1006 1007 /* 1008 * Allow drivers to perform optimised 128-bit doorbell writes. 1009 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1010 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1011 * the need for locking in the host, and are the only ones known to be safe to 1012 * use 128-bites write with. 1013 */ 1014 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1015 do { \ 1016 EFX_CHECK_REG((_enp), (_reg)); \ 1017 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1018 const char *, \ 1019 #_reg, \ 1020 uint32_t, (_index), \ 1021 uint32_t, _reg ## _OFST, \ 1022 uint32_t, (_eop)->eo_u32[3], \ 1023 uint32_t, (_eop)->eo_u32[2], \ 1024 uint32_t, (_eop)->eo_u32[1], \ 1025 uint32_t, (_eop)->eo_u32[0]); \ 1026 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1027 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1028 (_eop)); \ 1029 _NOTE(CONSTANTCONDITION) \ 1030 } while (B_FALSE) 1031 1032 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1033 do { \ 1034 unsigned int _new = (_wptr); \ 1035 unsigned int _old = (_owptr); \ 1036 \ 1037 if ((_new) >= (_old)) \ 1038 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1039 (_old) * sizeof (efx_desc_t), \ 1040 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1041 else \ 1042 /* \ 1043 * It is cheaper to sync entire map than sync \ 1044 * two parts especially when offset/size are \ 1045 * ignored and entire map is synced in any case.\ 1046 */ \ 1047 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1048 0, \ 1049 (_entries) * sizeof (efx_desc_t)); \ 1050 _NOTE(CONSTANTCONDITION) \ 1051 } while (B_FALSE) 1052 1053 extern __checkReturn efx_rc_t 1054 efx_mac_select( 1055 __in efx_nic_t *enp); 1056 1057 extern void 1058 efx_mac_multicast_hash_compute( 1059 __in_ecount(6*count) uint8_t const *addrs, 1060 __in int count, 1061 __out efx_oword_t *hash_low, 1062 __out efx_oword_t *hash_high); 1063 1064 extern __checkReturn efx_rc_t 1065 efx_phy_probe( 1066 __in efx_nic_t *enp); 1067 1068 extern void 1069 efx_phy_unprobe( 1070 __in efx_nic_t *enp); 1071 1072 #if EFSYS_OPT_VPD 1073 1074 /* VPD utility functions */ 1075 1076 extern __checkReturn efx_rc_t 1077 efx_vpd_hunk_length( 1078 __in_bcount(size) caddr_t data, 1079 __in size_t size, 1080 __out size_t *lengthp); 1081 1082 extern __checkReturn efx_rc_t 1083 efx_vpd_hunk_verify( 1084 __in_bcount(size) caddr_t data, 1085 __in size_t size, 1086 __out_opt boolean_t *cksummedp); 1087 1088 extern __checkReturn efx_rc_t 1089 efx_vpd_hunk_reinit( 1090 __in_bcount(size) caddr_t data, 1091 __in size_t size, 1092 __in boolean_t wantpid); 1093 1094 extern __checkReturn efx_rc_t 1095 efx_vpd_hunk_get( 1096 __in_bcount(size) caddr_t data, 1097 __in size_t size, 1098 __in efx_vpd_tag_t tag, 1099 __in efx_vpd_keyword_t keyword, 1100 __out unsigned int *payloadp, 1101 __out uint8_t *paylenp); 1102 1103 extern __checkReturn efx_rc_t 1104 efx_vpd_hunk_next( 1105 __in_bcount(size) caddr_t data, 1106 __in size_t size, 1107 __out efx_vpd_tag_t *tagp, 1108 __out efx_vpd_keyword_t *keyword, 1109 __out_opt unsigned int *payloadp, 1110 __out_opt uint8_t *paylenp, 1111 __inout unsigned int *contp); 1112 1113 extern __checkReturn efx_rc_t 1114 efx_vpd_hunk_set( 1115 __in_bcount(size) caddr_t data, 1116 __in size_t size, 1117 __in efx_vpd_value_t *evvp); 1118 1119 #endif /* EFSYS_OPT_VPD */ 1120 1121 #if EFSYS_OPT_MCDI 1122 1123 extern __checkReturn efx_rc_t 1124 efx_mcdi_set_workaround( 1125 __in efx_nic_t *enp, 1126 __in uint32_t type, 1127 __in boolean_t enabled, 1128 __out_opt uint32_t *flagsp); 1129 1130 extern __checkReturn efx_rc_t 1131 efx_mcdi_get_workarounds( 1132 __in efx_nic_t *enp, 1133 __out_opt uint32_t *implementedp, 1134 __out_opt uint32_t *enabledp); 1135 1136 #endif /* EFSYS_OPT_MCDI */ 1137 1138 #if EFSYS_OPT_MAC_STATS 1139 1140 /* 1141 * Closed range of stats (i.e. the first and the last are included). 1142 * The last must be greater or equal (if the range is one item only) to 1143 * the first. 1144 */ 1145 struct efx_mac_stats_range { 1146 efx_mac_stat_t first; 1147 efx_mac_stat_t last; 1148 }; 1149 1150 extern efx_rc_t 1151 efx_mac_stats_mask_add_ranges( 1152 __inout_bcount(mask_size) uint32_t *maskp, 1153 __in size_t mask_size, 1154 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1155 __in unsigned int rng_count); 1156 1157 #endif /* EFSYS_OPT_MAC_STATS */ 1158 1159 #ifdef __cplusplus 1160 } 1161 #endif 1162 1163 #endif /* _SYS_EFX_IMPL_H */ 1164