1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/mutex.h>
34 #include <sys/rman.h>
35 #include <machine/bus.h>
36
37 #include <dev/ofw/ofw_bus.h>
38 #include <dev/ofw/ofw_bus_subr.h>
39
40 #include <dev/iicbus/iiconf.h>
41 #include <dev/iicbus/iicbus.h>
42
43 #include <dev/extres/clk/clk.h>
44
45 #include "iicbus_if.h"
46
47 #define RK_I2C_CON 0x00
48 #define RK_I2C_CON_EN (1 << 0)
49 #define RK_I2C_CON_MODE_SHIFT 1
50 #define RK_I2C_CON_MODE_TX 0
51 #define RK_I2C_CON_MODE_RRX 1
52 #define RK_I2C_CON_MODE_RX 2
53 #define RK_I2C_CON_MODE_RTX 3
54 #define RK_I2C_CON_MODE_MASK 0x6
55 #define RK_I2C_CON_START (1 << 3)
56 #define RK_I2C_CON_STOP (1 << 4)
57 #define RK_I2C_CON_LASTACK (1 << 5)
58 #define RK_I2C_CON_NAKSTOP (1 << 6)
59 #define RK_I2C_CON_CTRL_MASK 0xFF
60
61 #define RK_I2C_CLKDIV 0x04
62 #define RK_I2C_CLKDIVL_MASK 0xFFFF
63 #define RK_I2C_CLKDIVL_SHIFT 0
64 #define RK_I2C_CLKDIVH_MASK 0xFFFF0000
65 #define RK_I2C_CLKDIVH_SHIFT 16
66 #define RK_I2C_CLKDIV_MUL 8
67
68 #define RK_I2C_MRXADDR 0x08
69 #define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF
70 #define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x))
71
72 #define RK_I2C_MRXRADDR 0x0C
73 #define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF
74 #define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x))
75
76 #define RK_I2C_MTXCNT 0x10
77 #define RK_I2C_MTXCNT_MASK 0x3F
78
79 #define RK_I2C_MRXCNT 0x14
80 #define RK_I2C_MRXCNT_MASK 0x3F
81
82 #define RK_I2C_IEN 0x18
83 #define RK_I2C_IEN_BTFIEN (1 << 0)
84 #define RK_I2C_IEN_BRFIEN (1 << 1)
85 #define RK_I2C_IEN_MBTFIEN (1 << 2)
86 #define RK_I2C_IEN_MBRFIEN (1 << 3)
87 #define RK_I2C_IEN_STARTIEN (1 << 4)
88 #define RK_I2C_IEN_STOPIEN (1 << 5)
89 #define RK_I2C_IEN_NAKRCVIEN (1 << 6)
90 #define RK_I2C_IEN_ALL (RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
91 RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN)
92
93 #define RK_I2C_IPD 0x1C
94 #define RK_I2C_IPD_BTFIPD (1 << 0)
95 #define RK_I2C_IPD_BRFIPD (1 << 1)
96 #define RK_I2C_IPD_MBTFIPD (1 << 2)
97 #define RK_I2C_IPD_MBRFIPD (1 << 3)
98 #define RK_I2C_IPD_STARTIPD (1 << 4)
99 #define RK_I2C_IPD_STOPIPD (1 << 5)
100 #define RK_I2C_IPD_NAKRCVIPD (1 << 6)
101 #define RK_I2C_IPD_ALL (RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
102 RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD)
103
104 #define RK_I2C_FNCT 0x20
105 #define RK_I2C_FNCT_MASK 0x3F
106
107 #define RK_I2C_TXDATA_BASE 0x100
108
109 #define RK_I2C_RXDATA_BASE 0x200
110
111 /* 8 data registers, 4 bytes each. */
112 #define RK_I2C_MAX_RXTX_LEN 32
113
114 enum rk_i2c_state {
115 STATE_IDLE = 0,
116 STATE_START,
117 STATE_READ,
118 STATE_WRITE,
119 STATE_STOP
120 };
121
122 struct rk_i2c_softc {
123 device_t dev;
124 struct resource *res[2];
125 struct mtx mtx;
126 clk_t sclk;
127 clk_t pclk;
128 int busy;
129 void * intrhand;
130 uint32_t intr;
131 uint32_t ipd;
132 struct iic_msg *msg;
133 size_t cnt;
134 bool transfer_done;
135 bool nak_recv;
136 bool tx_slave_addr;
137 uint8_t mode;
138 uint8_t state;
139
140 device_t iicbus;
141 };
142
143 static struct ofw_compat_data compat_data[] = {
144 {"rockchip,rk3288-i2c", 1},
145 {"rockchip,rk3328-i2c", 1},
146 {"rockchip,rk3399-i2c", 1},
147 {NULL, 0}
148 };
149
150 static struct resource_spec rk_i2c_spec[] = {
151 { SYS_RES_MEMORY, 0, RF_ACTIVE },
152 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
153 { -1, 0 }
154 };
155
156 static int rk_i2c_probe(device_t dev);
157 static int rk_i2c_attach(device_t dev);
158 static int rk_i2c_detach(device_t dev);
159
160 #define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx)
161 #define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
162 #define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
163 #define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
164 #define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
165
166 static uint32_t
rk_i2c_get_clkdiv(struct rk_i2c_softc * sc,uint32_t speed)167 rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed)
168 {
169 uint64_t sclk_freq;
170 uint32_t clkdiv;
171 int err;
172
173 err = clk_get_freq(sc->sclk, &sclk_freq);
174 if (err != 0)
175 return (err);
176
177 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1;
178 clkdiv &= RK_I2C_CLKDIVL_MASK;
179
180 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv;
181
182 return (clkdiv);
183 }
184
185 static int
rk_i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)186 rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
187 {
188 struct rk_i2c_softc *sc;
189 uint32_t clkdiv;
190 u_int busfreq;
191
192 sc = device_get_softc(dev);
193
194 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
195
196 clkdiv = rk_i2c_get_clkdiv(sc, busfreq);
197
198 RK_I2C_LOCK(sc);
199
200 /* Set the clock divider */
201 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv);
202
203 /* Disable the module */
204 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
205
206 RK_I2C_UNLOCK(sc);
207
208 return (0);
209 }
210
211 static uint8_t
rk_i2c_fill_tx(struct rk_i2c_softc * sc)212 rk_i2c_fill_tx(struct rk_i2c_softc *sc)
213 {
214 uint32_t buf32;
215 uint8_t buf;
216 int i, j, len;
217
218 len = sc->msg->len - sc->cnt;
219 if (sc->tx_slave_addr) {
220 KASSERT(sc->cnt == 0, ("tx_slave_addr in the middle of data"));
221 len++;
222 }
223
224 if (len > RK_I2C_MAX_RXTX_LEN)
225 len = RK_I2C_MAX_RXTX_LEN;
226
227 for (i = 0; i < len; ) {
228 buf32 = 0;
229
230 /* Process next 4 bytes or whatever remains. */
231 for (j = 0; j < MIN(len - i, 4); j++) {
232 /* Fill the addr if needed */
233 if (sc->tx_slave_addr) {
234 buf = sc->msg->slave;
235 sc->tx_slave_addr = false;
236 } else {
237 KASSERT(sc->cnt < sc->msg->len,
238 ("%s: data buffer overrun", __func__));
239 buf = sc->msg->buf[sc->cnt];
240 sc->cnt++;
241 }
242 buf32 |= (uint32_t)buf << (j * 8);
243 }
244
245 KASSERT(i % 4 == 0, ("%s: misaligned write offset", __func__));
246 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + i, buf32);
247
248 i += j;
249 }
250
251 return (len);
252 }
253
254 static void
rk_i2c_drain_rx(struct rk_i2c_softc * sc)255 rk_i2c_drain_rx(struct rk_i2c_softc *sc)
256 {
257 uint32_t buf32 = 0;
258 uint8_t buf8;
259 int len;
260 int i;
261
262 if (sc->msg == NULL) {
263 device_printf(sc->dev, "No current iic msg\n");
264 return;
265 }
266
267 len = sc->msg->len - sc->cnt;
268 if (len > RK_I2C_MAX_RXTX_LEN)
269 len = RK_I2C_MAX_RXTX_LEN;
270
271 for (i = 0; i < len; i++) {
272 if (i % 4 == 0)
273 buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + i);
274
275 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF;
276 sc->msg->buf[sc->cnt++] = buf8;
277 }
278 }
279
280 static void
rk_i2c_send_stop(struct rk_i2c_softc * sc)281 rk_i2c_send_stop(struct rk_i2c_softc *sc)
282 {
283 uint32_t reg;
284
285 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN);
286
287 sc->state = STATE_STOP;
288
289 reg = RK_I2C_READ(sc, RK_I2C_CON);
290 reg |= RK_I2C_CON_STOP;
291 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
292 }
293
294 static void
rk_i2c_intr_locked(struct rk_i2c_softc * sc)295 rk_i2c_intr_locked(struct rk_i2c_softc *sc)
296 {
297 uint32_t reg;
298 int transfer_len;
299
300 sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
301
302 /* Something to handle? */
303 if ((sc->ipd & RK_I2C_IPD_ALL) == 0)
304 return;
305
306 RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd);
307 sc->ipd &= RK_I2C_IPD_ALL;
308
309 if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) {
310 /* NACK received */
311 sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD;
312 sc->nak_recv = true;
313 /* XXXX last byte !!!, signal error !!! */
314 sc->transfer_done = true;
315 sc->state = STATE_IDLE;
316 goto err;
317 }
318
319 switch (sc->state) {
320 case STATE_START:
321 /* Disable start bit */
322 reg = RK_I2C_READ(sc, RK_I2C_CON);
323 reg &= ~RK_I2C_CON_START;
324 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
325
326 if (sc->mode == RK_I2C_CON_MODE_RRX ||
327 sc->mode == RK_I2C_CON_MODE_RX) {
328 sc->state = STATE_READ;
329 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
330 RK_I2C_IEN_NAKRCVIEN);
331
332 if ((sc->msg->len - sc->cnt) > 32)
333 transfer_len = 32;
334 else {
335 transfer_len = sc->msg->len - sc->cnt;
336 reg = RK_I2C_READ(sc, RK_I2C_CON);
337 reg |= RK_I2C_CON_LASTACK;
338 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
339 }
340
341 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
342 } else {
343 sc->state = STATE_WRITE;
344 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
345 RK_I2C_IEN_NAKRCVIEN);
346
347 transfer_len = rk_i2c_fill_tx(sc);
348 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
349 }
350 break;
351 case STATE_READ:
352 rk_i2c_drain_rx(sc);
353
354 if (sc->cnt == sc->msg->len)
355 rk_i2c_send_stop(sc);
356 else {
357 sc->mode = RK_I2C_CON_MODE_RX;
358 reg = RK_I2C_READ(sc, RK_I2C_CON) & \
359 ~RK_I2C_CON_CTRL_MASK;
360 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
361 reg |= RK_I2C_CON_EN;
362
363 if ((sc->msg->len - sc->cnt) > 32)
364 transfer_len = 32;
365 else {
366 transfer_len = sc->msg->len - sc->cnt;
367 reg |= RK_I2C_CON_LASTACK;
368 }
369
370 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
371 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
372 }
373
374 break;
375 case STATE_WRITE:
376 if (sc->cnt < sc->msg->len) {
377 /* Keep writing. */
378 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
379 RK_I2C_IEN_NAKRCVIEN);
380 transfer_len = rk_i2c_fill_tx(sc);
381 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
382 break;
383 } else if (!(sc->msg->flags & IIC_M_NOSTOP)) {
384 rk_i2c_send_stop(sc);
385 break;
386 }
387 /* passthru */
388 case STATE_STOP:
389 /* Disable stop bit */
390 reg = RK_I2C_READ(sc, RK_I2C_CON);
391 reg &= ~RK_I2C_CON_STOP;
392 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
393
394 sc->transfer_done = 1;
395 sc->state = STATE_IDLE;
396 break;
397 case STATE_IDLE:
398 break;
399 }
400
401 err:
402 wakeup(sc);
403 }
404
405 static void
rk_i2c_intr(void * arg)406 rk_i2c_intr(void *arg)
407 {
408 struct rk_i2c_softc *sc;
409
410 sc = (struct rk_i2c_softc *)arg;
411
412 RK_I2C_LOCK(sc);
413 rk_i2c_intr_locked(sc);
414 RK_I2C_UNLOCK(sc);
415 }
416
417 static void
rk_i2c_start_xfer(struct rk_i2c_softc * sc,struct iic_msg * msg,boolean_t last)418 rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last)
419 {
420 uint32_t reg;
421 uint8_t len;
422
423 sc->transfer_done = false;
424 sc->nak_recv = false;
425 sc->tx_slave_addr = false;
426 sc->cnt = 0;
427 sc->state = STATE_IDLE;
428 sc->msg = msg;
429
430 reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK;
431 if (!(sc->msg->flags & IIC_M_NOSTART)) {
432 /* Stadard message */
433 if (sc->mode == RK_I2C_CON_MODE_TX) {
434 sc->tx_slave_addr = true;
435 }
436 sc->state = STATE_START;
437 reg |= RK_I2C_CON_START;
438
439 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
440 } else {
441 /* Continuation message */
442 if (sc->mode == RK_I2C_CON_MODE_RX) {
443 sc->state = STATE_READ;
444 if (last)
445 reg |= RK_I2C_CON_LASTACK;
446
447 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
448 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
449 RK_I2C_IEN_NAKRCVIEN);
450 } else {
451 sc->state = STATE_WRITE;
452 len = rk_i2c_fill_tx(sc);
453
454 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len);
455
456 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
457 RK_I2C_IEN_NAKRCVIEN);
458 }
459 }
460 reg |= RK_I2C_CON_NAKSTOP;
461 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
462 reg |= RK_I2C_CON_EN;
463 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
464 }
465
466 static int
rk_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)467 rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
468 {
469 struct rk_i2c_softc *sc;
470 uint32_t reg;
471 bool last_msg;
472 int i, j, timeout, err;
473
474 sc = device_get_softc(dev);
475
476 RK_I2C_LOCK(sc);
477
478 while (sc->busy)
479 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
480 sc->busy = 1;
481
482 /* Disable the module and interrupts */
483 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
484 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
485
486 /* Clean stale interrupts */
487 RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL);
488
489 err = 0;
490 for (i = 0; i < nmsgs; i++) {
491 /* Validate parameters. */
492 if (msgs == NULL || msgs[i].buf == NULL ||
493 msgs[i].len == 0) {
494 err = IIC_ENOTSUPP;
495 break;
496 }
497 /*
498 * If next message have NOSTART flag, then they both
499 * should be same type (read/write) and same address.
500 */
501 if (i < nmsgs - 1) {
502 if ((msgs[i + 1].flags & IIC_M_NOSTART) &&
503 ((msgs[i].flags & IIC_M_RD) !=
504 (msgs[i + 1].flags & IIC_M_RD) ||
505 (msgs[i].slave != msgs[i + 1].slave))) {
506 err = IIC_ENOTSUPP;
507 break;
508 }
509 }
510 /*
511 * Detect simple register read case.
512 * The first message should be IIC_M_WR | IIC_M_NOSTOP,
513 * next pure IIC_M_RD (no other flags allowed). Both
514 * messages should have same slave address.
515 */
516
517 if (nmsgs - i >= 2 && msgs[i].len < 4 &&
518 msgs[i].flags == (IIC_M_WR | IIC_M_NOSTOP) &&
519 msgs[i + 1].flags == IIC_M_RD &&
520 (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) {
521 sc->mode = RK_I2C_CON_MODE_RRX;
522
523 /* Write slave address */
524 reg = msgs[i].slave & ~LSB;
525 reg |= RK_I2C_MRXADDR_VALID(0);
526 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
527
528 /* Write slave register address */
529 reg = 0;
530 for (j = 0; j < msgs[i].len ; j++) {
531 reg |= (uint32_t)msgs[i].buf[j] << (j * 8);
532 reg |= RK_I2C_MRXADDR_VALID(j);
533 }
534 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);
535
536 i++;
537 } else {
538 if (msgs[i].flags & IIC_M_RD) {
539 if (msgs[i].flags & IIC_M_NOSTART) {
540 sc->mode = RK_I2C_CON_MODE_RX;
541 } else {
542 sc->mode = RK_I2C_CON_MODE_RRX;
543 reg = msgs[i].slave & ~LSB;
544 reg |= RK_I2C_MRXADDR_VALID(0);
545 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
546 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0);
547 }
548 } else {
549 sc->mode = RK_I2C_CON_MODE_TX;
550 }
551 }
552 /* last message ? */
553 last_msg = (i >= nmsgs - 1) ||
554 !(msgs[i + 1].flags & IIC_M_NOSTART);
555 rk_i2c_start_xfer(sc, msgs + i, last_msg);
556
557 if (cold) {
558 for(timeout = 10000; timeout > 0; timeout--) {
559 rk_i2c_intr_locked(sc);
560 if (sc->transfer_done)
561 break;
562 DELAY(1000);
563 }
564 if (timeout <= 0)
565 err = IIC_ETIMEOUT;
566 } else {
567 while (err == 0 && !sc->transfer_done) {
568 err = msleep(sc, &sc->mtx, PZERO, "rk_i2c",
569 10 * hz);
570 }
571 }
572 }
573
574 /* Disable the module and interrupts */
575 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
576 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
577
578 sc->busy = 0;
579
580 if (sc->nak_recv)
581 err = IIC_ENOACK;
582
583 RK_I2C_UNLOCK(sc);
584 return (err);
585 }
586
587 static int
rk_i2c_probe(device_t dev)588 rk_i2c_probe(device_t dev)
589 {
590
591 if (!ofw_bus_status_okay(dev))
592 return (ENXIO);
593 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
594 return (ENXIO);
595
596 device_set_desc(dev, "RockChip I2C");
597 return (BUS_PROBE_DEFAULT);
598 }
599
600 static int
rk_i2c_attach(device_t dev)601 rk_i2c_attach(device_t dev)
602 {
603 struct rk_i2c_softc *sc;
604 int error;
605
606 sc = device_get_softc(dev);
607 sc->dev = dev;
608
609 mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF);
610
611 if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) {
612 device_printf(dev, "cannot allocate resources for device\n");
613 error = ENXIO;
614 goto fail;
615 }
616
617 if (bus_setup_intr(dev, sc->res[1],
618 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc,
619 &sc->intrhand)) {
620 bus_release_resources(dev, rk_i2c_spec, sc->res);
621 device_printf(dev, "cannot setup interrupt handler\n");
622 return (ENXIO);
623 }
624
625 clk_set_assigned(dev, ofw_bus_get_node(dev));
626
627 /* Activate the module clocks. */
628 error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk);
629 if (error != 0) {
630 device_printf(dev, "cannot get i2c clock\n");
631 goto fail;
632 }
633 error = clk_enable(sc->sclk);
634 if (error != 0) {
635 device_printf(dev, "cannot enable i2c clock\n");
636 goto fail;
637 }
638 /* pclk clock is optional. */
639 error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
640 if (error != 0 && error != ENOENT) {
641 device_printf(dev, "cannot get pclk clock\n");
642 goto fail;
643 }
644 if (sc->pclk != NULL) {
645 error = clk_enable(sc->pclk);
646 if (error != 0) {
647 device_printf(dev, "cannot enable pclk clock\n");
648 goto fail;
649 }
650 }
651
652 sc->iicbus = device_add_child(dev, "iicbus", -1);
653 if (sc->iicbus == NULL) {
654 device_printf(dev, "cannot add iicbus child device\n");
655 error = ENXIO;
656 goto fail;
657 }
658
659 bus_generic_attach(dev);
660
661 return (0);
662
663 fail:
664 if (rk_i2c_detach(dev) != 0)
665 device_printf(dev, "Failed to detach\n");
666 return (error);
667 }
668
669 static int
rk_i2c_detach(device_t dev)670 rk_i2c_detach(device_t dev)
671 {
672 struct rk_i2c_softc *sc;
673 int error;
674
675 sc = device_get_softc(dev);
676
677 if ((error = bus_generic_detach(dev)) != 0)
678 return (error);
679
680 if (sc->iicbus != NULL)
681 if ((error = device_delete_child(dev, sc->iicbus)) != 0)
682 return (error);
683
684 if (sc->sclk != NULL)
685 clk_release(sc->sclk);
686 if (sc->pclk != NULL)
687 clk_release(sc->pclk);
688
689 if (sc->intrhand != NULL)
690 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
691
692 bus_release_resources(dev, rk_i2c_spec, sc->res);
693
694 mtx_destroy(&sc->mtx);
695
696 return (0);
697 }
698
699 static phandle_t
rk_i2c_get_node(device_t bus,device_t dev)700 rk_i2c_get_node(device_t bus, device_t dev)
701 {
702
703 return ofw_bus_get_node(bus);
704 }
705
706 static device_method_t rk_i2c_methods[] = {
707 DEVMETHOD(device_probe, rk_i2c_probe),
708 DEVMETHOD(device_attach, rk_i2c_attach),
709 DEVMETHOD(device_detach, rk_i2c_detach),
710
711 /* OFW methods */
712 DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node),
713
714 DEVMETHOD(iicbus_callback, iicbus_null_callback),
715 DEVMETHOD(iicbus_reset, rk_i2c_reset),
716 DEVMETHOD(iicbus_transfer, rk_i2c_transfer),
717
718 DEVMETHOD_END
719 };
720
721 static driver_t rk_i2c_driver = {
722 "rk_i2c",
723 rk_i2c_methods,
724 sizeof(struct rk_i2c_softc),
725 };
726
727 EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, 0, 0,
728 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
729 EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver,
730 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
731 MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1);
732 MODULE_VERSION(rk_i2c, 1);
733