1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2001 George Reid <[email protected]>
5 * Copyright (c) 1999 Cameron Grant <[email protected]>
6 * Copyright (c) 1997,1998 Luigi Rizzo
7 * Copyright (c) 1994,1995 Hannu Savolainen
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #ifdef HAVE_KERNEL_OPTION_HEADERS
33 #include "opt_snd.h"
34 #endif
35
36 #include <dev/sound/pcm/sound.h>
37
38 SND_DECLARE_FILE("$FreeBSD$");
39
40 /* board-specific include files */
41 #include <dev/sound/isa/mss.h>
42 #include <dev/sound/isa/sb.h>
43 #include <dev/sound/chip.h>
44
45 #include <isa/isavar.h>
46
47 #include "mixer_if.h"
48
49 #define MSS_DEFAULT_BUFSZ (4096)
50 #define MSS_INDEXED_REGS 0x20
51 #define OPL_INDEXED_REGS 0x19
52
53 struct mss_info;
54
55 struct mss_chinfo {
56 struct mss_info *parent;
57 struct pcm_channel *channel;
58 struct snd_dbuf *buffer;
59 int dir;
60 u_int32_t fmt, blksz;
61 };
62
63 struct mss_info {
64 struct resource *io_base; /* primary I/O address for the board */
65 int io_rid;
66 struct resource *conf_base; /* and the opti931 also has a config space */
67 int conf_rid;
68 struct resource *irq;
69 int irq_rid;
70 struct resource *drq1; /* play */
71 int drq1_rid;
72 struct resource *drq2; /* rec */
73 int drq2_rid;
74 void *ih;
75 bus_dma_tag_t parent_dmat;
76 struct mtx *lock;
77
78 char mss_indexed_regs[MSS_INDEXED_REGS];
79 char opl_indexed_regs[OPL_INDEXED_REGS];
80 int bd_id; /* used to hold board-id info, eg. sb version,
81 * mss codec type, etc. etc.
82 */
83 int opti_offset; /* offset from config_base for opti931 */
84 u_long bd_flags; /* board-specific flags */
85 int optibase; /* base address for OPTi9xx config */
86 struct resource *indir; /* Indirect register index address */
87 int indir_rid;
88 int password; /* password for opti9xx cards */
89 int passwdreg; /* password register */
90 unsigned int bufsize;
91 struct mss_chinfo pch, rch;
92 };
93
94 static int mss_probe(device_t dev);
95 static int mss_attach(device_t dev);
96
97 static driver_intr_t mss_intr;
98
99 /* prototypes for local functions */
100 static int mss_detect(device_t dev, struct mss_info *mss);
101 static int opti_detect(device_t dev, struct mss_info *mss);
102 static char *ymf_test(device_t dev, struct mss_info *mss);
103 static void ad_unmute(struct mss_info *mss);
104
105 /* mixer set funcs */
106 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
107 static int mss_set_recsrc(struct mss_info *mss, int mask);
108
109 /* io funcs */
110 static int ad_wait_init(struct mss_info *mss, int x);
111 static int ad_read(struct mss_info *mss, int reg);
112 static void ad_write(struct mss_info *mss, int reg, u_char data);
113 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
114 static void ad_enter_MCE(struct mss_info *mss);
115 static void ad_leave_MCE(struct mss_info *mss);
116
117 /* OPTi-specific functions */
118 static void opti_write(struct mss_info *mss, u_char reg,
119 u_char data);
120 static u_char opti_read(struct mss_info *mss, u_char reg);
121 static int opti_init(device_t dev, struct mss_info *mss);
122
123 /* io primitives */
124 static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
125 static u_char conf_rd(struct mss_info *mss, u_char reg);
126
127 static int pnpmss_probe(device_t dev);
128 static int pnpmss_attach(device_t dev);
129
130 static driver_intr_t opti931_intr;
131
132 static u_int32_t mss_fmt[] = {
133 SND_FORMAT(AFMT_U8, 1, 0),
134 SND_FORMAT(AFMT_U8, 2, 0),
135 SND_FORMAT(AFMT_S16_LE, 1, 0),
136 SND_FORMAT(AFMT_S16_LE, 2, 0),
137 SND_FORMAT(AFMT_MU_LAW, 1, 0),
138 SND_FORMAT(AFMT_MU_LAW, 2, 0),
139 SND_FORMAT(AFMT_A_LAW, 1, 0),
140 SND_FORMAT(AFMT_A_LAW, 2, 0),
141 0
142 };
143 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
144
145 static u_int32_t guspnp_fmt[] = {
146 SND_FORMAT(AFMT_U8, 1, 0),
147 SND_FORMAT(AFMT_U8, 2, 0),
148 SND_FORMAT(AFMT_S16_LE, 1, 0),
149 SND_FORMAT(AFMT_S16_LE, 2, 0),
150 SND_FORMAT(AFMT_A_LAW, 1, 0),
151 SND_FORMAT(AFMT_A_LAW, 2, 0),
152 0
153 };
154 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
155
156 static u_int32_t opti931_fmt[] = {
157 SND_FORMAT(AFMT_U8, 1, 0),
158 SND_FORMAT(AFMT_U8, 2, 0),
159 SND_FORMAT(AFMT_S16_LE, 1, 0),
160 SND_FORMAT(AFMT_S16_LE, 2, 0),
161 0
162 };
163 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
164
165 #define MD_AD1848 0x91
166 #define MD_AD1845 0x92
167 #define MD_CS42XX 0xA1
168 #define MD_CS423X 0xA2
169 #define MD_OPTI930 0xB0
170 #define MD_OPTI931 0xB1
171 #define MD_OPTI925 0xB2
172 #define MD_OPTI924 0xB3
173 #define MD_GUSPNP 0xB8
174 #define MD_GUSMAX 0xB9
175 #define MD_YM0020 0xC1
176 #define MD_VIVO 0xD1
177
178 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
179
180 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
181
182 static void
mss_lock(struct mss_info * mss)183 mss_lock(struct mss_info *mss)
184 {
185 snd_mtxlock(mss->lock);
186 }
187
188 static void
mss_unlock(struct mss_info * mss)189 mss_unlock(struct mss_info *mss)
190 {
191 snd_mtxunlock(mss->lock);
192 }
193
194 static int
port_rd(struct resource * port,int off)195 port_rd(struct resource *port, int off)
196 {
197 if (port)
198 return bus_space_read_1(rman_get_bustag(port),
199 rman_get_bushandle(port),
200 off);
201 else
202 return -1;
203 }
204
205 static void
port_wr(struct resource * port,int off,u_int8_t data)206 port_wr(struct resource *port, int off, u_int8_t data)
207 {
208 if (port)
209 bus_space_write_1(rman_get_bustag(port),
210 rman_get_bushandle(port),
211 off, data);
212 }
213
214 static int
io_rd(struct mss_info * mss,int reg)215 io_rd(struct mss_info *mss, int reg)
216 {
217 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
218 return port_rd(mss->io_base, reg);
219 }
220
221 static void
io_wr(struct mss_info * mss,int reg,u_int8_t data)222 io_wr(struct mss_info *mss, int reg, u_int8_t data)
223 {
224 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
225 port_wr(mss->io_base, reg, data);
226 }
227
228 static void
conf_wr(struct mss_info * mss,u_char reg,u_char value)229 conf_wr(struct mss_info *mss, u_char reg, u_char value)
230 {
231 port_wr(mss->conf_base, 0, reg);
232 port_wr(mss->conf_base, 1, value);
233 }
234
235 static u_char
conf_rd(struct mss_info * mss,u_char reg)236 conf_rd(struct mss_info *mss, u_char reg)
237 {
238 port_wr(mss->conf_base, 0, reg);
239 return port_rd(mss->conf_base, 1);
240 }
241
242 static void
opti_wr(struct mss_info * mss,u_char reg,u_char value)243 opti_wr(struct mss_info *mss, u_char reg, u_char value)
244 {
245 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
246 port_wr(mss->conf_base, mss->opti_offset + 1, value);
247 }
248
249 static u_char
opti_rd(struct mss_info * mss,u_char reg)250 opti_rd(struct mss_info *mss, u_char reg)
251 {
252 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
253 return port_rd(mss->conf_base, mss->opti_offset + 1);
254 }
255
256 static void
gus_wr(struct mss_info * mss,u_char reg,u_char value)257 gus_wr(struct mss_info *mss, u_char reg, u_char value)
258 {
259 port_wr(mss->conf_base, 3, reg);
260 port_wr(mss->conf_base, 5, value);
261 }
262
263 static u_char
gus_rd(struct mss_info * mss,u_char reg)264 gus_rd(struct mss_info *mss, u_char reg)
265 {
266 port_wr(mss->conf_base, 3, reg);
267 return port_rd(mss->conf_base, 5);
268 }
269
270 static void
mss_release_resources(struct mss_info * mss,device_t dev)271 mss_release_resources(struct mss_info *mss, device_t dev)
272 {
273 if (mss->irq) {
274 if (mss->ih)
275 bus_teardown_intr(dev, mss->irq, mss->ih);
276 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
277 mss->irq);
278 mss->irq = NULL;
279 }
280 if (mss->drq2) {
281 if (mss->drq2 != mss->drq1) {
282 isa_dma_release(rman_get_start(mss->drq2));
283 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
284 mss->drq2);
285 }
286 mss->drq2 = NULL;
287 }
288 if (mss->drq1) {
289 isa_dma_release(rman_get_start(mss->drq1));
290 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
291 mss->drq1);
292 mss->drq1 = NULL;
293 }
294 if (mss->io_base) {
295 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
296 mss->io_base);
297 mss->io_base = NULL;
298 }
299 if (mss->conf_base) {
300 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
301 mss->conf_base);
302 mss->conf_base = NULL;
303 }
304 if (mss->indir) {
305 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
306 mss->indir);
307 mss->indir = NULL;
308 }
309 if (mss->parent_dmat) {
310 bus_dma_tag_destroy(mss->parent_dmat);
311 mss->parent_dmat = 0;
312 }
313 if (mss->lock) snd_mtxfree(mss->lock);
314
315 free(mss, M_DEVBUF);
316 }
317
318 static int
mss_alloc_resources(struct mss_info * mss,device_t dev)319 mss_alloc_resources(struct mss_info *mss, device_t dev)
320 {
321 int pdma, rdma, ok = 1;
322 if (!mss->io_base)
323 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
324 &mss->io_rid, RF_ACTIVE);
325 if (!mss->irq)
326 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
327 &mss->irq_rid, RF_ACTIVE);
328 if (!mss->drq1)
329 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
330 &mss->drq1_rid,
331 RF_ACTIVE);
332 if (mss->conf_rid >= 0 && !mss->conf_base)
333 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
334 &mss->conf_rid,
335 RF_ACTIVE);
336 if (mss->drq2_rid >= 0 && !mss->drq2)
337 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
338 &mss->drq2_rid,
339 RF_ACTIVE);
340
341 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
342 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
343 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
344
345 if (ok) {
346 pdma = rman_get_start(mss->drq1);
347 isa_dma_acquire(pdma);
348 isa_dmainit(pdma, mss->bufsize);
349 mss->bd_flags &= ~BD_F_DUPLEX;
350 if (mss->drq2) {
351 rdma = rman_get_start(mss->drq2);
352 isa_dma_acquire(rdma);
353 isa_dmainit(rdma, mss->bufsize);
354 mss->bd_flags |= BD_F_DUPLEX;
355 } else mss->drq2 = mss->drq1;
356 }
357 return ok;
358 }
359
360 /*
361 * The various mixers use a variety of bitmasks etc. The Voxware
362 * driver had a very nice technique to describe a mixer and interface
363 * to it. A table defines, for each channel, which register, bits,
364 * offset, polarity to use. This procedure creates the new value
365 * using the table and the old value.
366 */
367
368 static void
change_bits(mixer_tab * t,u_char * regval,int dev,int chn,int newval)369 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
370 {
371 u_char mask;
372 int shift;
373
374 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
375 "r %d p %d bit %d off %d\n",
376 dev, chn, newval, *regval,
377 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
378 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
379
380 if ( (*t)[dev][chn].polarity == 1) /* reverse */
381 newval = 100 - newval ;
382
383 mask = (1 << (*t)[dev][chn].nbits) - 1;
384 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
385 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
386
387 *regval &= ~(mask << shift); /* Filter out the previous value */
388 *regval |= (newval & mask) << shift; /* Set the new value */
389 }
390
391 /* -------------------------------------------------------------------- */
392 /* only one source can be set... */
393 static int
mss_set_recsrc(struct mss_info * mss,int mask)394 mss_set_recsrc(struct mss_info *mss, int mask)
395 {
396 u_char recdev;
397
398 switch (mask) {
399 case SOUND_MASK_LINE:
400 case SOUND_MASK_LINE3:
401 recdev = 0;
402 break;
403
404 case SOUND_MASK_CD:
405 case SOUND_MASK_LINE1:
406 recdev = 0x40;
407 break;
408
409 case SOUND_MASK_IMIX:
410 recdev = 0xc0;
411 break;
412
413 case SOUND_MASK_MIC:
414 default:
415 mask = SOUND_MASK_MIC;
416 recdev = 0x80;
417 }
418 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
419 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
420 return mask;
421 }
422
423 /* there are differences in the mixer depending on the actual sound card. */
424 static int
mss_mixer_set(struct mss_info * mss,int dev,int left,int right)425 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
426 {
427 int regoffs;
428 mixer_tab *mix_d;
429 u_char old, val;
430
431 switch (mss->bd_id) {
432 case MD_OPTI931:
433 mix_d = &opti931_devices;
434 break;
435 case MD_OPTI930:
436 mix_d = &opti930_devices;
437 break;
438 default:
439 mix_d = &mix_devices;
440 }
441
442 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
443 DEB(printf("nbits = 0 for dev %d\n", dev));
444 return -1;
445 }
446
447 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
448
449 /* Set the left channel */
450
451 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
452 old = val = ad_read(mss, regoffs);
453 /* if volume is 0, mute chan. Otherwise, unmute. */
454 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
455 change_bits(mix_d, &val, dev, LEFT_CHN, left);
456 ad_write(mss, regoffs, val);
457
458 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
459 dev, regoffs, old, val));
460
461 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
462 /* Set the right channel */
463 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
464 old = val = ad_read(mss, regoffs);
465 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
466 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
467 ad_write(mss, regoffs, val);
468
469 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
470 dev, regoffs, old, val));
471 }
472 return 0; /* success */
473 }
474
475 /* -------------------------------------------------------------------- */
476
477 static int
mssmix_init(struct snd_mixer * m)478 mssmix_init(struct snd_mixer *m)
479 {
480 struct mss_info *mss = mix_getdevinfo(m);
481
482 mix_setdevs(m, MODE2_MIXER_DEVICES);
483 mix_setrecdevs(m, MSS_REC_DEVICES);
484 switch(mss->bd_id) {
485 case MD_OPTI930:
486 mix_setdevs(m, OPTI930_MIXER_DEVICES);
487 break;
488
489 case MD_OPTI931:
490 mix_setdevs(m, OPTI931_MIXER_DEVICES);
491 mss_lock(mss);
492 ad_write(mss, 20, 0x88);
493 ad_write(mss, 21, 0x88);
494 mss_unlock(mss);
495 break;
496
497 case MD_AD1848:
498 mix_setdevs(m, MODE1_MIXER_DEVICES);
499 break;
500
501 case MD_GUSPNP:
502 case MD_GUSMAX:
503 /* this is only necessary in mode 3 ... */
504 mss_lock(mss);
505 ad_write(mss, 22, 0x88);
506 ad_write(mss, 23, 0x88);
507 mss_unlock(mss);
508 break;
509 }
510 return 0;
511 }
512
513 static int
mssmix_set(struct snd_mixer * m,unsigned dev,unsigned left,unsigned right)514 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
515 {
516 struct mss_info *mss = mix_getdevinfo(m);
517
518 mss_lock(mss);
519 mss_mixer_set(mss, dev, left, right);
520 mss_unlock(mss);
521
522 return left | (right << 8);
523 }
524
525 static u_int32_t
mssmix_setrecsrc(struct snd_mixer * m,u_int32_t src)526 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
527 {
528 struct mss_info *mss = mix_getdevinfo(m);
529
530 mss_lock(mss);
531 src = mss_set_recsrc(mss, src);
532 mss_unlock(mss);
533 return src;
534 }
535
536 static kobj_method_t mssmix_mixer_methods[] = {
537 KOBJMETHOD(mixer_init, mssmix_init),
538 KOBJMETHOD(mixer_set, mssmix_set),
539 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
540 KOBJMETHOD_END
541 };
542 MIXER_DECLARE(mssmix_mixer);
543
544 /* -------------------------------------------------------------------- */
545
546 static int
ymmix_init(struct snd_mixer * m)547 ymmix_init(struct snd_mixer *m)
548 {
549 struct mss_info *mss = mix_getdevinfo(m);
550
551 mssmix_init(m);
552 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
553 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
554 /* Set master volume */
555 mss_lock(mss);
556 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
557 conf_wr(mss, OPL3SAx_VOLUMER, 7);
558 mss_unlock(mss);
559
560 return 0;
561 }
562
563 static int
ymmix_set(struct snd_mixer * m,unsigned dev,unsigned left,unsigned right)564 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
565 {
566 struct mss_info *mss = mix_getdevinfo(m);
567 int t, l, r;
568
569 mss_lock(mss);
570 switch (dev) {
571 case SOUND_MIXER_VOLUME:
572 if (left) t = 15 - (left * 15) / 100;
573 else t = 0x80; /* mute */
574 conf_wr(mss, OPL3SAx_VOLUMEL, t);
575 if (right) t = 15 - (right * 15) / 100;
576 else t = 0x80; /* mute */
577 conf_wr(mss, OPL3SAx_VOLUMER, t);
578 break;
579
580 case SOUND_MIXER_MIC:
581 t = left;
582 if (left) t = 31 - (left * 31) / 100;
583 else t = 0x80; /* mute */
584 conf_wr(mss, OPL3SAx_MIC, t);
585 break;
586
587 case SOUND_MIXER_BASS:
588 l = (left * 7) / 100;
589 r = (right * 7) / 100;
590 t = (r << 4) | l;
591 conf_wr(mss, OPL3SAx_BASS, t);
592 break;
593
594 case SOUND_MIXER_TREBLE:
595 l = (left * 7) / 100;
596 r = (right * 7) / 100;
597 t = (r << 4) | l;
598 conf_wr(mss, OPL3SAx_TREBLE, t);
599 break;
600
601 default:
602 mss_mixer_set(mss, dev, left, right);
603 }
604 mss_unlock(mss);
605
606 return left | (right << 8);
607 }
608
609 static u_int32_t
ymmix_setrecsrc(struct snd_mixer * m,u_int32_t src)610 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
611 {
612 struct mss_info *mss = mix_getdevinfo(m);
613 mss_lock(mss);
614 src = mss_set_recsrc(mss, src);
615 mss_unlock(mss);
616 return src;
617 }
618
619 static kobj_method_t ymmix_mixer_methods[] = {
620 KOBJMETHOD(mixer_init, ymmix_init),
621 KOBJMETHOD(mixer_set, ymmix_set),
622 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
623 KOBJMETHOD_END
624 };
625 MIXER_DECLARE(ymmix_mixer);
626
627 /* -------------------------------------------------------------------- */
628 /*
629 * XXX This might be better off in the gusc driver.
630 */
631 static void
gusmax_setup(struct mss_info * mss,device_t dev,struct resource * alt)632 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
633 {
634 static const unsigned char irq_bits[16] = {
635 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
636 };
637 static const unsigned char dma_bits[8] = {
638 0, 1, 0, 2, 0, 3, 4, 5
639 };
640 device_t parent = device_get_parent(dev);
641 unsigned char irqctl, dmactl;
642 int s;
643
644 s = splhigh();
645
646 port_wr(alt, 0x0f, 0x05);
647 port_wr(alt, 0x00, 0x0c);
648 port_wr(alt, 0x0b, 0x00);
649
650 port_wr(alt, 0x0f, 0x00);
651
652 irqctl = irq_bits[isa_get_irq(parent)];
653 /* Share the IRQ with the MIDI driver. */
654 irqctl |= 0x40;
655 dmactl = dma_bits[isa_get_drq(parent)];
656 if (device_get_flags(parent) & DV_F_DUAL_DMA)
657 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
658 << 3;
659
660 /*
661 * Set the DMA and IRQ control latches.
662 */
663 port_wr(alt, 0x00, 0x0c);
664 port_wr(alt, 0x0b, dmactl | 0x80);
665 port_wr(alt, 0x00, 0x4c);
666 port_wr(alt, 0x0b, irqctl);
667
668 port_wr(alt, 0x00, 0x0c);
669 port_wr(alt, 0x0b, dmactl);
670 port_wr(alt, 0x00, 0x4c);
671 port_wr(alt, 0x0b, irqctl);
672
673 port_wr(mss->conf_base, 2, 0);
674 port_wr(alt, 0x00, 0x0c);
675 port_wr(mss->conf_base, 2, 0);
676
677 splx(s);
678 }
679
680 static int
mss_init(struct mss_info * mss,device_t dev)681 mss_init(struct mss_info *mss, device_t dev)
682 {
683 u_char r6, r9;
684 struct resource *alt;
685 int rid, tmp;
686
687 mss->bd_flags |= BD_F_MCE_BIT;
688 switch(mss->bd_id) {
689 case MD_OPTI931:
690 /*
691 * The MED3931 v.1.0 allocates 3 bytes for the config
692 * space, whereas v.2.0 allocates 4 bytes. What I know
693 * for sure is that the upper two ports must be used,
694 * and they should end on a boundary of 4 bytes. So I
695 * need the following trick.
696 */
697 mss->opti_offset =
698 (rman_get_start(mss->conf_base) & ~3) + 2
699 - rman_get_start(mss->conf_base);
700 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
701 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
702 ad_write(mss, 10, 2); /* enable interrupts */
703 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
704 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
705 break;
706
707 case MD_GUSPNP:
708 case MD_GUSMAX:
709 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
710 DELAY(1000 * 30);
711 /* release reset and enable DAC */
712 gus_wr(mss, 0x4c /* _URSTI */, 3);
713 DELAY(1000 * 30);
714 /* end of reset */
715
716 rid = 0;
717 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
718 RF_ACTIVE);
719 if (alt == NULL) {
720 printf("XXX couldn't init GUS PnP/MAX\n");
721 break;
722 }
723 port_wr(alt, 0, 0xC); /* enable int and dma */
724 if (mss->bd_id == MD_GUSMAX)
725 gusmax_setup(mss, dev, alt);
726 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
727
728 /*
729 * unmute left & right line. Need to go in mode3, unmute,
730 * and back to mode 2
731 */
732 tmp = ad_read(mss, 0x0c);
733 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
734 ad_write(mss, 0x19, 0); /* unmute left */
735 ad_write(mss, 0x1b, 0); /* unmute right */
736 ad_write(mss, 0x0c, tmp); /* restore old mode */
737
738 /* send codec interrupts on irq1 and only use that one */
739 gus_wr(mss, 0x5a, 0x4f);
740
741 /* enable access to hidden regs */
742 tmp = gus_rd(mss, 0x5b /* IVERI */);
743 gus_wr(mss, 0x5b, tmp | 1);
744 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
745 break;
746
747 case MD_YM0020:
748 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
749 r6 = conf_rd(mss, OPL3SAx_DMACONF);
750 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
751 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
752 /* yamaha - set volume to max */
753 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
754 conf_wr(mss, OPL3SAx_VOLUMER, 0);
755 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
756 break;
757 }
758 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
759 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
760 ad_enter_MCE(mss);
761 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
762 ad_leave_MCE(mss);
763 ad_write(mss, 10, 2); /* int enable */
764 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
765 /* the following seem required on the CS4232 */
766 ad_unmute(mss);
767 return 0;
768 }
769
770 /*
771 * main irq handler for the CS423x. The OPTi931 code is
772 * a separate one.
773 * The correct way to operate for a device with multiple internal
774 * interrupt sources is to loop on the status register and ack
775 * interrupts until all interrupts are served and none are reported. At
776 * this point the IRQ line to the ISA IRQ controller should go low
777 * and be raised at the next interrupt.
778 *
779 * Since the ISA IRQ controller is sent EOI _before_ passing control
780 * to the isr, it might happen that we serve an interrupt early, in
781 * which case the status register at the next interrupt should just
782 * say that there are no more interrupts...
783 */
784
785 static void
mss_intr(void * arg)786 mss_intr(void *arg)
787 {
788 struct mss_info *mss = arg;
789 u_char c = 0, served = 0;
790 int i;
791
792 DEB(printf("mss_intr\n"));
793 mss_lock(mss);
794 ad_read(mss, 11); /* fake read of status bits */
795
796 /* loop until there are interrupts, but no more than 10 times. */
797 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
798 /* get exact reason for full-duplex boards */
799 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
800 c &= ~served;
801 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
802 served |= 0x10;
803 mss_unlock(mss);
804 chn_intr(mss->pch.channel);
805 mss_lock(mss);
806 }
807 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
808 served |= 0x20;
809 mss_unlock(mss);
810 chn_intr(mss->rch.channel);
811 mss_lock(mss);
812 }
813 /* now ack the interrupt */
814 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
815 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
816 }
817 if (i == 10) {
818 BVDDB(printf("mss_intr: irq, but not from mss\n"));
819 } else if (served == 0) {
820 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
821 /*
822 * this should not happen... I have no idea what to do now.
823 * maybe should do a sanity check and restart dmas ?
824 */
825 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
826 }
827 mss_unlock(mss);
828 }
829
830 /*
831 * AD_WAIT_INIT waits if we are initializing the board and
832 * we cannot modify its settings
833 */
834 static int
ad_wait_init(struct mss_info * mss,int x)835 ad_wait_init(struct mss_info *mss, int x)
836 {
837 int arg = x, n = 0; /* to shut up the compiler... */
838 for (; x > 0; x--)
839 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
840 else return n;
841 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
842 return n;
843 }
844
845 static int
ad_read(struct mss_info * mss,int reg)846 ad_read(struct mss_info *mss, int reg)
847 {
848 int x;
849
850 ad_wait_init(mss, 201000);
851 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
852 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
853 x = io_rd(mss, MSS_IDATA);
854 /* printf("ad_read %d, %x\n", reg, x); */
855 return x;
856 }
857
858 static void
ad_write(struct mss_info * mss,int reg,u_char data)859 ad_write(struct mss_info *mss, int reg, u_char data)
860 {
861 int x;
862
863 /* printf("ad_write %d, %x\n", reg, data); */
864 ad_wait_init(mss, 1002000);
865 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
866 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
867 io_wr(mss, MSS_IDATA, data);
868 }
869
870 static void
ad_write_cnt(struct mss_info * mss,int reg,u_short cnt)871 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
872 {
873 ad_write(mss, reg+1, cnt & 0xff);
874 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
875 }
876
877 static void
wait_for_calibration(struct mss_info * mss)878 wait_for_calibration(struct mss_info *mss)
879 {
880 int t;
881
882 /*
883 * Wait until the auto calibration process has finished.
884 *
885 * 1) Wait until the chip becomes ready (reads don't return 0x80).
886 * 2) Wait until the ACI bit of I11 gets on
887 * 3) Wait until the ACI bit of I11 gets off
888 */
889
890 t = ad_wait_init(mss, 1000000);
891 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
892
893 /*
894 * The calibration mode for chips that support it is set so that
895 * we never see ACI go on.
896 */
897 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
898 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
899 } else {
900 /*
901 * XXX This should only be enabled for cards that *really*
902 * need it. Are there any?
903 */
904 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
905 }
906 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
907 }
908
909 static void
ad_unmute(struct mss_info * mss)910 ad_unmute(struct mss_info *mss)
911 {
912 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
913 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
914 }
915
916 static void
ad_enter_MCE(struct mss_info * mss)917 ad_enter_MCE(struct mss_info *mss)
918 {
919 int prev;
920
921 mss->bd_flags |= BD_F_MCE_BIT;
922 ad_wait_init(mss, 203000);
923 prev = io_rd(mss, MSS_INDEX);
924 prev &= ~MSS_TRD;
925 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
926 }
927
928 static void
ad_leave_MCE(struct mss_info * mss)929 ad_leave_MCE(struct mss_info *mss)
930 {
931 u_char prev;
932
933 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
934 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
935 return;
936 }
937
938 ad_wait_init(mss, 1000000);
939
940 mss->bd_flags &= ~BD_F_MCE_BIT;
941
942 prev = io_rd(mss, MSS_INDEX);
943 prev &= ~MSS_TRD;
944 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
945 wait_for_calibration(mss);
946 }
947
948 static int
mss_speed(struct mss_chinfo * ch,int speed)949 mss_speed(struct mss_chinfo *ch, int speed)
950 {
951 struct mss_info *mss = ch->parent;
952 /*
953 * In the CS4231, the low 4 bits of I8 are used to hold the
954 * sample rate. Only a fixed number of values is allowed. This
955 * table lists them. The speed-setting routines scans the table
956 * looking for the closest match. This is the only supported method.
957 *
958 * In the CS4236, there is an alternate metod (which we do not
959 * support yet) which provides almost arbitrary frequency setting.
960 * In the AD1845, it looks like the sample rate can be
961 * almost arbitrary, and written directly to a register.
962 * In the OPTi931, there is a SB command which provides for
963 * almost arbitrary frequency setting.
964 *
965 */
966 ad_enter_MCE(mss);
967 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
968 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
969 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
970 /* XXX must also do something in I27 for the ad1845 */
971 } else {
972 int i, sel = 0; /* assume entry 0 does not contain -1 */
973 static int speeds[] =
974 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
975 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
976
977 for (i = 1; i < 16; i++)
978 if (speeds[i] > 0 &&
979 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
980 speed = speeds[sel];
981 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
982 ad_wait_init(mss, 10000);
983 }
984 ad_leave_MCE(mss);
985
986 return speed;
987 }
988
989 /*
990 * mss_format checks that the format is supported (or defaults to AFMT_U8)
991 * and returns the bit setting for the 1848 register corresponding to
992 * the desired format.
993 *
994 * fixed lr970724
995 */
996
997 static int
mss_format(struct mss_chinfo * ch,u_int32_t format)998 mss_format(struct mss_chinfo *ch, u_int32_t format)
999 {
1000 struct mss_info *mss = ch->parent;
1001 int i, arg = AFMT_ENCODING(format);
1002
1003 /*
1004 * The data format uses 3 bits (just 2 on the 1848). For each
1005 * bit setting, the following array returns the corresponding format.
1006 * The code scans the array looking for a suitable format. In
1007 * case it is not found, default to AFMT_U8 (not such a good
1008 * choice, but let's do it for compatibility...).
1009 */
1010
1011 static int fmts[] =
1012 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1013 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1014
1015 ch->fmt = format;
1016 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1017 arg = i << 1;
1018 if (AFMT_CHANNEL(format) > 1) arg |= 1;
1019 arg <<= 4;
1020 ad_enter_MCE(mss);
1021 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1022 ad_wait_init(mss, 10000);
1023 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1024 ad_write(mss, 28, arg); /* capture mode */
1025 ad_wait_init(mss, 10000);
1026 }
1027 ad_leave_MCE(mss);
1028 return format;
1029 }
1030
1031 static int
mss_trigger(struct mss_chinfo * ch,int go)1032 mss_trigger(struct mss_chinfo *ch, int go)
1033 {
1034 struct mss_info *mss = ch->parent;
1035 u_char m;
1036 int retry, wr, cnt, ss;
1037
1038 ss = 1;
1039 ss <<= (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
1040 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1041
1042 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1043 m = ad_read(mss, 9);
1044 switch (go) {
1045 case PCMTRIG_START:
1046 cnt = (ch->blksz / ss) - 1;
1047
1048 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1049 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1050 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1051 break;
1052
1053 case PCMTRIG_STOP:
1054 case PCMTRIG_ABORT: /* XXX check this... */
1055 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1056 #if 0
1057 /*
1058 * try to disable DMA by clearing count registers. Not sure it
1059 * is needed, and it might cause false interrupts when the
1060 * DMA is re-enabled later.
1061 */
1062 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1063 #endif
1064 }
1065 /* on the OPTi931 the enable bit seems hard to set... */
1066 for (retry = 10; retry > 0; retry--) {
1067 ad_write(mss, 9, m);
1068 if (ad_read(mss, 9) == m) break;
1069 }
1070 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
1071 m, ad_read(mss, 9)));
1072 return 0;
1073 }
1074
1075 /*
1076 * the opti931 seems to miss interrupts when working in full
1077 * duplex, so we try some heuristics to catch them.
1078 */
1079 static void
opti931_intr(void * arg)1080 opti931_intr(void *arg)
1081 {
1082 struct mss_info *mss = (struct mss_info *)arg;
1083 u_char masked = 0, i11, mc11, c = 0;
1084 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1085 int loops = 10;
1086
1087 #if 0
1088 reason = io_rd(mss, MSS_STATUS);
1089 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1090 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1091 return;
1092 }
1093 #endif
1094 mss_lock(mss);
1095 i11 = ad_read(mss, 11); /* XXX what's for ? */
1096 again:
1097
1098 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1099 mc11 &= 0x0c;
1100 if (c & 0x10) {
1101 DEB(printf("Warning: CD interrupt\n");)
1102 mc11 |= 0x10;
1103 }
1104 if (c & 0x20) {
1105 DEB(printf("Warning: MPU interrupt\n");)
1106 mc11 |= 0x20;
1107 }
1108 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
1109 mc11, masked));
1110 masked |= mc11;
1111 /*
1112 * the nice OPTi931 sets the IRQ line before setting the bits in
1113 * mc11. So, on some occasions I have to retry (max 10 times).
1114 */
1115 if (mc11 == 0) { /* perhaps can return ... */
1116 reason = io_rd(mss, MSS_STATUS);
1117 if (reason & 1) {
1118 DEB(printf("one more try...\n");)
1119 if (--loops) goto again;
1120 else BVDDB(printf("intr, but mc11 not set\n");)
1121 }
1122 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
1123 mss_unlock(mss);
1124 return;
1125 }
1126
1127 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1128 mss_unlock(mss);
1129 chn_intr(mss->rch.channel);
1130 mss_lock(mss);
1131 }
1132 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1133 mss_unlock(mss);
1134 chn_intr(mss->pch.channel);
1135 mss_lock(mss);
1136 }
1137 opti_wr(mss, 11, ~mc11); /* ack */
1138 if (--loops) goto again;
1139 mss_unlock(mss);
1140 DEB(printf("xxx too many loops\n");)
1141 }
1142
1143 /* -------------------------------------------------------------------- */
1144 /* channel interface */
1145 static void *
msschan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)1146 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1147 {
1148 struct mss_info *mss = devinfo;
1149 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1150
1151 ch->parent = mss;
1152 ch->channel = c;
1153 ch->buffer = b;
1154 ch->dir = dir;
1155 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, 0, mss->bufsize) != 0)
1156 return NULL;
1157 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1158 return ch;
1159 }
1160
1161 static int
msschan_setformat(kobj_t obj,void * data,u_int32_t format)1162 msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1163 {
1164 struct mss_chinfo *ch = data;
1165 struct mss_info *mss = ch->parent;
1166
1167 mss_lock(mss);
1168 mss_format(ch, format);
1169 mss_unlock(mss);
1170 return 0;
1171 }
1172
1173 static u_int32_t
msschan_setspeed(kobj_t obj,void * data,u_int32_t speed)1174 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1175 {
1176 struct mss_chinfo *ch = data;
1177 struct mss_info *mss = ch->parent;
1178 u_int32_t r;
1179
1180 mss_lock(mss);
1181 r = mss_speed(ch, speed);
1182 mss_unlock(mss);
1183
1184 return r;
1185 }
1186
1187 static u_int32_t
msschan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)1188 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1189 {
1190 struct mss_chinfo *ch = data;
1191
1192 ch->blksz = blocksize;
1193 sndbuf_resize(ch->buffer, 2, ch->blksz);
1194
1195 return ch->blksz;
1196 }
1197
1198 static int
msschan_trigger(kobj_t obj,void * data,int go)1199 msschan_trigger(kobj_t obj, void *data, int go)
1200 {
1201 struct mss_chinfo *ch = data;
1202 struct mss_info *mss = ch->parent;
1203
1204 if (!PCMTRIG_COMMON(go))
1205 return 0;
1206
1207 sndbuf_dma(ch->buffer, go);
1208 mss_lock(mss);
1209 mss_trigger(ch, go);
1210 mss_unlock(mss);
1211 return 0;
1212 }
1213
1214 static u_int32_t
msschan_getptr(kobj_t obj,void * data)1215 msschan_getptr(kobj_t obj, void *data)
1216 {
1217 struct mss_chinfo *ch = data;
1218 return sndbuf_dmaptr(ch->buffer);
1219 }
1220
1221 static struct pcmchan_caps *
msschan_getcaps(kobj_t obj,void * data)1222 msschan_getcaps(kobj_t obj, void *data)
1223 {
1224 struct mss_chinfo *ch = data;
1225
1226 switch(ch->parent->bd_id) {
1227 case MD_OPTI931:
1228 return &opti931_caps;
1229 break;
1230
1231 case MD_GUSPNP:
1232 case MD_GUSMAX:
1233 return &guspnp_caps;
1234 break;
1235
1236 default:
1237 return &mss_caps;
1238 break;
1239 }
1240 }
1241
1242 static kobj_method_t msschan_methods[] = {
1243 KOBJMETHOD(channel_init, msschan_init),
1244 KOBJMETHOD(channel_setformat, msschan_setformat),
1245 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1246 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1247 KOBJMETHOD(channel_trigger, msschan_trigger),
1248 KOBJMETHOD(channel_getptr, msschan_getptr),
1249 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1250 KOBJMETHOD_END
1251 };
1252 CHANNEL_DECLARE(msschan);
1253
1254 /* -------------------------------------------------------------------- */
1255
1256 /*
1257 * mss_probe() is the probe routine. Note, it is not necessary to
1258 * go through this for PnP devices, since they are already
1259 * indentified precisely using their PnP id.
1260 *
1261 * The base address supplied in the device refers to the old MSS
1262 * specs where the four 4 registers in io space contain configuration
1263 * information. Some boards (as an example, early MSS boards)
1264 * has such a block of registers, whereas others (generally CS42xx)
1265 * do not. In order to distinguish between the two and do not have
1266 * to supply two separate probe routines, the flags entry in isa_device
1267 * has a bit to mark this.
1268 *
1269 */
1270
1271 static int
mss_probe(device_t dev)1272 mss_probe(device_t dev)
1273 {
1274 u_char tmp, tmpx;
1275 int flags, irq, drq, result = ENXIO, setres = 0;
1276 struct mss_info *mss;
1277
1278 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1279
1280 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1281 if (!mss) return ENXIO;
1282
1283 mss->io_rid = 0;
1284 mss->conf_rid = -1;
1285 mss->irq_rid = 0;
1286 mss->drq1_rid = 0;
1287 mss->drq2_rid = -1;
1288 mss->io_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1289 &mss->io_rid, 8, RF_ACTIVE);
1290 if (!mss->io_base) {
1291 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
1292 mss->io_rid = 0;
1293 /* XXX verify this */
1294 setres = 1;
1295 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1296 0x530, 8);
1297 mss->io_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1298 &mss->io_rid,
1299 8, RF_ACTIVE);
1300 }
1301 if (!mss->io_base) goto no;
1302
1303 /* got irq/dma regs? */
1304 flags = device_get_flags(dev);
1305 irq = isa_get_irq(dev);
1306 drq = isa_get_drq(dev);
1307
1308 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1309
1310 /*
1311 * Check if the IO port returns valid signature. The original MS
1312 * Sound system returns 0x04 while some cards
1313 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1314 */
1315
1316 device_set_desc(dev, "MSS");
1317 tmpx = tmp = io_rd(mss, 3);
1318 if (tmp == 0xff) { /* Bus float */
1319 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
1320 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1321 goto mss_probe_end;
1322 }
1323 tmp &= 0x3f;
1324 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00 || tmp == 0x05)) {
1325 BVDDB(printf("No MSS signature detected on port 0x%jx (0x%x)\n",
1326 rman_get_start(mss->io_base), tmpx));
1327 goto no;
1328 }
1329 if (irq > 11) {
1330 printf("MSS: Bad IRQ %d\n", irq);
1331 goto no;
1332 }
1333 if (!(drq == 0 || drq == 1 || drq == 3)) {
1334 printf("MSS: Bad DMA %d\n", drq);
1335 goto no;
1336 }
1337 if (tmpx & 0x80) {
1338 /* 8-bit board: only drq1/3 and irq7/9 */
1339 if (drq == 0) {
1340 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1341 goto no;
1342 }
1343 if (!(irq == 7 || irq == 9)) {
1344 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
1345 irq);
1346 goto no;
1347 }
1348 }
1349 mss_probe_end:
1350 result = mss_detect(dev, mss);
1351 no:
1352 mss_release_resources(mss, dev);
1353 #if 0
1354 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1355 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1356 #endif
1357 return result;
1358 }
1359
1360 static int
mss_detect(device_t dev,struct mss_info * mss)1361 mss_detect(device_t dev, struct mss_info *mss)
1362 {
1363 int i;
1364 u_char tmp = 0, tmp1, tmp2;
1365 char *name, *yamaha;
1366
1367 if (mss->bd_id != 0) {
1368 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1369 device_get_desc(dev));
1370 return 0;
1371 }
1372
1373 name = "AD1848";
1374 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1375
1376 if (opti_detect(dev, mss)) {
1377 switch (mss->bd_id) {
1378 case MD_OPTI924:
1379 name = "OPTi924";
1380 break;
1381 case MD_OPTI930:
1382 name = "OPTi930";
1383 break;
1384 }
1385 printf("Found OPTi device %s\n", name);
1386 if (opti_init(dev, mss) == 0) goto gotit;
1387 }
1388
1389 /*
1390 * Check that the I/O address is in use.
1391 *
1392 * bit 7 of the base I/O port is known to be 0 after the chip has
1393 * performed its power on initialization. Just assume this has
1394 * happened before the OS is starting.
1395 *
1396 * If the I/O address is unused, it typically returns 0xff.
1397 */
1398
1399 for (i = 0; i < 10; i++)
1400 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1401 else break;
1402
1403 if (i >= 10) { /* Not an AD1848 */
1404 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
1405 goto no;
1406 }
1407 /*
1408 * Test if it's possible to change contents of the indirect
1409 * registers. Registers 0 and 1 are ADC volume registers. The bit
1410 * 0x10 is read only so try to avoid using it.
1411 */
1412
1413 ad_write(mss, 0, 0xaa);
1414 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1415 tmp1 = ad_read(mss, 0);
1416 tmp2 = ad_read(mss, 1);
1417 if (tmp1 != 0xaa || tmp2 != 0x45) {
1418 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
1419 goto no;
1420 }
1421
1422 ad_write(mss, 0, 0x45);
1423 ad_write(mss, 1, 0xaa);
1424 tmp1 = ad_read(mss, 0);
1425 tmp2 = ad_read(mss, 1);
1426 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1427 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
1428 goto no;
1429 }
1430
1431 /*
1432 * The indirect register I12 has some read only bits. Lets try to
1433 * change them.
1434 */
1435
1436 tmp = ad_read(mss, 12);
1437 ad_write(mss, 12, (~tmp) & 0x0f);
1438 tmp1 = ad_read(mss, 12);
1439
1440 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1441 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
1442 goto no;
1443 }
1444
1445 /*
1446 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1447 * 0x01=RevB
1448 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1449 */
1450
1451 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
1452
1453 /*
1454 * The original AD1848/CS4248 has just 16 indirect registers. This
1455 * means that I0 and I16 should return the same value (etc.). Ensure
1456 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1457 * with new parts.
1458 */
1459
1460 ad_write(mss, 12, 0); /* Mode2=disabled */
1461 #if 0
1462 for (i = 0; i < 16; i++) {
1463 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1464 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
1465 i, tmp1, tmp2));
1466 /*
1467 * note - this seems to fail on the 4232 on I11. So we just break
1468 * rather than fail. (which makes this test pointless - cg)
1469 */
1470 break; /* return 0; */
1471 }
1472 }
1473 #endif
1474 /*
1475 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1476 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1477 *
1478 * On the OPTi931, however, I12 is readonly and only contains the
1479 * chip revision ID (as in the CS4231A). The upper bits return 0.
1480 */
1481
1482 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1483
1484 tmp1 = ad_read(mss, 12);
1485 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1486 if ((tmp1 & 0xf0) == 0x00) {
1487 BVDDB(printf("this should be an OPTi931\n");)
1488 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1489 /*
1490 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1491 * We want to check that this is really a CS4231
1492 * Verify that setting I0 doesn't change I16.
1493 */
1494 ad_write(mss, 16, 0); /* Set I16 to known value */
1495 ad_write(mss, 0, 0x45);
1496 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1497
1498 ad_write(mss, 0, 0xaa);
1499 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1500 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
1501 goto no;
1502 }
1503 /* Verify that some bits of I25 are read only. */
1504 tmp1 = ad_read(mss, 25); /* Original bits */
1505 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1506 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1507 int id;
1508
1509 /* It's at least CS4231 */
1510 name = "CS4231";
1511 mss->bd_id = MD_CS42XX;
1512
1513 /*
1514 * It could be an AD1845 or CS4231A as well.
1515 * CS4231 and AD1845 report the same revision info in I25
1516 * while the CS4231A reports different.
1517 */
1518
1519 id = ad_read(mss, 25) & 0xe7;
1520 /*
1521 * b7-b5 = version number;
1522 * 100 : all CS4231
1523 * 101 : CS4231A
1524 *
1525 * b2-b0 = chip id;
1526 */
1527 switch (id) {
1528 case 0xa0:
1529 name = "CS4231A";
1530 mss->bd_id = MD_CS42XX;
1531 break;
1532
1533 case 0xa2:
1534 name = "CS4232";
1535 mss->bd_id = MD_CS42XX;
1536 break;
1537
1538 case 0xb2:
1539 /* strange: the 4231 data sheet says b4-b3 are XX
1540 * so this should be the same as 0xa2
1541 */
1542 name = "CS4232A";
1543 mss->bd_id = MD_CS42XX;
1544 break;
1545
1546 case 0x80:
1547 /*
1548 * It must be a CS4231 or AD1845. The register I23
1549 * of CS4231 is undefined and it appears to be read
1550 * only. AD1845 uses I23 for setting sample rate.
1551 * Assume the chip is AD1845 if I23 is changeable.
1552 */
1553
1554 tmp = ad_read(mss, 23);
1555
1556 ad_write(mss, 23, ~tmp);
1557 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1558 name = "AD1845";
1559 mss->bd_id = MD_AD1845;
1560 }
1561 ad_write(mss, 23, tmp); /* Restore */
1562
1563 yamaha = ymf_test(dev, mss);
1564 if (yamaha) {
1565 mss->bd_id = MD_YM0020;
1566 name = yamaha;
1567 }
1568 break;
1569
1570 case 0x83: /* CS4236 */
1571 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1572 name = "CS4236";
1573 mss->bd_id = MD_CS42XX;
1574 break;
1575
1576 default: /* Assume CS4231 */
1577 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
1578 mss->bd_id = MD_CS42XX;
1579 }
1580 }
1581 ad_write(mss, 25, tmp1); /* Restore bits */
1582 gotit:
1583 BVDDB(printf("mss_detect() - Detected %s\n", name));
1584 device_set_desc(dev, name);
1585 device_set_flags(dev,
1586 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1587 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1588 return 0;
1589 no:
1590 return ENXIO;
1591 }
1592
1593 static int
opti_detect(device_t dev,struct mss_info * mss)1594 opti_detect(device_t dev, struct mss_info *mss)
1595 {
1596 int c;
1597 static const struct opticard {
1598 int boardid;
1599 int passwdreg;
1600 int password;
1601 int base;
1602 int indir_reg;
1603 } cards[] = {
1604 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1605 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1606 { 0 },
1607 };
1608 mss->conf_rid = 3;
1609 mss->indir_rid = 4;
1610 for (c = 0; cards[c].base; c++) {
1611 mss->optibase = cards[c].base;
1612 mss->password = cards[c].password;
1613 mss->passwdreg = cards[c].passwdreg;
1614 mss->bd_id = cards[c].boardid;
1615
1616 if (cards[c].indir_reg)
1617 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1618 &mss->indir_rid, cards[c].indir_reg,
1619 cards[c].indir_reg+1, 1, RF_ACTIVE);
1620
1621 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1622 &mss->conf_rid, mss->optibase, mss->optibase+9,
1623 9, RF_ACTIVE);
1624
1625 if (opti_read(mss, 1) != 0xff) {
1626 return 1;
1627 } else {
1628 if (mss->indir)
1629 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1630 mss->indir = NULL;
1631 if (mss->conf_base)
1632 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1633 mss->conf_base = NULL;
1634 }
1635 }
1636 return 0;
1637 }
1638
1639 static char *
ymf_test(device_t dev,struct mss_info * mss)1640 ymf_test(device_t dev, struct mss_info *mss)
1641 {
1642 static int ports[] = {0x370, 0x310, 0x538};
1643 int p, i, j, version;
1644 static char *chipset[] = {
1645 NULL, /* 0 */
1646 "OPL3-SA2 (YMF711)", /* 1 */
1647 "OPL3-SA3 (YMF715)", /* 2 */
1648 "OPL3-SA3 (YMF715)", /* 3 */
1649 "OPL3-SAx (YMF719)", /* 4 */
1650 "OPL3-SAx (YMF719)", /* 5 */
1651 "OPL3-SAx (YMF719)", /* 6 */
1652 "OPL3-SAx (YMF719)", /* 7 */
1653 };
1654
1655 for (p = 0; p < 3; p++) {
1656 mss->conf_rid = 1;
1657 mss->conf_base = bus_alloc_resource(dev,
1658 SYS_RES_IOPORT,
1659 &mss->conf_rid,
1660 ports[p], ports[p] + 1, 2,
1661 RF_ACTIVE);
1662 if (!mss->conf_base) return 0;
1663
1664 /* Test the index port of the config registers */
1665 i = port_rd(mss->conf_base, 0);
1666 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1667 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1668 port_wr(mss->conf_base, 0, i);
1669 if (!j) {
1670 bus_release_resource(dev, SYS_RES_IOPORT,
1671 mss->conf_rid, mss->conf_base);
1672 mss->conf_base = NULL;
1673 continue;
1674 }
1675 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1676 return chipset[version];
1677 }
1678 return NULL;
1679 }
1680
1681 static int
mss_doattach(device_t dev,struct mss_info * mss)1682 mss_doattach(device_t dev, struct mss_info *mss)
1683 {
1684 int pdma, rdma, flags = device_get_flags(dev);
1685 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1686
1687 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_mss softc");
1688 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1689 if (!mss_alloc_resources(mss, dev)) goto no;
1690 mss_init(mss, dev);
1691 pdma = rman_get_start(mss->drq1);
1692 rdma = rman_get_start(mss->drq2);
1693 if (flags & DV_F_TRUE_MSS) {
1694 /* has IRQ/DMA registers, set IRQ and DMA addr */
1695 static char interrupt_bits[12] =
1696 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
1697 static char pdma_bits[4] = {1, 2, -1, 3};
1698 static char valid_rdma[4] = {1, 0, -1, 0};
1699 char bits;
1700
1701 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1702 goto no;
1703 io_wr(mss, 0, bits | 0x40); /* config port */
1704 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
1705 /* Write IRQ+DMA setup */
1706 if (pdma_bits[pdma] == -1) goto no;
1707 bits |= pdma_bits[pdma];
1708 if (pdma != rdma) {
1709 if (rdma == valid_rdma[pdma]) bits |= 4;
1710 else {
1711 printf("invalid dual dma config %d:%d\n", pdma, rdma);
1712 goto no;
1713 }
1714 }
1715 io_wr(mss, 0, bits);
1716 printf("drq/irq conf %x\n", io_rd(mss, 0));
1717 }
1718 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1719 switch (mss->bd_id) {
1720 case MD_OPTI931:
1721 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
1722 break;
1723 default:
1724 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
1725 }
1726 if (pdma == rdma)
1727 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1728 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
1729 /*boundary*/0,
1730 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1731 /*highaddr*/BUS_SPACE_MAXADDR,
1732 /*filter*/NULL, /*filterarg*/NULL,
1733 /*maxsize*/mss->bufsize, /*nsegments*/1,
1734 /*maxsegz*/0x3ffff, /*flags*/0,
1735 /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant,
1736 &mss->parent_dmat) != 0) {
1737 device_printf(dev, "unable to create dma tag\n");
1738 goto no;
1739 }
1740
1741 if (pdma != rdma)
1742 snprintf(status2, SND_STATUSLEN, ":%d", rdma);
1743 else
1744 status2[0] = '\0';
1745
1746 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd drq %d%s bufsz %u",
1747 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1748
1749 if (pcm_register(dev, mss, 1, 1)) goto no;
1750 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1751 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1752 pcm_setstatus(dev, status);
1753
1754 return 0;
1755 no:
1756 mss_release_resources(mss, dev);
1757 return ENXIO;
1758 }
1759
1760 static int
mss_detach(device_t dev)1761 mss_detach(device_t dev)
1762 {
1763 int r;
1764 struct mss_info *mss;
1765
1766 r = pcm_unregister(dev);
1767 if (r)
1768 return r;
1769
1770 mss = pcm_getdevinfo(dev);
1771 mss_release_resources(mss, dev);
1772
1773 return 0;
1774 }
1775
1776 static int
mss_attach(device_t dev)1777 mss_attach(device_t dev)
1778 {
1779 struct mss_info *mss;
1780 int flags = device_get_flags(dev);
1781
1782 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1783 if (!mss) return ENXIO;
1784
1785 mss->io_rid = 0;
1786 mss->conf_rid = -1;
1787 mss->irq_rid = 0;
1788 mss->drq1_rid = 0;
1789 mss->drq2_rid = -1;
1790 if (flags & DV_F_DUAL_DMA) {
1791 bus_set_resource(dev, SYS_RES_DRQ, 1,
1792 flags & DV_F_DRQ_MASK, 1);
1793 mss->drq2_rid = 1;
1794 }
1795 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1796 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1797 return mss_doattach(dev, mss);
1798 }
1799
1800 /*
1801 * mss_resume() is the code to allow a laptop to resume using the sound
1802 * card.
1803 *
1804 * This routine re-sets the state of the board to the state before going
1805 * to sleep. According to the yamaha docs this is the right thing to do,
1806 * but getting DMA restarted appears to be a bit of a trick, so the device
1807 * has to be closed and re-opened to be re-used, but there is no skipping
1808 * problem, and volume, bass/treble and most other things are restored
1809 * properly.
1810 *
1811 */
1812
1813 static int
mss_resume(device_t dev)1814 mss_resume(device_t dev)
1815 {
1816 /*
1817 * Restore the state taken below.
1818 */
1819 struct mss_info *mss;
1820 int i;
1821
1822 mss = pcm_getdevinfo(dev);
1823
1824 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
1825 /* This works on a Toshiba Libretto 100CT. */
1826 for (i = 0; i < MSS_INDEXED_REGS; i++)
1827 ad_write(mss, i, mss->mss_indexed_regs[i]);
1828 for (i = 0; i < OPL_INDEXED_REGS; i++)
1829 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1830 mss_intr(mss);
1831 }
1832
1833 if (mss->bd_id == MD_CS423X) {
1834 /* Needed on IBM Thinkpad 600E */
1835 mss_lock(mss);
1836 mss_format(&mss->pch, mss->pch.channel->format);
1837 mss_speed(&mss->pch, mss->pch.channel->speed);
1838 mss_unlock(mss);
1839 }
1840
1841 return 0;
1842
1843 }
1844
1845 /*
1846 * mss_suspend() is the code that gets called right before a laptop
1847 * suspends.
1848 *
1849 * This code saves the state of the sound card right before shutdown
1850 * so it can be restored above.
1851 *
1852 */
1853
1854 static int
mss_suspend(device_t dev)1855 mss_suspend(device_t dev)
1856 {
1857 int i;
1858 struct mss_info *mss;
1859
1860 mss = pcm_getdevinfo(dev);
1861
1862 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
1863 {
1864 /* this stops playback. */
1865 conf_wr(mss, 0x12, 0x0c);
1866 for(i = 0; i < MSS_INDEXED_REGS; i++)
1867 mss->mss_indexed_regs[i] = ad_read(mss, i);
1868 for(i = 0; i < OPL_INDEXED_REGS; i++)
1869 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1870 mss->opl_indexed_regs[0x12] = 0x0;
1871 }
1872 return 0;
1873 }
1874
1875 static device_method_t mss_methods[] = {
1876 /* Device interface */
1877 DEVMETHOD(device_probe, mss_probe),
1878 DEVMETHOD(device_attach, mss_attach),
1879 DEVMETHOD(device_detach, mss_detach),
1880 DEVMETHOD(device_suspend, mss_suspend),
1881 DEVMETHOD(device_resume, mss_resume),
1882 { 0, 0 }
1883 };
1884
1885 static driver_t mss_driver = {
1886 "pcm",
1887 mss_methods,
1888 PCM_SOFTC_SIZE,
1889 };
1890
1891 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
1892 MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1893 MODULE_VERSION(snd_mss, 1);
1894
1895 static int
azt2320_mss_mode(struct mss_info * mss,device_t dev)1896 azt2320_mss_mode(struct mss_info *mss, device_t dev)
1897 {
1898 struct resource *sbport;
1899 int i, ret, rid;
1900
1901 rid = 0;
1902 ret = -1;
1903 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1904 if (sbport) {
1905 for (i = 0; i < 1000; i++) {
1906 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1907 DELAY((i > 100) ? 1000 : 10);
1908 else {
1909 port_wr(sbport, SBDSP_CMD, 0x09);
1910 break;
1911 }
1912 }
1913 for (i = 0; i < 1000; i++) {
1914 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1915 DELAY((i > 100) ? 1000 : 10);
1916 else {
1917 port_wr(sbport, SBDSP_CMD, 0x00);
1918 ret = 0;
1919 break;
1920 }
1921 }
1922 DELAY(1000);
1923 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1924 }
1925 return ret;
1926 }
1927
1928 static struct isa_pnp_id pnpmss_ids[] = {
1929 {0x0000630e, "CS423x"}, /* CSC0000 */
1930 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1931 {0x01000000, "CMI8330"}, /* @@@0001 */
1932 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1933 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1934 {0x1093143e, "OPTi931"}, /* OPT9310 */
1935 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1936 {0x0000143e, "OPTi924"}, /* OPT0924 */
1937 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1938 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1939 #if 0
1940 {0x0000561e, "GusPnP"}, /* GRV0000 */
1941 #endif
1942 {0},
1943 };
1944
1945 static int
pnpmss_probe(device_t dev)1946 pnpmss_probe(device_t dev)
1947 {
1948 u_int32_t lid, vid;
1949
1950 lid = isa_get_logicalid(dev);
1951 vid = isa_get_vendorid(dev);
1952 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1953 return ENXIO;
1954 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1955 }
1956
1957 static int
pnpmss_attach(device_t dev)1958 pnpmss_attach(device_t dev)
1959 {
1960 struct mss_info *mss;
1961
1962 mss = malloc(sizeof(*mss), M_DEVBUF, M_WAITOK | M_ZERO);
1963 mss->io_rid = 0;
1964 mss->conf_rid = -1;
1965 mss->irq_rid = 0;
1966 mss->drq1_rid = 0;
1967 mss->drq2_rid = 1;
1968 mss->bd_id = MD_CS42XX;
1969
1970 switch (isa_get_logicalid(dev)) {
1971 case 0x0000630e: /* CSC0000 */
1972 case 0x0001630e: /* CSC0100 */
1973 mss->bd_flags |= BD_F_MSS_OFFSET;
1974 mss->bd_id = MD_CS423X;
1975 break;
1976
1977 case 0x2100a865: /* YHM0021 */
1978 mss->io_rid = 1;
1979 mss->conf_rid = 4;
1980 mss->bd_id = MD_YM0020;
1981 break;
1982
1983 case 0x1110d315: /* ENS1011 */
1984 mss->io_rid = 1;
1985 mss->bd_id = MD_VIVO;
1986 break;
1987
1988 case 0x1093143e: /* OPT9310 */
1989 mss->bd_flags |= BD_F_MSS_OFFSET;
1990 mss->conf_rid = 3;
1991 mss->bd_id = MD_OPTI931;
1992 break;
1993
1994 case 0x5092143e: /* OPT9250 XXX guess */
1995 mss->io_rid = 1;
1996 mss->conf_rid = 3;
1997 mss->bd_id = MD_OPTI925;
1998 break;
1999
2000 case 0x0000143e: /* OPT0924 */
2001 mss->password = 0xe5;
2002 mss->passwdreg = 3;
2003 mss->optibase = 0xf0c;
2004 mss->io_rid = 2;
2005 mss->conf_rid = 3;
2006 mss->bd_id = MD_OPTI924;
2007 mss->bd_flags |= BD_F_924PNP;
2008 if(opti_init(dev, mss) != 0) {
2009 free(mss, M_DEVBUF);
2010 return ENXIO;
2011 }
2012 break;
2013
2014 case 0x1022b839: /* NMX2210 */
2015 mss->io_rid = 1;
2016 break;
2017
2018 case 0x01005407: /* AZT0001 */
2019 /* put into MSS mode first (snatched from NetBSD) */
2020 if (azt2320_mss_mode(mss, dev) == -1) {
2021 free(mss, M_DEVBUF);
2022 return ENXIO;
2023 }
2024
2025 mss->bd_flags |= BD_F_MSS_OFFSET;
2026 mss->io_rid = 2;
2027 break;
2028
2029 #if 0
2030 case 0x0000561e: /* GRV0000 */
2031 mss->bd_flags |= BD_F_MSS_OFFSET;
2032 mss->io_rid = 2;
2033 mss->conf_rid = 1;
2034 mss->drq1_rid = 1;
2035 mss->drq2_rid = 0;
2036 mss->bd_id = MD_GUSPNP;
2037 break;
2038 #endif
2039 case 0x01000000: /* @@@0001 */
2040 mss->drq2_rid = -1;
2041 break;
2042
2043 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2044 default:
2045 mss->bd_flags |= BD_F_MSS_OFFSET;
2046 break;
2047 }
2048 return mss_doattach(dev, mss);
2049 }
2050
2051 static int
opti_init(device_t dev,struct mss_info * mss)2052 opti_init(device_t dev, struct mss_info *mss)
2053 {
2054 int flags = device_get_flags(dev);
2055 int basebits = 0;
2056
2057 if (!mss->conf_base) {
2058 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2059 mss->optibase, 0x9);
2060
2061 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2062 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2063 0x9, RF_ACTIVE);
2064 }
2065
2066 if (!mss->conf_base)
2067 return ENXIO;
2068
2069 if (!mss->io_base)
2070 mss->io_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
2071 &mss->io_rid, 8, RF_ACTIVE);
2072
2073 if (!mss->io_base) /* No hint specified, use 0x530 */
2074 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2075 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2076
2077 if (!mss->io_base)
2078 return ENXIO;
2079
2080 switch (rman_get_start(mss->io_base)) {
2081 case 0x530:
2082 basebits = 0x0;
2083 break;
2084 case 0xe80:
2085 basebits = 0x10;
2086 break;
2087 case 0xf40:
2088 basebits = 0x20;
2089 break;
2090 case 0x604:
2091 basebits = 0x30;
2092 break;
2093 default:
2094 printf("opti_init: invalid MSS base address!\n");
2095 return ENXIO;
2096 }
2097
2098 switch (mss->bd_id) {
2099 case MD_OPTI924:
2100 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2101 opti_write(mss, 2, 0x00); /* Disable CD */
2102 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2103 opti_write(mss, 4, 0xf0);
2104 opti_write(mss, 5, 0x00);
2105 opti_write(mss, 6, 0x02); /* MPU stuff */
2106 break;
2107
2108 case MD_OPTI930:
2109 opti_write(mss, 1, 0x00 | basebits);
2110 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2111 opti_write(mss, 4, 0x52); /* Empty FIFO */
2112 opti_write(mss, 5, 0x3c); /* Mode 2 */
2113 opti_write(mss, 6, 0x02); /* Enable MSS */
2114 break;
2115 }
2116
2117 if (mss->bd_flags & BD_F_924PNP) {
2118 u_int32_t irq = isa_get_irq(dev);
2119 u_int32_t drq = isa_get_drq(dev);
2120 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2121 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2122 if (flags & DV_F_DUAL_DMA) {
2123 bus_set_resource(dev, SYS_RES_DRQ, 1,
2124 flags & DV_F_DRQ_MASK, 1);
2125 mss->drq2_rid = 1;
2126 }
2127 }
2128
2129 /* OPTixxx has I/DRQ registers */
2130
2131 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2132
2133 return 0;
2134 }
2135
2136 static void
opti_write(struct mss_info * mss,u_char reg,u_char val)2137 opti_write(struct mss_info *mss, u_char reg, u_char val)
2138 {
2139 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2140
2141 switch(mss->bd_id) {
2142 case MD_OPTI924:
2143 if (reg > 7) { /* Indirect register */
2144 port_wr(mss->conf_base, mss->passwdreg, reg);
2145 port_wr(mss->conf_base, mss->passwdreg,
2146 mss->password);
2147 port_wr(mss->conf_base, 9, val);
2148 return;
2149 }
2150 port_wr(mss->conf_base, reg, val);
2151 break;
2152
2153 case MD_OPTI930:
2154 port_wr(mss->indir, 0, reg);
2155 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2156 port_wr(mss->indir, 1, val);
2157 break;
2158 }
2159 }
2160
2161 u_char
opti_read(struct mss_info * mss,u_char reg)2162 opti_read(struct mss_info *mss, u_char reg)
2163 {
2164 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2165
2166 switch(mss->bd_id) {
2167 case MD_OPTI924:
2168 if (reg > 7) { /* Indirect register */
2169 port_wr(mss->conf_base, mss->passwdreg, reg);
2170 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2171 return(port_rd(mss->conf_base, 9));
2172 }
2173 return(port_rd(mss->conf_base, reg));
2174 break;
2175
2176 case MD_OPTI930:
2177 port_wr(mss->indir, 0, reg);
2178 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2179 return port_rd(mss->indir, 1);
2180 break;
2181 }
2182 return -1;
2183 }
2184
2185 static device_method_t pnpmss_methods[] = {
2186 /* Device interface */
2187 DEVMETHOD(device_probe, pnpmss_probe),
2188 DEVMETHOD(device_attach, pnpmss_attach),
2189 DEVMETHOD(device_detach, mss_detach),
2190 DEVMETHOD(device_suspend, mss_suspend),
2191 DEVMETHOD(device_resume, mss_resume),
2192 { 0, 0 }
2193 };
2194
2195 static driver_t pnpmss_driver = {
2196 "pcm",
2197 pnpmss_methods,
2198 PCM_SOFTC_SIZE,
2199 };
2200
2201 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
2202 DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
2203 MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2204 MODULE_VERSION(snd_pnpmss, 1);
2205
2206 static int
guspcm_probe(device_t dev)2207 guspcm_probe(device_t dev)
2208 {
2209 struct sndcard_func *func;
2210
2211 func = device_get_ivars(dev);
2212 if (func == NULL || func->func != SCF_PCM)
2213 return ENXIO;
2214
2215 device_set_desc(dev, "GUS CS4231");
2216 return 0;
2217 }
2218
2219 static int
guspcm_attach(device_t dev)2220 guspcm_attach(device_t dev)
2221 {
2222 device_t parent = device_get_parent(dev);
2223 struct mss_info *mss;
2224 int base, flags;
2225 unsigned char ctl;
2226
2227 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
2228 if (mss == NULL)
2229 return ENOMEM;
2230
2231 mss->bd_flags = BD_F_MSS_OFFSET;
2232 mss->io_rid = 2;
2233 mss->conf_rid = 1;
2234 mss->irq_rid = 0;
2235 mss->drq1_rid = 1;
2236 mss->drq2_rid = -1;
2237
2238 if (isa_get_logicalid(parent) == 0)
2239 mss->bd_id = MD_GUSMAX;
2240 else {
2241 mss->bd_id = MD_GUSPNP;
2242 mss->drq2_rid = 0;
2243 goto skip_setup;
2244 }
2245
2246 flags = device_get_flags(parent);
2247 if (flags & DV_F_DUAL_DMA)
2248 mss->drq2_rid = 0;
2249
2250 mss->conf_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
2251 &mss->conf_rid,
2252 8, RF_ACTIVE);
2253
2254 if (mss->conf_base == NULL) {
2255 mss_release_resources(mss, dev);
2256 return ENXIO;
2257 }
2258
2259 base = isa_get_port(parent);
2260
2261 ctl = 0x40; /* CS4231 enable */
2262 if (isa_get_drq(dev) > 3)
2263 ctl |= 0x10; /* 16-bit dma channel 1 */
2264 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2265 ctl |= 0x20; /* 16-bit dma channel 2 */
2266 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2267 port_wr(mss->conf_base, 6, ctl);
2268
2269 skip_setup:
2270 return mss_doattach(dev, mss);
2271 }
2272
2273 static device_method_t guspcm_methods[] = {
2274 DEVMETHOD(device_probe, guspcm_probe),
2275 DEVMETHOD(device_attach, guspcm_attach),
2276 DEVMETHOD(device_detach, mss_detach),
2277 { 0, 0 }
2278 };
2279
2280 static driver_t guspcm_driver = {
2281 "pcm",
2282 guspcm_methods,
2283 PCM_SOFTC_SIZE,
2284 };
2285
2286 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
2287 MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2288 MODULE_VERSION(snd_guspcm, 1);
2289 ISA_PNP_INFO(pnpmss_ids);
2290