1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/rman.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <machine/bus.h>
36
37 #include <dev/fdt/simplebus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #ifdef __aarch64__
43 #include "opt_soc.h"
44 #endif
45
46 #include <dev/extres/clk/clk_div.h>
47 #include <dev/extres/clk/clk_fixed.h>
48 #include <dev/extres/clk/clk_mux.h>
49
50 #include <dev/extres/hwreset/hwreset.h>
51
52 #include <arm/allwinner/clkng/aw_ccung.h>
53
54 #include <dt-bindings/clock/sun8i-de2.h>
55 #include <dt-bindings/reset/sun8i-de2.h>
56
57 enum CCU_DE2 {
58 H3_CCU = 1,
59 A64_CCU,
60 };
61
62 /* Non exported clocks */
63 #define CLK_MIXER0_DIV 3
64 #define CLK_MIXER1_DIV 4
65 #define CLK_WB_DIV 5
66
67 static struct aw_ccung_reset h3_de2_ccu_resets[] = {
68 CCU_RESET(RST_MIXER0, 0x08, 0)
69 CCU_RESET(RST_WB, 0x08, 2)
70 };
71
72 static struct aw_ccung_reset a64_de2_ccu_resets[] = {
73 CCU_RESET(RST_MIXER0, 0x08, 0)
74 CCU_RESET(RST_MIXER1, 0x08, 1)
75 CCU_RESET(RST_WB, 0x08, 2)
76 };
77
78 static struct aw_ccung_gate h3_de2_ccu_gates[] = {
79 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0)
80 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2)
81
82 CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0)
83 CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2)
84 };
85
86 static struct aw_ccung_gate a64_de2_ccu_gates[] = {
87 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0)
88 CCU_GATE(CLK_BUS_MIXER1, "mixer1", "mixer1-div", 0x00, 1)
89 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2)
90
91 CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0)
92 CCU_GATE(CLK_MIXER1, "bus-mixer1", "bus-de", 0x04, 1)
93 CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2)
94 };
95
96 static const char *div_parents[] = {"de"};
97
98 NM_CLK(mixer0_div_clk,
99 CLK_MIXER0_DIV, /* id */
100 "mixer0-div", div_parents, /* names, parents */
101 0x0C, /* offset */
102 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/
103 0, 4, 0, 0, /* M flags */
104 0, 0, /* mux */
105 0, /* gate */
106 AW_CLK_SCALE_CHANGE); /* flags */
107
108 NM_CLK(mixer1_div_clk,
109 CLK_MIXER1_DIV, /* id */
110 "mixer1-div", div_parents, /* names, parents */
111 0x0C, /* offset */
112 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/
113 4, 4, 0, 0, /* M flags */
114 0, 0, /* mux */
115 0, /* gate */
116 AW_CLK_SCALE_CHANGE); /* flags */
117
118 NM_CLK(wb_div_clk,
119 CLK_WB_DIV, /* id */
120 "wb-div", div_parents, /* names, parents */
121 0x0C, /* offset */
122 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/
123 8, 4, 0, 0, /* M flags */
124 0, 0, /* mux */
125 0, /* gate */
126 AW_CLK_SCALE_CHANGE); /* flags */
127
128 static struct aw_ccung_clk h3_de2_ccu_clks[] = {
129 { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk},
130 { .type = AW_CLK_NM, .clk.nm = &wb_div_clk},
131 };
132
133 static struct aw_ccung_clk a64_de2_ccu_clks[] = {
134 { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk},
135 { .type = AW_CLK_NM, .clk.nm = &mixer1_div_clk},
136 { .type = AW_CLK_NM, .clk.nm = &wb_div_clk},
137 };
138
139 static struct ofw_compat_data compat_data[] = {
140 {"allwinner,sun8i-h3-de2-clk", H3_CCU},
141 {"allwinner,sun50i-a64-de2-clk", A64_CCU},
142 {NULL, 0}
143 };
144
145 static int
ccu_de2_probe(device_t dev)146 ccu_de2_probe(device_t dev)
147 {
148
149 if (!ofw_bus_status_okay(dev))
150 return (ENXIO);
151
152 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
153 return (ENXIO);
154
155 device_set_desc(dev, "Allwinner DE2 Clock Control Unit");
156 return (BUS_PROBE_DEFAULT);
157 }
158
159 static int
ccu_de2_attach(device_t dev)160 ccu_de2_attach(device_t dev)
161 {
162 struct aw_ccung_softc *sc;
163 phandle_t node;
164 clk_t mod, bus;
165 hwreset_t rst_de;
166 enum CCU_DE2 type;
167
168 sc = device_get_softc(dev);
169 node = ofw_bus_get_node(dev);
170
171 type = (enum CCU_DE2)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
172
173 switch (type) {
174 case H3_CCU:
175 sc->resets = h3_de2_ccu_resets;
176 sc->nresets = nitems(h3_de2_ccu_resets);
177 sc->gates = h3_de2_ccu_gates;
178 sc->ngates = nitems(h3_de2_ccu_gates);
179 sc->clks = h3_de2_ccu_clks;
180 sc->nclks = nitems(h3_de2_ccu_clks);
181 break;
182 case A64_CCU:
183 sc->resets = a64_de2_ccu_resets;
184 sc->nresets = nitems(a64_de2_ccu_resets);
185 sc->gates = a64_de2_ccu_gates;
186 sc->ngates = nitems(a64_de2_ccu_gates);
187 sc->clks = a64_de2_ccu_clks;
188 sc->nclks = nitems(a64_de2_ccu_clks);
189 break;
190 }
191
192 if (hwreset_get_by_ofw_idx(dev, node, 0, &rst_de) != 0) {
193 device_printf(dev, "Cannot get de reset\n");
194 return (ENXIO);
195 }
196 if (hwreset_deassert(rst_de) != 0) {
197 device_printf(dev, "Cannot de-assert de reset\n");
198 return (ENXIO);
199 }
200
201 if (clk_get_by_ofw_name(dev, node, "mod", &mod) != 0) {
202 device_printf(dev, "Cannot get mod clock\n");
203 return (ENXIO);
204 }
205 if (clk_enable(mod) != 0) {
206 device_printf(dev, "Cannot enable mod clock\n");
207 return (ENXIO);
208 }
209
210 if (clk_get_by_ofw_name(dev, node, "bus", &bus) != 0) {
211 device_printf(dev, "Cannot get bus clock\n");
212 return (ENXIO);
213 }
214 if (clk_enable(bus) != 0) {
215 device_printf(dev, "Cannot enable bus clock\n");
216 return (ENXIO);
217 }
218
219 return (aw_ccung_attach(dev));
220 }
221
222 static device_method_t ccu_de2_methods[] = {
223 /* Device interface */
224 DEVMETHOD(device_probe, ccu_de2_probe),
225 DEVMETHOD(device_attach, ccu_de2_attach),
226
227 DEVMETHOD_END
228 };
229
230 DEFINE_CLASS_1(ccu_de2, ccu_de2_driver, ccu_de2_methods,
231 sizeof(struct aw_ccung_softc), aw_ccung_driver);
232
233 EARLY_DRIVER_MODULE(ccu_de2, simplebus, ccu_de2_driver, 0, 0,
234 BUS_PASS_RESOURCE + BUS_PASS_ORDER_LAST);
235