1 /*-
2 * Copyright (c) 2016 Jared McNeill <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 /*
30 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface)
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/rman.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <machine/bus.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <dev/iicbus/iiconf.h>
48 #include <dev/iicbus/iicbus.h>
49
50 #include <dev/extres/clk/clk.h>
51 #include <dev/extres/hwreset/hwreset.h>
52
53 #include "iicbus_if.h"
54
55 #define RSB_CTRL 0x00
56 #define START_TRANS (1 << 7)
57 #define GLOBAL_INT_ENB (1 << 1)
58 #define SOFT_RESET (1 << 0)
59 #define RSB_CCR 0x04
60 #define RSB_INTE 0x08
61 #define RSB_INTS 0x0c
62 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf)
63 #define INT_LOAD_BSY (1 << 2)
64 #define INT_TRANS_ERR (1 << 1)
65 #define INT_TRANS_OVER (1 << 0)
66 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER)
67 #define RSB_DADDR0 0x10
68 #define RSB_DADDR1 0x14
69 #define RSB_DLEN 0x18
70 #define DLEN_READ (1 << 4)
71 #define RSB_DATA0 0x1c
72 #define RSB_DATA1 0x20
73 #define RSB_CMD 0x2c
74 #define CMD_SRTA 0xe8
75 #define CMD_RD8 0x8b
76 #define CMD_RD16 0x9c
77 #define CMD_RD32 0xa6
78 #define CMD_WR8 0x4e
79 #define CMD_WR16 0x59
80 #define CMD_WR32 0x63
81 #define RSB_DAR 0x30
82 #define DAR_RTA (0xff << 16)
83 #define DAR_RTA_SHIFT 16
84 #define DAR_DA (0xffff << 0)
85 #define DAR_DA_SHIFT 0
86
87 #define RSB_MAXLEN 8
88 #define RSB_RESET_RETRY 100
89 #define RSB_I2C_TIMEOUT hz
90
91 #define RSB_ADDR_PMIC_PRIMARY 0x3a3
92 #define RSB_ADDR_PMIC_SECONDARY 0x745
93 #define RSB_ADDR_PERIPH_IC 0xe89
94
95 #define A31_P2WI 1
96 #define A23_RSB 2
97
98 static struct ofw_compat_data compat_data[] = {
99 { "allwinner,sun6i-a31-p2wi", A31_P2WI },
100 { "allwinner,sun8i-a23-rsb", A23_RSB },
101 { NULL, 0 }
102 };
103
104 static struct resource_spec rsb_spec[] = {
105 { SYS_RES_MEMORY, 0, RF_ACTIVE },
106 { -1, 0 }
107 };
108
109 /*
110 * Device address to Run-time address mappings.
111 *
112 * Run-time address (RTA) is an 8-bit value used to address the device during
113 * a read or write transaction. The following are valid RTAs:
114 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
115 *
116 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
117 * and 0x4e for the peripheral IC (where applicable).
118 */
119 static const struct {
120 uint16_t addr;
121 uint8_t rta;
122 } rsb_rtamap[] = {
123 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d },
124 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a },
125 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e },
126 { .addr = 0, .rta = 0 }
127 };
128
129 struct rsb_softc {
130 struct resource *res;
131 struct mtx mtx;
132 clk_t clk;
133 hwreset_t rst;
134 device_t iicbus;
135 int busy;
136 uint32_t status;
137 uint16_t cur_addr;
138 int type;
139
140 struct iic_msg *msg;
141 };
142
143 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx)
144 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
145 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
146 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg))
147 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
148
149 static phandle_t
rsb_get_node(device_t bus,device_t dev)150 rsb_get_node(device_t bus, device_t dev)
151 {
152 return (ofw_bus_get_node(bus));
153 }
154
155 static int
rsb_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)156 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
157 {
158 struct rsb_softc *sc;
159 int retry;
160
161 sc = device_get_softc(dev);
162
163 RSB_LOCK(sc);
164
165 /* Write soft-reset bit and wait for it to self-clear. */
166 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET);
167 for (retry = RSB_RESET_RETRY; retry > 0; retry--)
168 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0)
169 break;
170
171 RSB_UNLOCK(sc);
172
173 if (retry == 0) {
174 device_printf(dev, "soft reset timeout\n");
175 return (ETIMEDOUT);
176 }
177
178 return (IIC_ENOADDR);
179 }
180
181 static uint32_t
rsb_encode(const uint8_t * buf,u_int len,u_int off)182 rsb_encode(const uint8_t *buf, u_int len, u_int off)
183 {
184 uint32_t val;
185 u_int n;
186
187 val = 0;
188 for (n = off; n < MIN(len, 4 + off); n++)
189 val |= ((uint32_t)buf[n] << ((n - off) * NBBY));
190
191 return val;
192 }
193
194 static void
rsb_decode(const uint32_t val,uint8_t * buf,u_int len,u_int off)195 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off)
196 {
197 u_int n;
198
199 for (n = off; n < MIN(len, 4 + off); n++)
200 buf[n] = (val >> ((n - off) * NBBY)) & 0xff;
201 }
202
203 static int
rsb_start(device_t dev)204 rsb_start(device_t dev)
205 {
206 struct rsb_softc *sc;
207 int error, retry;
208
209 sc = device_get_softc(dev);
210
211 RSB_ASSERT_LOCKED(sc);
212
213 /* Start the transfer */
214 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS);
215
216 /* Wait for transfer to complete */
217 error = ETIMEDOUT;
218 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) {
219 sc->status |= RSB_READ(sc, RSB_INTS);
220 if ((sc->status & INT_TRANS_OVER) != 0) {
221 error = 0;
222 break;
223 }
224 DELAY((1000 * hz) / RSB_I2C_TIMEOUT);
225 }
226 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) {
227 device_printf(dev, "transfer error, status 0x%08x\n",
228 sc->status);
229 error = EIO;
230 }
231
232 return (error);
233
234 }
235
236 static int
rsb_set_rta(device_t dev,uint16_t addr)237 rsb_set_rta(device_t dev, uint16_t addr)
238 {
239 struct rsb_softc *sc;
240 uint8_t rta;
241 int i;
242
243 sc = device_get_softc(dev);
244
245 RSB_ASSERT_LOCKED(sc);
246
247 /* Lookup run-time address for given device address */
248 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
249 if (rsb_rtamap[i].addr == addr) {
250 rta = rsb_rtamap[i].rta;
251 break;
252 }
253 if (rta == 0) {
254 device_printf(dev, "RTA not known for address %#x\n", addr);
255 return (ENXIO);
256 }
257
258 /* Set run-time address */
259 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
260 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT));
261 RSB_WRITE(sc, RSB_CMD, CMD_SRTA);
262
263 return (rsb_start(dev));
264 }
265
266 static int
rsb_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)267 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
268 {
269 struct rsb_softc *sc;
270 uint32_t daddr[2], data[2], dlen;
271 uint16_t device_addr;
272 uint8_t cmd;
273 int error;
274
275 sc = device_get_softc(dev);
276
277 /*
278 * P2WI and RSB are not really I2C or SMBus controllers, so there are
279 * some restrictions imposed by the driver.
280 *
281 * Transfers must contain exactly two messages. The first is always
282 * a write, containing a single data byte offset. Data will either
283 * be read from or written to the corresponding data byte in the
284 * second message. The slave address in both messages must be the
285 * same.
286 */
287 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD ||
288 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) ||
289 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN)
290 return (EINVAL);
291
292 /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */
293 if (sc->type == A23_RSB) {
294 if ((msgs[1].flags & IIC_M_RD) != 0) {
295 switch (msgs[1].len) {
296 case 1:
297 cmd = CMD_RD8;
298 break;
299 case 2:
300 cmd = CMD_RD16;
301 break;
302 case 4:
303 cmd = CMD_RD32;
304 break;
305 default:
306 return (EINVAL);
307 }
308 } else {
309 switch (msgs[1].len) {
310 case 1:
311 cmd = CMD_WR8;
312 break;
313 case 2:
314 cmd = CMD_WR16;
315 break;
316 case 4:
317 cmd = CMD_WR32;
318 break;
319 default:
320 return (EINVAL);
321 }
322 }
323 }
324
325 RSB_LOCK(sc);
326 while (sc->busy)
327 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
328 sc->busy = 1;
329 sc->status = 0;
330
331 /* Select current run-time address if necessary */
332 if (sc->type == A23_RSB) {
333 device_addr = msgs[0].slave >> 1;
334 if (sc->cur_addr != device_addr) {
335 error = rsb_set_rta(dev, device_addr);
336 if (error != 0)
337 goto done;
338 sc->cur_addr = device_addr;
339 sc->status = 0;
340 }
341 }
342
343 /* Clear interrupt status */
344 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
345
346 /* Program data access address registers */
347 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0);
348 RSB_WRITE(sc, RSB_DADDR0, daddr[0]);
349
350 /* Write data */
351 if ((msgs[1].flags & IIC_M_RD) == 0) {
352 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0);
353 RSB_WRITE(sc, RSB_DATA0, data[0]);
354 }
355
356 /* Set command type for RSB */
357 if (sc->type == A23_RSB)
358 RSB_WRITE(sc, RSB_CMD, cmd);
359
360 /* Program data length register and transfer direction */
361 dlen = msgs[0].len - 1;
362 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD)
363 dlen |= DLEN_READ;
364 RSB_WRITE(sc, RSB_DLEN, dlen);
365
366 /* Start transfer */
367 error = rsb_start(dev);
368 if (error != 0)
369 goto done;
370
371 /* Read data */
372 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) {
373 data[0] = RSB_READ(sc, RSB_DATA0);
374 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0);
375 }
376
377 done:
378 sc->msg = NULL;
379 sc->busy = 0;
380 wakeup(sc);
381 RSB_UNLOCK(sc);
382
383 return (error);
384 }
385
386 static int
rsb_probe(device_t dev)387 rsb_probe(device_t dev)
388 {
389 if (!ofw_bus_status_okay(dev))
390 return (ENXIO);
391
392 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
393 case A23_RSB:
394 device_set_desc(dev, "Allwinner RSB");
395 break;
396 case A31_P2WI:
397 device_set_desc(dev, "Allwinner P2WI");
398 break;
399 default:
400 return (ENXIO);
401 }
402
403 return (BUS_PROBE_DEFAULT);
404 }
405
406 static int
rsb_attach(device_t dev)407 rsb_attach(device_t dev)
408 {
409 struct rsb_softc *sc;
410 int error;
411
412 sc = device_get_softc(dev);
413 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
414
415 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
416
417 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) {
418 error = clk_enable(sc->clk);
419 if (error != 0) {
420 device_printf(dev, "cannot enable clock\n");
421 goto fail;
422 }
423 }
424 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) {
425 error = hwreset_deassert(sc->rst);
426 if (error != 0) {
427 device_printf(dev, "cannot de-assert reset\n");
428 goto fail;
429 }
430 }
431
432 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) {
433 device_printf(dev, "cannot allocate resources for device\n");
434 error = ENXIO;
435 goto fail;
436 }
437
438 sc->iicbus = device_add_child(dev, "iicbus", -1);
439 if (sc->iicbus == NULL) {
440 device_printf(dev, "cannot add iicbus child device\n");
441 error = ENXIO;
442 goto fail;
443 }
444
445 bus_generic_attach(dev);
446
447 return (0);
448
449 fail:
450 bus_release_resources(dev, rsb_spec, &sc->res);
451 if (sc->rst != NULL)
452 hwreset_release(sc->rst);
453 if (sc->clk != NULL)
454 clk_release(sc->clk);
455 mtx_destroy(&sc->mtx);
456 return (error);
457 }
458
459 static device_method_t rsb_methods[] = {
460 /* Device interface */
461 DEVMETHOD(device_probe, rsb_probe),
462 DEVMETHOD(device_attach, rsb_attach),
463
464 /* Bus interface */
465 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
466 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
467 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
468 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
469 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
470 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
471 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
472 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
473 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
474
475 /* OFW methods */
476 DEVMETHOD(ofw_bus_get_node, rsb_get_node),
477
478 /* iicbus interface */
479 DEVMETHOD(iicbus_callback, iicbus_null_callback),
480 DEVMETHOD(iicbus_reset, rsb_reset),
481 DEVMETHOD(iicbus_transfer, rsb_transfer),
482
483 DEVMETHOD_END
484 };
485
486 static driver_t rsb_driver = {
487 "iichb",
488 rsb_methods,
489 sizeof(struct rsb_softc),
490 };
491
492 static devclass_t rsb_devclass;
493
494 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0,
495 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
496 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0,
497 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
498 MODULE_VERSION(rsb, 1);
499 MODULE_DEPEND(rsb, iicbus, 1, 1, 1);
500 SIMPLEBUS_PNP_INFO(compat_data);
501