1 /*-
2 * Copyright (c) 2016 Jared McNeill <[email protected]>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface)
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/rman.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <machine/bus.h>
40
41 #include <dev/ofw/ofw_bus.h>
42 #include <dev/ofw/ofw_bus_subr.h>
43
44 #include <dev/iicbus/iiconf.h>
45 #include <dev/iicbus/iicbus.h>
46
47 #include <dev/extres/clk/clk.h>
48 #include <dev/extres/hwreset/hwreset.h>
49
50 #include "iicbus_if.h"
51
52 #define RSB_CTRL 0x00
53 #define START_TRANS (1 << 7)
54 #define GLOBAL_INT_ENB (1 << 1)
55 #define SOFT_RESET (1 << 0)
56 #define RSB_CCR 0x04
57 #define RSB_INTE 0x08
58 #define RSB_INTS 0x0c
59 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf)
60 #define INT_LOAD_BSY (1 << 2)
61 #define INT_TRANS_ERR (1 << 1)
62 #define INT_TRANS_OVER (1 << 0)
63 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER)
64 #define RSB_DADDR0 0x10
65 #define RSB_DADDR1 0x14
66 #define RSB_DLEN 0x18
67 #define DLEN_READ (1 << 4)
68 #define RSB_DATA0 0x1c
69 #define RSB_DATA1 0x20
70 #define RSB_PMCR 0x28
71 #define RSB_PMCR_START (1 << 31)
72 #define RSB_PMCR_DATA(x) (x << 16)
73 #define RSB_PMCR_REG(x) (x << 8)
74 #define RSB_CMD 0x2c
75 #define CMD_SRTA 0xe8
76 #define CMD_RD8 0x8b
77 #define CMD_RD16 0x9c
78 #define CMD_RD32 0xa6
79 #define CMD_WR8 0x4e
80 #define CMD_WR16 0x59
81 #define CMD_WR32 0x63
82 #define RSB_DAR 0x30
83 #define DAR_RTA (0xff << 16)
84 #define DAR_RTA_SHIFT 16
85 #define DAR_DA (0xffff << 0)
86 #define DAR_DA_SHIFT 0
87
88 #define RSB_MAXLEN 8
89 #define RSB_RESET_RETRY 100
90 #define RSB_I2C_TIMEOUT hz
91
92 #define RSB_ADDR_PMIC_PRIMARY 0x3a3
93 #define RSB_ADDR_PMIC_SECONDARY 0x745
94 #define RSB_ADDR_PERIPH_IC 0xe89
95
96 #define PMIC_MODE_REG 0x3e
97 #define PMIC_MODE_I2C 0x00
98 #define PMIC_MODE_RSB 0x7c
99
100 #define A31_P2WI 1
101 #define A23_RSB 2
102
103 static struct ofw_compat_data compat_data[] = {
104 { "allwinner,sun6i-a31-p2wi", A31_P2WI },
105 { "allwinner,sun8i-a23-rsb", A23_RSB },
106 { NULL, 0 }
107 };
108
109 static struct resource_spec rsb_spec[] = {
110 { SYS_RES_MEMORY, 0, RF_ACTIVE },
111 { -1, 0 }
112 };
113
114 /*
115 * Device address to Run-time address mappings.
116 *
117 * Run-time address (RTA) is an 8-bit value used to address the device during
118 * a read or write transaction. The following are valid RTAs:
119 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
120 *
121 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
122 * and 0x4e for the peripheral IC (where applicable).
123 */
124 static const struct {
125 uint16_t addr;
126 uint8_t rta;
127 } rsb_rtamap[] = {
128 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d },
129 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a },
130 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e },
131 { .addr = 0, .rta = 0 }
132 };
133
134 struct rsb_softc {
135 struct resource *res;
136 struct mtx mtx;
137 clk_t clk;
138 hwreset_t rst;
139 device_t iicbus;
140 int busy;
141 uint32_t status;
142 uint16_t cur_addr;
143 int type;
144
145 struct iic_msg *msg;
146 };
147
148 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx)
149 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
150 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
151 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg))
152 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
153
154 static phandle_t
rsb_get_node(device_t bus,device_t dev)155 rsb_get_node(device_t bus, device_t dev)
156 {
157 return (ofw_bus_get_node(bus));
158 }
159
160 static int
rsb_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)161 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
162 {
163 struct rsb_softc *sc;
164 int retry;
165
166 sc = device_get_softc(dev);
167
168 RSB_LOCK(sc);
169
170 /* Write soft-reset bit and wait for it to self-clear. */
171 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET);
172 for (retry = RSB_RESET_RETRY; retry > 0; retry--)
173 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0)
174 break;
175
176 RSB_UNLOCK(sc);
177
178 if (retry == 0) {
179 device_printf(dev, "soft reset timeout\n");
180 return (ETIMEDOUT);
181 }
182
183 return (IIC_ENOADDR);
184 }
185
186 static uint32_t
rsb_encode(const uint8_t * buf,u_int len,u_int off)187 rsb_encode(const uint8_t *buf, u_int len, u_int off)
188 {
189 uint32_t val;
190 u_int n;
191
192 val = 0;
193 for (n = off; n < MIN(len, 4 + off); n++)
194 val |= ((uint32_t)buf[n] << ((n - off) * NBBY));
195
196 return val;
197 }
198
199 static void
rsb_decode(const uint32_t val,uint8_t * buf,u_int len,u_int off)200 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off)
201 {
202 u_int n;
203
204 for (n = off; n < MIN(len, 4 + off); n++)
205 buf[n] = (val >> ((n - off) * NBBY)) & 0xff;
206 }
207
208 static int
rsb_start(device_t dev)209 rsb_start(device_t dev)
210 {
211 struct rsb_softc *sc;
212 int error, retry;
213
214 sc = device_get_softc(dev);
215
216 RSB_ASSERT_LOCKED(sc);
217
218 /* Start the transfer */
219 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS);
220
221 /* Wait for transfer to complete */
222 error = ETIMEDOUT;
223 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) {
224 sc->status |= RSB_READ(sc, RSB_INTS);
225 if ((sc->status & INT_TRANS_OVER) != 0) {
226 error = 0;
227 break;
228 }
229 DELAY((1000 * hz) / RSB_I2C_TIMEOUT);
230 }
231 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) {
232 device_printf(dev, "transfer error, status 0x%08x\n",
233 sc->status);
234 error = EIO;
235 }
236
237 return (error);
238
239 }
240
241 static int
rsb_set_rta(device_t dev,uint16_t addr)242 rsb_set_rta(device_t dev, uint16_t addr)
243 {
244 struct rsb_softc *sc;
245 uint8_t rta;
246 int i;
247
248 sc = device_get_softc(dev);
249
250 RSB_ASSERT_LOCKED(sc);
251
252 /* Lookup run-time address for given device address */
253 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
254 if (rsb_rtamap[i].addr == addr) {
255 rta = rsb_rtamap[i].rta;
256 break;
257 }
258 if (rta == 0) {
259 device_printf(dev, "RTA not known for address %#x\n", addr);
260 return (ENXIO);
261 }
262
263 /* Set run-time address */
264 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
265 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT));
266 RSB_WRITE(sc, RSB_CMD, CMD_SRTA);
267
268 return (rsb_start(dev));
269 }
270
271 static int
rsb_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)272 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
273 {
274 struct rsb_softc *sc;
275 uint32_t daddr[2], data[2], dlen;
276 uint16_t device_addr;
277 uint8_t cmd;
278 int error;
279
280 sc = device_get_softc(dev);
281
282 /*
283 * P2WI and RSB are not really I2C or SMBus controllers, so there are
284 * some restrictions imposed by the driver.
285 *
286 * Transfers must contain exactly two messages. The first is always
287 * a write, containing a single data byte offset. Data will either
288 * be read from or written to the corresponding data byte in the
289 * second message. The slave address in both messages must be the
290 * same.
291 */
292 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD ||
293 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) ||
294 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN)
295 return (EINVAL);
296
297 /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */
298 if (sc->type == A23_RSB) {
299 if ((msgs[1].flags & IIC_M_RD) != 0) {
300 switch (msgs[1].len) {
301 case 1:
302 cmd = CMD_RD8;
303 break;
304 case 2:
305 cmd = CMD_RD16;
306 break;
307 case 4:
308 cmd = CMD_RD32;
309 break;
310 default:
311 return (EINVAL);
312 }
313 } else {
314 switch (msgs[1].len) {
315 case 1:
316 cmd = CMD_WR8;
317 break;
318 case 2:
319 cmd = CMD_WR16;
320 break;
321 case 4:
322 cmd = CMD_WR32;
323 break;
324 default:
325 return (EINVAL);
326 }
327 }
328 }
329
330 RSB_LOCK(sc);
331 while (sc->busy)
332 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
333 sc->busy = 1;
334 sc->status = 0;
335
336 /* Select current run-time address if necessary */
337 if (sc->type == A23_RSB) {
338 device_addr = msgs[0].slave >> 1;
339 if (sc->cur_addr != device_addr) {
340 error = rsb_set_rta(dev, device_addr);
341 if (error != 0)
342 goto done;
343 sc->cur_addr = device_addr;
344 sc->status = 0;
345 }
346 }
347
348 /* Clear interrupt status */
349 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
350
351 /* Program data access address registers */
352 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0);
353 RSB_WRITE(sc, RSB_DADDR0, daddr[0]);
354
355 /* Write data */
356 if ((msgs[1].flags & IIC_M_RD) == 0) {
357 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0);
358 RSB_WRITE(sc, RSB_DATA0, data[0]);
359 }
360
361 /* Set command type for RSB */
362 if (sc->type == A23_RSB)
363 RSB_WRITE(sc, RSB_CMD, cmd);
364
365 /* Program data length register and transfer direction */
366 dlen = msgs[0].len - 1;
367 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD)
368 dlen |= DLEN_READ;
369 RSB_WRITE(sc, RSB_DLEN, dlen);
370
371 /* Start transfer */
372 error = rsb_start(dev);
373 if (error != 0)
374 goto done;
375
376 /* Read data */
377 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) {
378 data[0] = RSB_READ(sc, RSB_DATA0);
379 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0);
380 }
381
382 done:
383 sc->msg = NULL;
384 sc->busy = 0;
385 wakeup(sc);
386 RSB_UNLOCK(sc);
387
388 return (error);
389 }
390
391 static int
rsb_probe(device_t dev)392 rsb_probe(device_t dev)
393 {
394 if (!ofw_bus_status_okay(dev))
395 return (ENXIO);
396
397 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
398 case A23_RSB:
399 device_set_desc(dev, "Allwinner RSB");
400 break;
401 case A31_P2WI:
402 device_set_desc(dev, "Allwinner P2WI");
403 break;
404 default:
405 return (ENXIO);
406 }
407
408 return (BUS_PROBE_DEFAULT);
409 }
410
411 static int
rsb_attach(device_t dev)412 rsb_attach(device_t dev)
413 {
414 struct rsb_softc *sc;
415 int error;
416
417 sc = device_get_softc(dev);
418 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
419
420 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
421
422 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) {
423 error = clk_enable(sc->clk);
424 if (error != 0) {
425 device_printf(dev, "cannot enable clock\n");
426 goto fail;
427 }
428 }
429 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) {
430 error = hwreset_deassert(sc->rst);
431 if (error != 0) {
432 device_printf(dev, "cannot de-assert reset\n");
433 goto fail;
434 }
435 }
436
437 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) {
438 device_printf(dev, "cannot allocate resources for device\n");
439 error = ENXIO;
440 goto fail;
441 }
442
443 /* Set the PMIC into RSB mode as ATF might have leave it in I2C mode */
444 RSB_WRITE(sc, RSB_PMCR, RSB_PMCR_REG(PMIC_MODE_REG) | RSB_PMCR_DATA(PMIC_MODE_RSB) | RSB_PMCR_START);
445
446 sc->iicbus = device_add_child(dev, "iicbus", -1);
447 if (sc->iicbus == NULL) {
448 device_printf(dev, "cannot add iicbus child device\n");
449 error = ENXIO;
450 goto fail;
451 }
452
453 bus_generic_attach(dev);
454
455 return (0);
456
457 fail:
458 bus_release_resources(dev, rsb_spec, &sc->res);
459 if (sc->rst != NULL)
460 hwreset_release(sc->rst);
461 if (sc->clk != NULL)
462 clk_release(sc->clk);
463 mtx_destroy(&sc->mtx);
464 return (error);
465 }
466
467 static device_method_t rsb_methods[] = {
468 /* Device interface */
469 DEVMETHOD(device_probe, rsb_probe),
470 DEVMETHOD(device_attach, rsb_attach),
471
472 /* Bus interface */
473 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
474 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
475 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
476 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
477 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
478 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
479 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
480 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
481 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
482
483 /* OFW methods */
484 DEVMETHOD(ofw_bus_get_node, rsb_get_node),
485
486 /* iicbus interface */
487 DEVMETHOD(iicbus_callback, iicbus_null_callback),
488 DEVMETHOD(iicbus_reset, rsb_reset),
489 DEVMETHOD(iicbus_transfer, rsb_transfer),
490
491 DEVMETHOD_END
492 };
493
494 static driver_t rsb_driver = {
495 "iichb",
496 rsb_methods,
497 sizeof(struct rsb_softc),
498 };
499
500 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, 0, 0,
501 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
502 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, 0, 0,
503 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
504 MODULE_VERSION(rsb, 1);
505 MODULE_DEPEND(rsb, iicbus, 1, 1, 1);
506 SIMPLEBUS_PNP_INFO(compat_data);
507