1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #include "opt_kern_tls.h"
30 #include "opt_rss.h"
31 #include "opt_ratelimit.h"
32
33 #include <dev/mlx5/mlx5_en/en.h>
34
35 #include <sys/eventhandler.h>
36 #include <sys/sockio.h>
37 #include <machine/atomic.h>
38
39 #include <net/debugnet.h>
40
41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
42
43 struct mlx5e_channel_param {
44 struct mlx5e_rq_param rq;
45 struct mlx5e_sq_param sq;
46 struct mlx5e_cq_param rx_cq;
47 struct mlx5e_cq_param tx_cq;
48 };
49
50 struct media {
51 u32 subtype;
52 u64 baudrate;
53 };
54
55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] =
56 {
57 [MLX5E_1000BASE_CX_SGMII] = {
58 .subtype = IFM_1000_CX_SGMII,
59 .baudrate = IF_Mbps(1000ULL),
60 },
61 [MLX5E_1000BASE_KX] = {
62 .subtype = IFM_1000_KX,
63 .baudrate = IF_Mbps(1000ULL),
64 },
65 [MLX5E_10GBASE_CX4] = {
66 .subtype = IFM_10G_CX4,
67 .baudrate = IF_Gbps(10ULL),
68 },
69 [MLX5E_10GBASE_KX4] = {
70 .subtype = IFM_10G_KX4,
71 .baudrate = IF_Gbps(10ULL),
72 },
73 [MLX5E_10GBASE_KR] = {
74 .subtype = IFM_10G_KR,
75 .baudrate = IF_Gbps(10ULL),
76 },
77 [MLX5E_20GBASE_KR2] = {
78 .subtype = IFM_20G_KR2,
79 .baudrate = IF_Gbps(20ULL),
80 },
81 [MLX5E_40GBASE_CR4] = {
82 .subtype = IFM_40G_CR4,
83 .baudrate = IF_Gbps(40ULL),
84 },
85 [MLX5E_40GBASE_KR4] = {
86 .subtype = IFM_40G_KR4,
87 .baudrate = IF_Gbps(40ULL),
88 },
89 [MLX5E_56GBASE_R4] = {
90 .subtype = IFM_56G_R4,
91 .baudrate = IF_Gbps(56ULL),
92 },
93 [MLX5E_10GBASE_CR] = {
94 .subtype = IFM_10G_CR1,
95 .baudrate = IF_Gbps(10ULL),
96 },
97 [MLX5E_10GBASE_SR] = {
98 .subtype = IFM_10G_SR,
99 .baudrate = IF_Gbps(10ULL),
100 },
101 [MLX5E_10GBASE_ER_LR] = {
102 .subtype = IFM_10G_ER,
103 .baudrate = IF_Gbps(10ULL),
104 },
105 [MLX5E_40GBASE_SR4] = {
106 .subtype = IFM_40G_SR4,
107 .baudrate = IF_Gbps(40ULL),
108 },
109 [MLX5E_40GBASE_LR4_ER4] = {
110 .subtype = IFM_40G_LR4,
111 .baudrate = IF_Gbps(40ULL),
112 },
113 [MLX5E_100GBASE_CR4] = {
114 .subtype = IFM_100G_CR4,
115 .baudrate = IF_Gbps(100ULL),
116 },
117 [MLX5E_100GBASE_SR4] = {
118 .subtype = IFM_100G_SR4,
119 .baudrate = IF_Gbps(100ULL),
120 },
121 [MLX5E_100GBASE_KR4] = {
122 .subtype = IFM_100G_KR4,
123 .baudrate = IF_Gbps(100ULL),
124 },
125 [MLX5E_100GBASE_LR4] = {
126 .subtype = IFM_100G_LR4,
127 .baudrate = IF_Gbps(100ULL),
128 },
129 [MLX5E_100BASE_TX] = {
130 .subtype = IFM_100_TX,
131 .baudrate = IF_Mbps(100ULL),
132 },
133 [MLX5E_1000BASE_T] = {
134 .subtype = IFM_1000_T,
135 .baudrate = IF_Mbps(1000ULL),
136 },
137 [MLX5E_10GBASE_T] = {
138 .subtype = IFM_10G_T,
139 .baudrate = IF_Gbps(10ULL),
140 },
141 [MLX5E_25GBASE_CR] = {
142 .subtype = IFM_25G_CR,
143 .baudrate = IF_Gbps(25ULL),
144 },
145 [MLX5E_25GBASE_KR] = {
146 .subtype = IFM_25G_KR,
147 .baudrate = IF_Gbps(25ULL),
148 },
149 [MLX5E_25GBASE_SR] = {
150 .subtype = IFM_25G_SR,
151 .baudrate = IF_Gbps(25ULL),
152 },
153 [MLX5E_50GBASE_CR2] = {
154 .subtype = IFM_50G_CR2,
155 .baudrate = IF_Gbps(50ULL),
156 },
157 [MLX5E_50GBASE_KR2] = {
158 .subtype = IFM_50G_KR2,
159 .baudrate = IF_Gbps(50ULL),
160 },
161 [MLX5E_50GBASE_KR4] = {
162 .subtype = IFM_50G_KR4,
163 .baudrate = IF_Gbps(50ULL),
164 },
165 };
166
167 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] =
168 {
169 /**/
170 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = {
171 .subtype = IFM_100_SGMII,
172 .baudrate = IF_Mbps(100),
173 },
174
175 /**/
176 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = {
177 .subtype = IFM_1000_CX,
178 .baudrate = IF_Mbps(1000),
179 },
180 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
181 .subtype = IFM_1000_SX,
182 .baudrate = IF_Mbps(1000),
183 },
184
185 /**/
186 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = {
187 .subtype = IFM_5000_KR,
188 .baudrate = IF_Mbps(5000),
189 },
190 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = {
191 .subtype = IFM_5000_T,
192 .baudrate = IF_Mbps(5000),
193 },
194
195 /**/
196 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = {
197 .subtype = IFM_10G_KR,
198 .baudrate = IF_Gbps(10ULL),
199 },
200 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
201 .subtype = IFM_10G_CR1,
202 .baudrate = IF_Gbps(10ULL),
203 },
204 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
205 .subtype = IFM_10G_SR,
206 .baudrate = IF_Gbps(10ULL),
207 },
208
209 /**/
210 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = {
211 .subtype = IFM_40G_KR4,
212 .baudrate = IF_Gbps(40ULL),
213 },
214 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
215 .subtype = IFM_40G_CR4,
216 .baudrate = IF_Gbps(40ULL),
217 },
218 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
219 .subtype = IFM_40G_SR4,
220 .baudrate = IF_Gbps(40ULL),
221 },
222
223 /**/
224 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = {
225 .subtype = IFM_25G_KR,
226 .baudrate = IF_Gbps(25ULL),
227 },
228 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
229 .subtype = IFM_25G_CR,
230 .baudrate = IF_Gbps(25ULL),
231 },
232 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
233 .subtype = IFM_25G_SR,
234 .baudrate = IF_Gbps(25ULL),
235 },
236 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = {
237 .subtype = IFM_25G_T,
238 .baudrate = IF_Gbps(25ULL),
239 },
240
241 /**/
242 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = {
243 .subtype = IFM_50G_KR2,
244 .baudrate = IF_Gbps(50ULL),
245 },
246 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
247 .subtype = IFM_50G_CR2,
248 .baudrate = IF_Gbps(50ULL),
249 },
250 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
251 .subtype = IFM_50G_SR2,
252 .baudrate = IF_Gbps(50ULL),
253 },
254
255 /**/
256 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = {
257 .subtype = IFM_50G_KR_PAM4,
258 .baudrate = IF_Gbps(50ULL),
259 },
260 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
261 .subtype = IFM_50G_CP,
262 .baudrate = IF_Gbps(50ULL),
263 },
264 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
265 .subtype = IFM_50G_SR,
266 .baudrate = IF_Gbps(50ULL),
267 },
268
269 /**/
270 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = {
271 .subtype = IFM_100G_KR4,
272 .baudrate = IF_Gbps(100ULL),
273 },
274 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
275 .subtype = IFM_100G_CR4,
276 .baudrate = IF_Gbps(100ULL),
277 },
278 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
279 .subtype = IFM_100G_SR4,
280 .baudrate = IF_Gbps(100ULL),
281 },
282
283 /**/
284 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = {
285 .subtype = IFM_100G_KR_PAM4,
286 .baudrate = IF_Gbps(100ULL),
287 },
288 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
289 .subtype = IFM_100G_CR_PAM4,
290 .baudrate = IF_Gbps(100ULL),
291 },
292 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
293 .subtype = IFM_100G_SR2, /* XXX */
294 .baudrate = IF_Gbps(100ULL),
295 },
296
297 /**/
298 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = {
299 .subtype = IFM_100G_KR4,
300 .baudrate = IF_Gbps(100ULL),
301 },
302 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
303 .subtype = IFM_100G_CP2,
304 .baudrate = IF_Gbps(100ULL),
305 },
306 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
307 .subtype = IFM_100G_SR2,
308 .baudrate = IF_Gbps(100ULL),
309 },
310
311 /**/
312 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = {
313 .subtype = IFM_200G_KR4_PAM4, /* XXX */
314 .baudrate = IF_Gbps(200ULL),
315 },
316 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
317 .subtype = IFM_200G_CR4_PAM4, /* XXX */
318 .baudrate = IF_Gbps(200ULL),
319 },
320 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
321 .subtype = IFM_200G_SR4, /* XXX */
322 .baudrate = IF_Gbps(200ULL),
323 },
324
325 /**/
326 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = {
327 .subtype = IFM_200G_KR4_PAM4,
328 .baudrate = IF_Gbps(200ULL),
329 },
330 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
331 .subtype = IFM_200G_CR4_PAM4,
332 .baudrate = IF_Gbps(200ULL),
333 },
334 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
335 .subtype = IFM_200G_SR4,
336 .baudrate = IF_Gbps(200ULL),
337 },
338
339 /**/
340 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = {
341 .subtype = IFM_400G_LR8, /* XXX */
342 .baudrate = IF_Gbps(400ULL),
343 },
344
345 /**/
346 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = {
347 .subtype = IFM_400G_LR8, /* XXX */
348 .baudrate = IF_Gbps(400ULL),
349 },
350 };
351
352 DEBUGNET_DEFINE(mlx5_en);
353
354 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
355
356 static void
mlx5e_update_carrier(struct mlx5e_priv * priv)357 mlx5e_update_carrier(struct mlx5e_priv *priv)
358 {
359 struct mlx5_core_dev *mdev = priv->mdev;
360 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
361 u32 eth_proto_oper;
362 int error;
363 u8 i;
364 u8 cable_type;
365 u8 port_state;
366 u8 is_er_type;
367 bool ext;
368 struct media media_entry = {};
369
370 port_state = mlx5_query_vport_state(mdev,
371 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
372
373 if (port_state == VPORT_STATE_UP) {
374 priv->media_status_last |= IFM_ACTIVE;
375 } else {
376 priv->media_status_last &= ~IFM_ACTIVE;
377 priv->media_active_last = IFM_ETHER;
378 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
379 return;
380 }
381
382 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
383 MLX5_PTYS_EN, 1);
384 if (error) {
385 priv->media_active_last = IFM_ETHER;
386 priv->ifp->if_baudrate = 1;
387 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
388 error);
389 return;
390 }
391
392 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
393 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
394 eth_proto_oper);
395
396 i = ilog2(eth_proto_oper);
397
398 if (ext) {
399 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type);
400 if (error != 0) {
401 /* use fallback entry */
402 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN];
403
404 mlx5_en_err(priv->ifp,
405 "query port pddr failed: %d\n", error);
406 } else {
407 media_entry = mlx5e_ext_mode_table[i][cable_type];
408
409 /* check if we should use fallback entry */
410 if (media_entry.subtype == 0)
411 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN];
412 }
413 } else {
414 media_entry = mlx5e_mode_table[i];
415 }
416
417 if (media_entry.subtype == 0) {
418 mlx5_en_err(priv->ifp,
419 "Could not find operational media subtype\n");
420 return;
421 }
422
423 switch (media_entry.subtype) {
424 case IFM_10G_ER:
425 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
426 if (error != 0) {
427 mlx5_en_err(priv->ifp,
428 "query port pddr failed: %d\n", error);
429 }
430 if (error != 0 || is_er_type == 0)
431 media_entry.subtype = IFM_10G_LR;
432 break;
433 case IFM_40G_LR4:
434 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
435 if (error != 0) {
436 mlx5_en_err(priv->ifp,
437 "query port pddr failed: %d\n", error);
438 }
439 if (error == 0 && is_er_type != 0)
440 media_entry.subtype = IFM_40G_ER4;
441 break;
442 }
443 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
444 priv->ifp->if_baudrate = media_entry.baudrate;
445
446 if_link_state_change(priv->ifp, LINK_STATE_UP);
447 }
448
449 static void
mlx5e_media_status(struct ifnet * dev,struct ifmediareq * ifmr)450 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
451 {
452 struct mlx5e_priv *priv = dev->if_softc;
453
454 ifmr->ifm_status = priv->media_status_last;
455 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last |
456 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
457 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
458
459 }
460
461 static u32
mlx5e_find_link_mode(u32 subtype,bool ext)462 mlx5e_find_link_mode(u32 subtype, bool ext)
463 {
464 u32 link_mode = 0;
465
466 switch (subtype) {
467 case 0:
468 goto done;
469 case IFM_10G_LR:
470 subtype = IFM_10G_ER;
471 break;
472 case IFM_40G_ER4:
473 subtype = IFM_40G_LR4;
474 break;
475 default:
476 break;
477 }
478
479 if (ext) {
480 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) {
481 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) {
482 if (mlx5e_ext_mode_table[i][j].subtype == subtype)
483 link_mode |= MLX5E_PROT_MASK(i);
484 }
485 }
486 } else {
487 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) {
488 if (mlx5e_mode_table[i].subtype == subtype)
489 link_mode |= MLX5E_PROT_MASK(i);
490 }
491 }
492 done:
493 return (link_mode);
494 }
495
496 static int
mlx5e_set_port_pause_and_pfc(struct mlx5e_priv * priv)497 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
498 {
499 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
500 priv->params.rx_pauseframe_control,
501 priv->params.tx_pauseframe_control,
502 priv->params.rx_priority_flow_control,
503 priv->params.tx_priority_flow_control));
504 }
505
506 static int
mlx5e_set_port_pfc(struct mlx5e_priv * priv)507 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
508 {
509 int error;
510
511 if (priv->gone != 0) {
512 error = -ENXIO;
513 } else if (priv->params.rx_pauseframe_control ||
514 priv->params.tx_pauseframe_control) {
515 mlx5_en_err(priv->ifp,
516 "Global pauseframes must be disabled before enabling PFC.\n");
517 error = -EINVAL;
518 } else {
519 error = mlx5e_set_port_pause_and_pfc(priv);
520 }
521 return (error);
522 }
523
524 static int
mlx5e_media_change(struct ifnet * dev)525 mlx5e_media_change(struct ifnet *dev)
526 {
527 struct mlx5e_priv *priv = dev->if_softc;
528 struct mlx5_core_dev *mdev = priv->mdev;
529 u32 eth_proto_cap;
530 u32 link_mode;
531 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
532 int was_opened;
533 int locked;
534 int error;
535 bool ext;
536
537 locked = PRIV_LOCKED(priv);
538 if (!locked)
539 PRIV_LOCK(priv);
540
541 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
542 error = EINVAL;
543 goto done;
544 }
545
546 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
547 MLX5_PTYS_EN, 1);
548 if (error != 0) {
549 mlx5_en_err(dev, "Query port media capability failed\n");
550 goto done;
551 }
552
553 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
554 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
555
556 /* query supported capabilities */
557 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
558 eth_proto_capability);
559
560 /* check for autoselect */
561 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
562 link_mode = eth_proto_cap;
563 if (link_mode == 0) {
564 mlx5_en_err(dev, "Port media capability is zero\n");
565 error = EINVAL;
566 goto done;
567 }
568 } else {
569 link_mode = link_mode & eth_proto_cap;
570 if (link_mode == 0) {
571 mlx5_en_err(dev, "Not supported link mode requested\n");
572 error = EINVAL;
573 goto done;
574 }
575 }
576 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
577 /* check if PFC is enabled */
578 if (priv->params.rx_priority_flow_control ||
579 priv->params.tx_priority_flow_control) {
580 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
581 error = EINVAL;
582 goto done;
583 }
584 }
585 /* update pauseframe control bits */
586 priv->params.rx_pauseframe_control =
587 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
588 priv->params.tx_pauseframe_control =
589 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
590
591 /* check if device is opened */
592 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
593
594 /* reconfigure the hardware */
595 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
596 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
597 error = -mlx5e_set_port_pause_and_pfc(priv);
598 if (was_opened)
599 mlx5_set_port_status(mdev, MLX5_PORT_UP);
600
601 done:
602 if (!locked)
603 PRIV_UNLOCK(priv);
604 return (error);
605 }
606
607 static void
mlx5e_update_carrier_work(struct work_struct * work)608 mlx5e_update_carrier_work(struct work_struct *work)
609 {
610 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
611 update_carrier_work);
612
613 PRIV_LOCK(priv);
614 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
615 mlx5e_update_carrier(priv);
616 PRIV_UNLOCK(priv);
617 }
618
619 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
620 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
621
622 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
623 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
624
625 static void
mlx5e_update_pcie_counters(struct mlx5e_priv * priv)626 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
627 {
628 struct mlx5_core_dev *mdev = priv->mdev;
629 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
630 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
631 void *out;
632 void *in;
633 int err;
634
635 /* allocate firmware request structures */
636 in = mlx5_vzalloc(sz);
637 out = mlx5_vzalloc(sz);
638 if (in == NULL || out == NULL)
639 goto free_out;
640
641 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
642 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
643 if (err != 0)
644 goto free_out;
645
646 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
647 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
648
649 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
650 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
651 if (err != 0)
652 goto free_out;
653
654 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
655
656 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
657 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
658 if (err != 0)
659 goto free_out;
660
661 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
662
663 free_out:
664 /* free firmware request structures */
665 kvfree(in);
666 kvfree(out);
667 }
668
669 /*
670 * This function reads the physical port counters from the firmware
671 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
672 * macros. The output is converted from big-endian 64-bit values into
673 * host endian ones and stored in the "priv->stats.pport" structure.
674 */
675 static void
mlx5e_update_pport_counters(struct mlx5e_priv * priv)676 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
677 {
678 struct mlx5_core_dev *mdev = priv->mdev;
679 struct mlx5e_pport_stats *s = &priv->stats.pport;
680 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
681 u32 *in;
682 u32 *out;
683 const u64 *ptr;
684 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
685 unsigned x;
686 unsigned y;
687 unsigned z;
688
689 /* allocate firmware request structures */
690 in = mlx5_vzalloc(sz);
691 out = mlx5_vzalloc(sz);
692 if (in == NULL || out == NULL)
693 goto free_out;
694
695 /*
696 * Get pointer to the 64-bit counter set which is located at a
697 * fixed offset in the output firmware request structure:
698 */
699 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
700
701 MLX5_SET(ppcnt_reg, in, local_port, 1);
702
703 /* read IEEE802_3 counter group using predefined counter layout */
704 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
705 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
706 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
707 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
708 s->arg[y] = be64toh(ptr[x]);
709
710 /* read RFC2819 counter group using predefined counter layout */
711 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
712 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
713 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
714 s->arg[y] = be64toh(ptr[x]);
715
716 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
717 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
718 s_debug->arg[y] = be64toh(ptr[x]);
719
720 /* read RFC2863 counter group using predefined counter layout */
721 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
722 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
723 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
724 s_debug->arg[y] = be64toh(ptr[x]);
725
726 /* read physical layer stats counter group using predefined counter layout */
727 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
728 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
729 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
730 s_debug->arg[y] = be64toh(ptr[x]);
731
732 /* read Extended Ethernet counter group using predefined counter layout */
733 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
734 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
735 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
736 s_debug->arg[y] = be64toh(ptr[x]);
737
738 /* read Extended Statistical Group */
739 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
740 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
741 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
742 /* read Extended Statistical counter group using predefined counter layout */
743 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
744 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
745
746 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
747 s_debug->arg[y] = be64toh(ptr[x]);
748 }
749
750 /* read PCIE counters */
751 mlx5e_update_pcie_counters(priv);
752
753 /* read per-priority counters */
754 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
755
756 /* iterate all the priorities */
757 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
758 MLX5_SET(ppcnt_reg, in, prio_tc, z);
759 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
760
761 /* read per priority stats counter group using predefined counter layout */
762 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
763 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
764 s->arg[y] = be64toh(ptr[x]);
765 }
766
767 free_out:
768 /* free firmware request structures */
769 kvfree(in);
770 kvfree(out);
771 }
772
773 static void
mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv * priv)774 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
775 {
776 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
777 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
778
779 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
780 return;
781
782 MLX5_SET(query_vnic_env_in, in, opcode,
783 MLX5_CMD_OP_QUERY_VNIC_ENV);
784 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
785 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
786
787 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
788 return;
789
790 priv->stats.vport.rx_steer_missed_packets =
791 MLX5_GET64(query_vnic_env_out, out,
792 vport_env.nic_receive_steering_discard);
793 }
794
795 /*
796 * This function is called regularly to collect all statistics
797 * counters from the firmware. The values can be viewed through the
798 * sysctl interface. Execution is serialized using the priv's global
799 * configuration lock.
800 */
801 static void
mlx5e_update_stats_locked(struct mlx5e_priv * priv)802 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
803 {
804 struct mlx5_core_dev *mdev = priv->mdev;
805 struct mlx5e_vport_stats *s = &priv->stats.vport;
806 struct mlx5e_sq_stats *sq_stats;
807 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
808 u32 *out;
809 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
810 u64 tso_packets = 0;
811 u64 tso_bytes = 0;
812 u64 tx_queue_dropped = 0;
813 u64 tx_defragged = 0;
814 u64 tx_offload_none = 0;
815 u64 lro_packets = 0;
816 u64 lro_bytes = 0;
817 u64 sw_lro_queued = 0;
818 u64 sw_lro_flushed = 0;
819 u64 rx_csum_none = 0;
820 u64 rx_wqe_err = 0;
821 u64 rx_packets = 0;
822 u64 rx_bytes = 0;
823 u32 rx_out_of_buffer = 0;
824 int error;
825 int i;
826 int j;
827
828 out = mlx5_vzalloc(outlen);
829 if (out == NULL)
830 goto free_out;
831
832 /* Collect firts the SW counters and then HW for consistency */
833 for (i = 0; i < priv->params.num_channels; i++) {
834 struct mlx5e_channel *pch = priv->channel + i;
835 struct mlx5e_rq *rq = &pch->rq;
836 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
837
838 /* collect stats from LRO */
839 rq_stats->sw_lro_queued = rq->lro.lro_queued;
840 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
841 sw_lro_queued += rq_stats->sw_lro_queued;
842 sw_lro_flushed += rq_stats->sw_lro_flushed;
843 lro_packets += rq_stats->lro_packets;
844 lro_bytes += rq_stats->lro_bytes;
845 rx_csum_none += rq_stats->csum_none;
846 rx_wqe_err += rq_stats->wqe_err;
847 rx_packets += rq_stats->packets;
848 rx_bytes += rq_stats->bytes;
849
850 for (j = 0; j < priv->num_tc; j++) {
851 sq_stats = &pch->sq[j].stats;
852
853 tso_packets += sq_stats->tso_packets;
854 tso_bytes += sq_stats->tso_bytes;
855 tx_queue_dropped += sq_stats->dropped;
856 tx_queue_dropped += sq_stats->enobuf;
857 tx_defragged += sq_stats->defragged;
858 tx_offload_none += sq_stats->csum_offload_none;
859 }
860 }
861
862 #ifdef RATELIMIT
863 /* Collect statistics from all rate-limit queues */
864 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) {
865 struct mlx5e_rl_worker *rlw = priv->rl.workers + j;
866
867 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) {
868 struct mlx5e_rl_channel *channel = rlw->channels + i;
869 struct mlx5e_sq *sq = channel->sq;
870
871 if (sq == NULL)
872 continue;
873
874 sq_stats = &sq->stats;
875
876 tso_packets += sq_stats->tso_packets;
877 tso_bytes += sq_stats->tso_bytes;
878 tx_queue_dropped += sq_stats->dropped;
879 tx_queue_dropped += sq_stats->enobuf;
880 tx_defragged += sq_stats->defragged;
881 tx_offload_none += sq_stats->csum_offload_none;
882 }
883 }
884 #endif
885
886 /* update counters */
887 s->tso_packets = tso_packets;
888 s->tso_bytes = tso_bytes;
889 s->tx_queue_dropped = tx_queue_dropped;
890 s->tx_defragged = tx_defragged;
891 s->lro_packets = lro_packets;
892 s->lro_bytes = lro_bytes;
893 s->sw_lro_queued = sw_lro_queued;
894 s->sw_lro_flushed = sw_lro_flushed;
895 s->rx_csum_none = rx_csum_none;
896 s->rx_wqe_err = rx_wqe_err;
897 s->rx_packets = rx_packets;
898 s->rx_bytes = rx_bytes;
899
900 mlx5e_grp_vnic_env_update_stats(priv);
901
902 /* HW counters */
903 memset(in, 0, sizeof(in));
904
905 MLX5_SET(query_vport_counter_in, in, opcode,
906 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
907 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
908 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
909
910 memset(out, 0, outlen);
911
912 /* get number of out-of-buffer drops first */
913 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
914 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
915 &rx_out_of_buffer) == 0) {
916 s->rx_out_of_buffer = rx_out_of_buffer;
917 }
918
919 /* get port statistics */
920 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
921 #define MLX5_GET_CTR(out, x) \
922 MLX5_GET64(query_vport_counter_out, out, x)
923
924 s->rx_error_packets =
925 MLX5_GET_CTR(out, received_errors.packets);
926 s->rx_error_bytes =
927 MLX5_GET_CTR(out, received_errors.octets);
928 s->tx_error_packets =
929 MLX5_GET_CTR(out, transmit_errors.packets);
930 s->tx_error_bytes =
931 MLX5_GET_CTR(out, transmit_errors.octets);
932
933 s->rx_unicast_packets =
934 MLX5_GET_CTR(out, received_eth_unicast.packets);
935 s->rx_unicast_bytes =
936 MLX5_GET_CTR(out, received_eth_unicast.octets);
937 s->tx_unicast_packets =
938 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
939 s->tx_unicast_bytes =
940 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
941
942 s->rx_multicast_packets =
943 MLX5_GET_CTR(out, received_eth_multicast.packets);
944 s->rx_multicast_bytes =
945 MLX5_GET_CTR(out, received_eth_multicast.octets);
946 s->tx_multicast_packets =
947 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
948 s->tx_multicast_bytes =
949 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
950
951 s->rx_broadcast_packets =
952 MLX5_GET_CTR(out, received_eth_broadcast.packets);
953 s->rx_broadcast_bytes =
954 MLX5_GET_CTR(out, received_eth_broadcast.octets);
955 s->tx_broadcast_packets =
956 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
957 s->tx_broadcast_bytes =
958 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
959
960 s->tx_packets = s->tx_unicast_packets +
961 s->tx_multicast_packets + s->tx_broadcast_packets;
962 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
963 s->tx_broadcast_bytes;
964
965 /* Update calculated offload counters */
966 s->tx_csum_offload = s->tx_packets - tx_offload_none;
967 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
968 }
969
970 /* Get physical port counters */
971 mlx5e_update_pport_counters(priv);
972
973 s->tx_jumbo_packets =
974 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
975 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
976 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
977 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
978
979 free_out:
980 kvfree(out);
981
982 /* Update diagnostics, if any */
983 if (priv->params_ethtool.diag_pci_enable ||
984 priv->params_ethtool.diag_general_enable) {
985 error = mlx5_core_get_diagnostics_full(mdev,
986 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
987 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
988 if (error != 0)
989 mlx5_en_err(priv->ifp,
990 "Failed reading diagnostics: %d\n", error);
991 }
992
993 /* Update FEC, if any */
994 error = mlx5e_fec_update(priv);
995 if (error != 0 && error != EOPNOTSUPP) {
996 mlx5_en_err(priv->ifp,
997 "Updating FEC failed: %d\n", error);
998 }
999
1000 /* Update temperature, if any */
1001 if (priv->params_ethtool.hw_num_temp != 0) {
1002 error = mlx5e_hw_temperature_update(priv);
1003 if (error != 0 && error != EOPNOTSUPP) {
1004 mlx5_en_err(priv->ifp,
1005 "Updating temperature failed: %d\n", error);
1006 }
1007 }
1008 }
1009
1010 static void
mlx5e_update_stats_work(struct work_struct * work)1011 mlx5e_update_stats_work(struct work_struct *work)
1012 {
1013 struct mlx5e_priv *priv;
1014
1015 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1016 PRIV_LOCK(priv);
1017 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1018 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1019 mlx5e_update_stats_locked(priv);
1020 PRIV_UNLOCK(priv);
1021 }
1022
1023 static void
mlx5e_update_stats(void * arg)1024 mlx5e_update_stats(void *arg)
1025 {
1026 struct mlx5e_priv *priv = arg;
1027
1028 queue_work(priv->wq, &priv->update_stats_work);
1029
1030 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1031 }
1032
1033 static void
mlx5e_async_event_sub(struct mlx5e_priv * priv,enum mlx5_dev_event event)1034 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1035 enum mlx5_dev_event event)
1036 {
1037 switch (event) {
1038 case MLX5_DEV_EVENT_PORT_UP:
1039 case MLX5_DEV_EVENT_PORT_DOWN:
1040 queue_work(priv->wq, &priv->update_carrier_work);
1041 break;
1042
1043 default:
1044 break;
1045 }
1046 }
1047
1048 static void
mlx5e_async_event(struct mlx5_core_dev * mdev,void * vpriv,enum mlx5_dev_event event,unsigned long param)1049 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1050 enum mlx5_dev_event event, unsigned long param)
1051 {
1052 struct mlx5e_priv *priv = vpriv;
1053
1054 mtx_lock(&priv->async_events_mtx);
1055 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1056 mlx5e_async_event_sub(priv, event);
1057 mtx_unlock(&priv->async_events_mtx);
1058 }
1059
1060 static void
mlx5e_enable_async_events(struct mlx5e_priv * priv)1061 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1062 {
1063 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1064 }
1065
1066 static void
mlx5e_disable_async_events(struct mlx5e_priv * priv)1067 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1068 {
1069 mtx_lock(&priv->async_events_mtx);
1070 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1071 mtx_unlock(&priv->async_events_mtx);
1072 }
1073
1074 static void mlx5e_calibration_callout(void *arg);
1075 static int mlx5e_calibration_duration = 20;
1076 static int mlx5e_fast_calibration = 1;
1077 static int mlx5e_normal_calibration = 30;
1078
1079 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1080 "MLX5 timestamp calibration parameters");
1081
1082 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1083 &mlx5e_calibration_duration, 0,
1084 "Duration of initial calibration");
1085 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1086 &mlx5e_fast_calibration, 0,
1087 "Recalibration interval during initial calibration");
1088 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1089 &mlx5e_normal_calibration, 0,
1090 "Recalibration interval during normal operations");
1091
1092 /*
1093 * Ignites the calibration process.
1094 */
1095 static void
mlx5e_reset_calibration_callout(struct mlx5e_priv * priv)1096 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1097 {
1098
1099 if (priv->clbr_done == 0)
1100 mlx5e_calibration_callout(priv);
1101 else
1102 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1103 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1104 mlx5e_normal_calibration) * SBT_1S, 0,
1105 mlx5e_calibration_callout, priv, C_DIRECT_EXEC);
1106 }
1107
1108 static uint64_t
mlx5e_timespec2usec(const struct timespec * ts)1109 mlx5e_timespec2usec(const struct timespec *ts)
1110 {
1111
1112 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1113 }
1114
1115 static uint64_t
mlx5e_hw_clock(struct mlx5e_priv * priv)1116 mlx5e_hw_clock(struct mlx5e_priv *priv)
1117 {
1118 struct mlx5_init_seg *iseg;
1119 uint32_t hw_h, hw_h1, hw_l;
1120
1121 iseg = priv->mdev->iseg;
1122 do {
1123 hw_h = ioread32be(&iseg->internal_timer_h);
1124 hw_l = ioread32be(&iseg->internal_timer_l);
1125 hw_h1 = ioread32be(&iseg->internal_timer_h);
1126 } while (hw_h1 != hw_h);
1127 return (((uint64_t)hw_h << 32) | hw_l);
1128 }
1129
1130 /*
1131 * The calibration callout, it runs either in the context of the
1132 * thread which enables calibration, or in callout. It takes the
1133 * snapshot of system and adapter clocks, then advances the pointers to
1134 * the calibration point to allow rx path to read the consistent data
1135 * lockless.
1136 */
1137 static void
mlx5e_calibration_callout(void * arg)1138 mlx5e_calibration_callout(void *arg)
1139 {
1140 struct mlx5e_priv *priv;
1141 struct mlx5e_clbr_point *next, *curr;
1142 struct timespec ts;
1143 int clbr_curr_next;
1144
1145 priv = arg;
1146 curr = &priv->clbr_points[priv->clbr_curr];
1147 clbr_curr_next = priv->clbr_curr + 1;
1148 if (clbr_curr_next >= nitems(priv->clbr_points))
1149 clbr_curr_next = 0;
1150 next = &priv->clbr_points[clbr_curr_next];
1151
1152 next->base_prev = curr->base_curr;
1153 next->clbr_hw_prev = curr->clbr_hw_curr;
1154
1155 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1156 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1157 0) {
1158 if (priv->clbr_done != 0) {
1159 mlx5_en_err(priv->ifp,
1160 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1161 next->clbr_hw_curr, curr->clbr_hw_prev);
1162 priv->clbr_done = 0;
1163 }
1164 atomic_store_rel_int(&curr->clbr_gen, 0);
1165 return;
1166 }
1167
1168 nanouptime(&ts);
1169 next->base_curr = mlx5e_timespec2usec(&ts);
1170
1171 curr->clbr_gen = 0;
1172 atomic_thread_fence_rel();
1173 priv->clbr_curr = clbr_curr_next;
1174 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1175
1176 if (priv->clbr_done < mlx5e_calibration_duration)
1177 priv->clbr_done++;
1178 mlx5e_reset_calibration_callout(priv);
1179 }
1180
1181 static const char *mlx5e_rq_stats_desc[] = {
1182 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1183 };
1184
1185 static int
mlx5e_create_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1186 mlx5e_create_rq(struct mlx5e_channel *c,
1187 struct mlx5e_rq_param *param,
1188 struct mlx5e_rq *rq)
1189 {
1190 struct mlx5e_priv *priv = c->priv;
1191 struct mlx5_core_dev *mdev = priv->mdev;
1192 char buffer[16];
1193 void *rqc = param->rqc;
1194 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1195 int wq_sz;
1196 int err;
1197 int i;
1198 u32 nsegs, wqe_sz;
1199
1200 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1201 if (err != 0)
1202 goto done;
1203
1204 /* Create DMA descriptor TAG */
1205 if ((err = -bus_dma_tag_create(
1206 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1207 1, /* any alignment */
1208 0, /* no boundary */
1209 BUS_SPACE_MAXADDR, /* lowaddr */
1210 BUS_SPACE_MAXADDR, /* highaddr */
1211 NULL, NULL, /* filter, filterarg */
1212 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1213 nsegs, /* nsegments */
1214 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1215 0, /* flags */
1216 NULL, NULL, /* lockfunc, lockfuncarg */
1217 &rq->dma_tag)))
1218 goto done;
1219
1220 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1221 &rq->wq_ctrl);
1222 if (err)
1223 goto err_free_dma_tag;
1224
1225 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1226
1227 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1228 if (err != 0)
1229 goto err_rq_wq_destroy;
1230
1231 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1232
1233 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1234 if (err)
1235 goto err_rq_wq_destroy;
1236
1237 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN,
1238 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO);
1239 for (i = 0; i != wq_sz; i++) {
1240 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1241 int j;
1242
1243 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1244 if (err != 0) {
1245 while (i--)
1246 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1247 goto err_rq_mbuf_free;
1248 }
1249
1250 /* set value for constant fields */
1251 for (j = 0; j < rq->nsegs; j++)
1252 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1253 }
1254
1255 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1256 if (priv->params.rx_cq_moderation_mode < 2) {
1257 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1258 } else {
1259 void *cqc = container_of(param,
1260 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1261
1262 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1263 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1264 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1265 break;
1266 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1267 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1268 break;
1269 default:
1270 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1271 break;
1272 }
1273 }
1274
1275 rq->ifp = priv->ifp;
1276 rq->channel = c;
1277 rq->ix = c->ix;
1278
1279 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1280 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1281 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1282 rq->stats.arg);
1283 return (0);
1284
1285 err_rq_mbuf_free:
1286 free(rq->mbuf, M_MLX5EN);
1287 tcp_lro_free(&rq->lro);
1288 err_rq_wq_destroy:
1289 mlx5_wq_destroy(&rq->wq_ctrl);
1290 err_free_dma_tag:
1291 bus_dma_tag_destroy(rq->dma_tag);
1292 done:
1293 return (err);
1294 }
1295
1296 static void
mlx5e_destroy_rq(struct mlx5e_rq * rq)1297 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1298 {
1299 int wq_sz;
1300 int i;
1301
1302 /* destroy all sysctl nodes */
1303 sysctl_ctx_free(&rq->stats.ctx);
1304
1305 /* free leftover LRO packets, if any */
1306 tcp_lro_free(&rq->lro);
1307
1308 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1309 for (i = 0; i != wq_sz; i++) {
1310 if (rq->mbuf[i].mbuf != NULL) {
1311 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1312 m_freem(rq->mbuf[i].mbuf);
1313 }
1314 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1315 }
1316 free(rq->mbuf, M_MLX5EN);
1317 mlx5_wq_destroy(&rq->wq_ctrl);
1318 bus_dma_tag_destroy(rq->dma_tag);
1319 }
1320
1321 static int
mlx5e_enable_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param)1322 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1323 {
1324 struct mlx5e_channel *c = rq->channel;
1325 struct mlx5e_priv *priv = c->priv;
1326 struct mlx5_core_dev *mdev = priv->mdev;
1327 void *in;
1328 void *rqc;
1329 void *wq;
1330 int inlen;
1331 int err;
1332 u8 ts_format;
1333
1334 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1335 sizeof(u64) * rq->wq_ctrl.buf.npages;
1336 in = mlx5_vzalloc(inlen);
1337 if (in == NULL)
1338 return (-ENOMEM);
1339
1340 ts_format = mlx5_get_rq_default_ts(mdev);
1341 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1342 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1343
1344 memcpy(rqc, param->rqc, sizeof(param->rqc));
1345
1346 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1347 MLX5_SET(rqc, rqc, ts_format, ts_format);
1348 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1349 if (priv->counter_set_id >= 0)
1350 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1351 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1352 PAGE_SHIFT);
1353 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1354
1355 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1356 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1357
1358 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1359
1360 kvfree(in);
1361
1362 return (err);
1363 }
1364
1365 static int
mlx5e_modify_rq(struct mlx5e_rq * rq,int curr_state,int next_state)1366 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1367 {
1368 struct mlx5e_channel *c = rq->channel;
1369 struct mlx5e_priv *priv = c->priv;
1370 struct mlx5_core_dev *mdev = priv->mdev;
1371
1372 void *in;
1373 void *rqc;
1374 int inlen;
1375 int err;
1376
1377 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1378 in = mlx5_vzalloc(inlen);
1379 if (in == NULL)
1380 return (-ENOMEM);
1381
1382 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1383
1384 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1385 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1386 MLX5_SET(rqc, rqc, state, next_state);
1387
1388 err = mlx5_core_modify_rq(mdev, in, inlen);
1389
1390 kvfree(in);
1391
1392 return (err);
1393 }
1394
1395 static void
mlx5e_disable_rq(struct mlx5e_rq * rq)1396 mlx5e_disable_rq(struct mlx5e_rq *rq)
1397 {
1398 struct mlx5e_channel *c = rq->channel;
1399 struct mlx5e_priv *priv = c->priv;
1400 struct mlx5_core_dev *mdev = priv->mdev;
1401
1402 mlx5_core_destroy_rq(mdev, rq->rqn);
1403 }
1404
1405 static int
mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq * rq)1406 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1407 {
1408 struct mlx5e_channel *c = rq->channel;
1409 struct mlx5e_priv *priv = c->priv;
1410 struct mlx5_wq_ll *wq = &rq->wq;
1411 int i;
1412
1413 for (i = 0; i < 1000; i++) {
1414 if (wq->cur_sz >= priv->params.min_rx_wqes)
1415 return (0);
1416
1417 msleep(4);
1418 }
1419 return (-ETIMEDOUT);
1420 }
1421
1422 static int
mlx5e_open_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1423 mlx5e_open_rq(struct mlx5e_channel *c,
1424 struct mlx5e_rq_param *param,
1425 struct mlx5e_rq *rq)
1426 {
1427 int err;
1428
1429 err = mlx5e_create_rq(c, param, rq);
1430 if (err)
1431 return (err);
1432
1433 /* set CQN in RQ parameters */
1434 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn);
1435
1436 err = mlx5e_enable_rq(rq, param);
1437 if (err)
1438 goto err_destroy_rq;
1439
1440 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1441 if (err)
1442 goto err_disable_rq;
1443
1444 c->rq.enabled = 1;
1445
1446 return (0);
1447
1448 err_disable_rq:
1449 mlx5e_disable_rq(rq);
1450 err_destroy_rq:
1451 mlx5e_destroy_rq(rq);
1452
1453 return (err);
1454 }
1455
1456 static void
mlx5e_close_rq(struct mlx5e_rq * rq)1457 mlx5e_close_rq(struct mlx5e_rq *rq)
1458 {
1459 mtx_lock(&rq->mtx);
1460 rq->enabled = 0;
1461 callout_stop(&rq->watchdog);
1462 mtx_unlock(&rq->mtx);
1463
1464 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1465 }
1466
1467 static void
mlx5e_close_rq_wait(struct mlx5e_rq * rq)1468 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1469 {
1470
1471 mlx5e_disable_rq(rq);
1472 mlx5e_close_cq(&rq->cq);
1473 cancel_work_sync(&rq->dim.work);
1474 mlx5e_destroy_rq(rq);
1475 }
1476
1477 /*
1478 * What is a drop RQ and why is it needed?
1479 *
1480 * The RSS indirection table, also called the RQT, selects the
1481 * destination RQ based on the receive queue number, RQN. The RQT is
1482 * frequently referred to by flow steering rules to distribute traffic
1483 * among multiple RQs. The problem is that the RQs cannot be destroyed
1484 * before the RQT referring them is destroyed too. Further, TLS RX
1485 * rules may still be referring to the RQT even if the link went
1486 * down. Because there is no magic RQN for dropping packets, we create
1487 * a dummy RQ, also called drop RQ, which sole purpose is to drop all
1488 * received packets. When the link goes down this RQN is filled in all
1489 * RQT entries, of the main RQT, so the real RQs which are about to be
1490 * destroyed can be released and the TLS RX rules can be sustained.
1491 */
1492 static void
mlx5e_open_drop_rq_comp(struct mlx5_core_cq * mcq __unused,struct mlx5_eqe * eqe __unused)1493 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused)
1494 {
1495 }
1496
1497 static int
mlx5e_open_drop_rq(struct mlx5e_priv * priv,struct mlx5e_rq * drop_rq)1498 mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1499 struct mlx5e_rq *drop_rq)
1500 {
1501 struct mlx5e_cq_param param_cq = {};
1502 struct mlx5e_rq_param param_rq = {};
1503 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq);
1504 int err;
1505
1506 /* set channel pointer */
1507 drop_rq->channel = priv->channel;
1508
1509 /* set basic CQ parameters needed */
1510 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0);
1511 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index);
1512
1513 /* open receive completion queue */
1514 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq,
1515 &mlx5e_open_drop_rq_comp, 0);
1516 if (err)
1517 goto err_done;
1518
1519 /* set basic WQ parameters needed */
1520 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1521 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1522 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg)));
1523 MLX5_SET(wq, rqc_wq, log_wq_sz, 0);
1524 MLX5_SET(wq, rqc_wq, pd, priv->pdn);
1525
1526 param_rq.wq.linear = 1;
1527
1528 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq,
1529 &drop_rq->wq_ctrl);
1530 if (err)
1531 goto err_close_cq;
1532
1533 /* set CQN in RQ parameters */
1534 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn);
1535
1536 err = mlx5e_enable_rq(drop_rq, ¶m_rq);
1537 if (err)
1538 goto err_wq_destroy;
1539
1540 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1541 if (err)
1542 goto err_disable_rq;
1543
1544 return (err);
1545
1546 err_disable_rq:
1547 mlx5e_disable_rq(drop_rq);
1548 err_wq_destroy:
1549 mlx5_wq_destroy(&drop_rq->wq_ctrl);
1550 err_close_cq:
1551 mlx5e_close_cq(&drop_rq->cq);
1552 err_done:
1553 return (err);
1554 }
1555
1556 static void
mlx5e_close_drop_rq(struct mlx5e_rq * drop_rq)1557 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
1558 {
1559 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1560 mlx5e_disable_rq(drop_rq);
1561 mlx5_wq_destroy(&drop_rq->wq_ctrl);
1562 mlx5e_close_cq(&drop_rq->cq);
1563 }
1564
1565 void
mlx5e_free_sq_db(struct mlx5e_sq * sq)1566 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1567 {
1568 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1569 int x;
1570
1571 for (x = 0; x != wq_sz; x++) {
1572 if (sq->mbuf[x].mbuf != NULL) {
1573 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1574 m_freem(sq->mbuf[x].mbuf);
1575 }
1576 if (sq->mbuf[x].mst != NULL) {
1577 m_snd_tag_rele(sq->mbuf[x].mst);
1578 sq->mbuf[x].mst = NULL;
1579 }
1580 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1581 }
1582 free(sq->mbuf, M_MLX5EN);
1583 }
1584
1585 int
mlx5e_alloc_sq_db(struct mlx5e_sq * sq)1586 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1587 {
1588 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1589 int err;
1590 int x;
1591
1592 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN,
1593 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO);
1594
1595 /* Create DMA descriptor MAPs */
1596 for (x = 0; x != wq_sz; x++) {
1597 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1598 if (err != 0) {
1599 while (x--)
1600 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1601 free(sq->mbuf, M_MLX5EN);
1602 return (err);
1603 }
1604 }
1605 return (0);
1606 }
1607
1608 static const char *mlx5e_sq_stats_desc[] = {
1609 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1610 };
1611
1612 void
mlx5e_update_sq_inline(struct mlx5e_sq * sq)1613 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1614 {
1615 sq->max_inline = sq->priv->params.tx_max_inline;
1616 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1617
1618 /*
1619 * Check if trust state is DSCP or if inline mode is NONE which
1620 * indicates CX-5 or newer hardware.
1621 */
1622 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1623 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1624 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1625 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1626 else
1627 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1628 } else {
1629 sq->min_insert_caps = 0;
1630 }
1631 }
1632
1633 static void
mlx5e_refresh_sq_inline_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)1634 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1635 {
1636 int i;
1637
1638 for (i = 0; i != priv->num_tc; i++) {
1639 mtx_lock(&c->sq[i].lock);
1640 mlx5e_update_sq_inline(&c->sq[i]);
1641 mtx_unlock(&c->sq[i].lock);
1642 }
1643 }
1644
1645 void
mlx5e_refresh_sq_inline(struct mlx5e_priv * priv)1646 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1647 {
1648 int i;
1649
1650 /* check if channels are closed */
1651 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1652 return;
1653
1654 for (i = 0; i < priv->params.num_channels; i++)
1655 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1656 }
1657
1658 static int
mlx5e_create_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1659 mlx5e_create_sq(struct mlx5e_channel *c,
1660 int tc,
1661 struct mlx5e_sq_param *param,
1662 struct mlx5e_sq *sq)
1663 {
1664 struct mlx5e_priv *priv = c->priv;
1665 struct mlx5_core_dev *mdev = priv->mdev;
1666 char buffer[16];
1667 void *sqc = param->sqc;
1668 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1669 int err;
1670
1671 /* Create DMA descriptor TAG */
1672 if ((err = -bus_dma_tag_create(
1673 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1674 1, /* any alignment */
1675 0, /* no boundary */
1676 BUS_SPACE_MAXADDR, /* lowaddr */
1677 BUS_SPACE_MAXADDR, /* highaddr */
1678 NULL, NULL, /* filter, filterarg */
1679 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1680 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1681 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1682 0, /* flags */
1683 NULL, NULL, /* lockfunc, lockfuncarg */
1684 &sq->dma_tag)))
1685 goto done;
1686
1687 sq->mkey_be = cpu_to_be32(priv->mr.key);
1688 sq->ifp = priv->ifp;
1689 sq->priv = priv;
1690 sq->tc = tc;
1691
1692 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1693 &sq->wq_ctrl);
1694 if (err)
1695 goto err_free_dma_tag;
1696
1697 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1698
1699 err = mlx5e_alloc_sq_db(sq);
1700 if (err)
1701 goto err_sq_wq_destroy;
1702
1703 mlx5e_update_sq_inline(sq);
1704
1705 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1706 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1707 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1708 sq->stats.arg);
1709
1710 return (0);
1711
1712 err_sq_wq_destroy:
1713 mlx5_wq_destroy(&sq->wq_ctrl);
1714
1715 err_free_dma_tag:
1716 bus_dma_tag_destroy(sq->dma_tag);
1717 done:
1718 return (err);
1719 }
1720
1721 static void
mlx5e_destroy_sq(struct mlx5e_sq * sq)1722 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1723 {
1724 /* destroy all sysctl nodes */
1725 sysctl_ctx_free(&sq->stats.ctx);
1726
1727 mlx5e_free_sq_db(sq);
1728 mlx5_wq_destroy(&sq->wq_ctrl);
1729 bus_dma_tag_destroy(sq->dma_tag);
1730 }
1731
1732 int
mlx5e_enable_sq(struct mlx5e_sq * sq,struct mlx5e_sq_param * param,const struct mlx5_sq_bfreg * bfreg,int tis_num)1733 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1734 const struct mlx5_sq_bfreg *bfreg, int tis_num)
1735 {
1736 void *in;
1737 void *sqc;
1738 void *wq;
1739 int inlen;
1740 int err;
1741 u8 ts_format;
1742
1743 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1744 sizeof(u64) * sq->wq_ctrl.buf.npages;
1745 in = mlx5_vzalloc(inlen);
1746 if (in == NULL)
1747 return (-ENOMEM);
1748
1749 sq->uar_map = bfreg->map;
1750
1751 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev);
1752 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1753 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1754
1755 memcpy(sqc, param->sqc, sizeof(param->sqc));
1756
1757 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1758 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1759 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1760 MLX5_SET(sqc, sqc, ts_format, ts_format);
1761 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1762 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1763 MLX5_SET(sqc, sqc, allow_swp, 1);
1764
1765 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1766 MLX5_SET(wq, wq, uar_page, bfreg->index);
1767 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1768 PAGE_SHIFT);
1769 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1770
1771 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1772 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1773
1774 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1775
1776 kvfree(in);
1777
1778 return (err);
1779 }
1780
1781 int
mlx5e_modify_sq(struct mlx5e_sq * sq,int curr_state,int next_state)1782 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1783 {
1784 void *in;
1785 void *sqc;
1786 int inlen;
1787 int err;
1788
1789 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1790 in = mlx5_vzalloc(inlen);
1791 if (in == NULL)
1792 return (-ENOMEM);
1793
1794 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1795
1796 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1797 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1798 MLX5_SET(sqc, sqc, state, next_state);
1799
1800 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1801
1802 kvfree(in);
1803
1804 return (err);
1805 }
1806
1807 void
mlx5e_disable_sq(struct mlx5e_sq * sq)1808 mlx5e_disable_sq(struct mlx5e_sq *sq)
1809 {
1810
1811 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1812 }
1813
1814 static int
mlx5e_open_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1815 mlx5e_open_sq(struct mlx5e_channel *c,
1816 int tc,
1817 struct mlx5e_sq_param *param,
1818 struct mlx5e_sq *sq)
1819 {
1820 int err;
1821
1822 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1823
1824 /* ensure the TX completion event factor is not zero */
1825 if (sq->cev_factor == 0)
1826 sq->cev_factor = 1;
1827
1828 err = mlx5e_create_sq(c, tc, param, sq);
1829 if (err)
1830 return (err);
1831
1832 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]);
1833 if (err)
1834 goto err_destroy_sq;
1835
1836 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1837 if (err)
1838 goto err_disable_sq;
1839
1840 WRITE_ONCE(sq->running, 1);
1841
1842 return (0);
1843
1844 err_disable_sq:
1845 mlx5e_disable_sq(sq);
1846 err_destroy_sq:
1847 mlx5e_destroy_sq(sq);
1848
1849 return (err);
1850 }
1851
1852 static void
mlx5e_sq_send_nops_locked(struct mlx5e_sq * sq,int can_sleep)1853 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1854 {
1855 /* fill up remainder with NOPs */
1856 while (sq->cev_counter != 0) {
1857 while (!mlx5e_sq_has_room_for(sq, 1)) {
1858 if (can_sleep != 0) {
1859 mtx_unlock(&sq->lock);
1860 msleep(4);
1861 mtx_lock(&sq->lock);
1862 } else {
1863 goto done;
1864 }
1865 }
1866 /* send a single NOP */
1867 mlx5e_send_nop(sq, 1);
1868 atomic_thread_fence_rel();
1869 }
1870 done:
1871 mlx5e_tx_notify_hw(sq, false);
1872 }
1873
1874 void
mlx5e_sq_cev_timeout(void * arg)1875 mlx5e_sq_cev_timeout(void *arg)
1876 {
1877 struct mlx5e_sq *sq = arg;
1878
1879 mtx_assert(&sq->lock, MA_OWNED);
1880
1881 /* check next state */
1882 switch (sq->cev_next_state) {
1883 case MLX5E_CEV_STATE_SEND_NOPS:
1884 /* fill TX ring with NOPs, if any */
1885 mlx5e_sq_send_nops_locked(sq, 0);
1886
1887 /* check if completed */
1888 if (sq->cev_counter == 0) {
1889 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1890 return;
1891 }
1892 break;
1893 default:
1894 /* send NOPs on next timeout */
1895 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1896 break;
1897 }
1898
1899 /* restart timer */
1900 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1901 }
1902
1903 void
mlx5e_drain_sq(struct mlx5e_sq * sq)1904 mlx5e_drain_sq(struct mlx5e_sq *sq)
1905 {
1906 int error;
1907 struct mlx5_core_dev *mdev= sq->priv->mdev;
1908
1909 /*
1910 * Check if already stopped.
1911 *
1912 * NOTE: Serialization of this function is managed by the
1913 * caller ensuring the priv's state lock is locked or in case
1914 * of rate limit support, a single thread manages drain and
1915 * resume of SQs. The "running" variable can therefore safely
1916 * be read without any locks.
1917 */
1918 if (READ_ONCE(sq->running) == 0)
1919 return;
1920
1921 /* don't put more packets into the SQ */
1922 WRITE_ONCE(sq->running, 0);
1923
1924 /* serialize access to DMA rings */
1925 mtx_lock(&sq->lock);
1926
1927 /* teardown event factor timer, if any */
1928 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1929 callout_stop(&sq->cev_callout);
1930
1931 /* send dummy NOPs in order to flush the transmit ring */
1932 mlx5e_sq_send_nops_locked(sq, 1);
1933 mtx_unlock(&sq->lock);
1934
1935 /* wait till SQ is empty or link is down */
1936 mtx_lock(&sq->lock);
1937 while (sq->cc != sq->pc &&
1938 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1939 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
1940 pci_channel_offline(mdev->pdev) == 0) {
1941 mtx_unlock(&sq->lock);
1942 msleep(1);
1943 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1944 mtx_lock(&sq->lock);
1945 }
1946 mtx_unlock(&sq->lock);
1947
1948 /* error out remaining requests */
1949 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1950 if (error != 0) {
1951 mlx5_en_err(sq->ifp,
1952 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1953 }
1954
1955 /* wait till SQ is empty */
1956 mtx_lock(&sq->lock);
1957 while (sq->cc != sq->pc &&
1958 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
1959 pci_channel_offline(mdev->pdev) == 0) {
1960 mtx_unlock(&sq->lock);
1961 msleep(1);
1962 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1963 mtx_lock(&sq->lock);
1964 }
1965 mtx_unlock(&sq->lock);
1966 }
1967
1968 static void
mlx5e_close_sq_wait(struct mlx5e_sq * sq)1969 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1970 {
1971
1972 mlx5e_drain_sq(sq);
1973 mlx5e_disable_sq(sq);
1974 mlx5e_destroy_sq(sq);
1975 }
1976
1977 static int
mlx5e_create_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)1978 mlx5e_create_cq(struct mlx5e_priv *priv,
1979 struct mlx5e_cq_param *param,
1980 struct mlx5e_cq *cq,
1981 mlx5e_cq_comp_t *comp,
1982 int eq_ix)
1983 {
1984 struct mlx5_core_dev *mdev = priv->mdev;
1985 struct mlx5_core_cq *mcq = &cq->mcq;
1986 int eqn_not_used;
1987 int irqn;
1988 int err;
1989 u32 i;
1990
1991 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1992 if (err)
1993 return (err);
1994
1995 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1996 &cq->wq_ctrl);
1997 if (err)
1998 return (err);
1999
2000 mcq->cqe_sz = 64;
2001 mcq->set_ci_db = cq->wq_ctrl.db.db;
2002 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2003 *mcq->set_ci_db = 0;
2004 *mcq->arm_db = 0;
2005 mcq->vector = eq_ix;
2006 mcq->comp = comp;
2007 mcq->event = mlx5e_cq_error_event;
2008 mcq->irqn = irqn;
2009
2010 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
2011 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
2012
2013 cqe->op_own = 0xf1;
2014 }
2015
2016 cq->priv = priv;
2017
2018 return (0);
2019 }
2020
2021 static void
mlx5e_destroy_cq(struct mlx5e_cq * cq)2022 mlx5e_destroy_cq(struct mlx5e_cq *cq)
2023 {
2024 mlx5_wq_destroy(&cq->wq_ctrl);
2025 }
2026
2027 static int
mlx5e_enable_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param,int eq_ix)2028 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
2029 {
2030 struct mlx5_core_cq *mcq = &cq->mcq;
2031 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2032 void *in;
2033 void *cqc;
2034 int inlen;
2035 int irqn_not_used;
2036 int eqn;
2037 int err;
2038
2039 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2040 sizeof(u64) * cq->wq_ctrl.buf.npages;
2041 in = mlx5_vzalloc(inlen);
2042 if (in == NULL)
2043 return (-ENOMEM);
2044
2045 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2046
2047 memcpy(cqc, param->cqc, sizeof(param->cqc));
2048
2049 mlx5_fill_page_array(&cq->wq_ctrl.buf,
2050 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2051
2052 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2053
2054 MLX5_SET(cqc, cqc, c_eqn, eqn);
2055 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2056 PAGE_SHIFT);
2057 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2058
2059 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out));
2060
2061 kvfree(in);
2062
2063 if (err)
2064 return (err);
2065
2066 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2067
2068 return (0);
2069 }
2070
2071 static void
mlx5e_disable_cq(struct mlx5e_cq * cq)2072 mlx5e_disable_cq(struct mlx5e_cq *cq)
2073 {
2074
2075 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2076 }
2077
2078 int
mlx5e_open_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)2079 mlx5e_open_cq(struct mlx5e_priv *priv,
2080 struct mlx5e_cq_param *param,
2081 struct mlx5e_cq *cq,
2082 mlx5e_cq_comp_t *comp,
2083 int eq_ix)
2084 {
2085 int err;
2086
2087 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2088 if (err)
2089 return (err);
2090
2091 err = mlx5e_enable_cq(cq, param, eq_ix);
2092 if (err)
2093 goto err_destroy_cq;
2094
2095 return (0);
2096
2097 err_destroy_cq:
2098 mlx5e_destroy_cq(cq);
2099
2100 return (err);
2101 }
2102
2103 void
mlx5e_close_cq(struct mlx5e_cq * cq)2104 mlx5e_close_cq(struct mlx5e_cq *cq)
2105 {
2106 mlx5e_disable_cq(cq);
2107 mlx5e_destroy_cq(cq);
2108 }
2109
2110 static int
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2111 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2112 struct mlx5e_channel_param *cparam)
2113 {
2114 int err;
2115 int tc;
2116
2117 for (tc = 0; tc < c->priv->num_tc; tc++) {
2118 /* open completion queue */
2119 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2120 &mlx5e_tx_cq_comp, c->ix);
2121 if (err)
2122 goto err_close_tx_cqs;
2123 }
2124 return (0);
2125
2126 err_close_tx_cqs:
2127 for (tc--; tc >= 0; tc--)
2128 mlx5e_close_cq(&c->sq[tc].cq);
2129
2130 return (err);
2131 }
2132
2133 static void
mlx5e_close_tx_cqs(struct mlx5e_channel * c)2134 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2135 {
2136 int tc;
2137
2138 for (tc = 0; tc < c->priv->num_tc; tc++)
2139 mlx5e_close_cq(&c->sq[tc].cq);
2140 }
2141
2142 static int
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2143 mlx5e_open_sqs(struct mlx5e_channel *c,
2144 struct mlx5e_channel_param *cparam)
2145 {
2146 int err;
2147 int tc;
2148
2149 for (tc = 0; tc < c->priv->num_tc; tc++) {
2150 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2151 if (err)
2152 goto err_close_sqs;
2153 }
2154
2155 return (0);
2156
2157 err_close_sqs:
2158 for (tc--; tc >= 0; tc--)
2159 mlx5e_close_sq_wait(&c->sq[tc]);
2160
2161 return (err);
2162 }
2163
2164 static void
mlx5e_close_sqs_wait(struct mlx5e_channel * c)2165 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2166 {
2167 int tc;
2168
2169 for (tc = 0; tc < c->priv->num_tc; tc++)
2170 mlx5e_close_sq_wait(&c->sq[tc]);
2171 }
2172
2173 static void
mlx5e_chan_static_init(struct mlx5e_priv * priv,struct mlx5e_channel * c,int ix)2174 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2175 {
2176 int tc;
2177
2178 /* setup priv and channel number */
2179 c->priv = priv;
2180 c->ix = ix;
2181
2182 /* setup send tag */
2183 m_snd_tag_init(&c->tag, c->priv->ifp, IF_SND_TAG_TYPE_UNLIMITED);
2184
2185 init_completion(&c->completion);
2186
2187 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2188
2189 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2190
2191 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2192 struct mlx5e_sq *sq = c->sq + tc;
2193
2194 mtx_init(&sq->lock, "mlx5tx",
2195 MTX_NETWORK_LOCK " TX", MTX_DEF);
2196 mtx_init(&sq->comp_lock, "mlx5comp",
2197 MTX_NETWORK_LOCK " TX", MTX_DEF);
2198
2199 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2200 }
2201
2202 mlx5e_iq_static_init(&c->iq);
2203 }
2204
2205 static void
mlx5e_chan_wait_for_completion(struct mlx5e_channel * c)2206 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2207 {
2208
2209 m_snd_tag_rele(&c->tag);
2210 wait_for_completion(&c->completion);
2211 }
2212
2213 static void
mlx5e_priv_wait_for_completion(struct mlx5e_priv * priv,const uint32_t channels)2214 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2215 {
2216 uint32_t x;
2217
2218 for (x = 0; x != channels; x++)
2219 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2220 }
2221
2222 static void
mlx5e_chan_static_destroy(struct mlx5e_channel * c)2223 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2224 {
2225 int tc;
2226
2227 callout_drain(&c->rq.watchdog);
2228
2229 mtx_destroy(&c->rq.mtx);
2230
2231 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2232 callout_drain(&c->sq[tc].cev_callout);
2233 mtx_destroy(&c->sq[tc].lock);
2234 mtx_destroy(&c->sq[tc].comp_lock);
2235 }
2236
2237 mlx5e_iq_static_destroy(&c->iq);
2238 }
2239
2240 static int
mlx5e_open_channel(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam,struct mlx5e_channel * c)2241 mlx5e_open_channel(struct mlx5e_priv *priv,
2242 struct mlx5e_channel_param *cparam,
2243 struct mlx5e_channel *c)
2244 {
2245 struct epoch_tracker et;
2246 int i, err;
2247
2248 /* zero non-persistant data */
2249 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2250 for (i = 0; i != priv->num_tc; i++)
2251 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2252 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start);
2253
2254 /* open transmit completion queue */
2255 err = mlx5e_open_tx_cqs(c, cparam);
2256 if (err)
2257 goto err_free;
2258
2259 /* open receive completion queue */
2260 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2261 &mlx5e_rx_cq_comp, c->ix);
2262 if (err)
2263 goto err_close_tx_cqs;
2264
2265 err = mlx5e_open_sqs(c, cparam);
2266 if (err)
2267 goto err_close_rx_cq;
2268
2269 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq);
2270 if (err)
2271 goto err_close_sqs;
2272
2273 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2274 if (err)
2275 goto err_close_iq;
2276
2277 /* poll receive queue initially */
2278 NET_EPOCH_ENTER(et);
2279 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL);
2280 NET_EPOCH_EXIT(et);
2281
2282 return (0);
2283
2284 err_close_iq:
2285 mlx5e_iq_close(&c->iq);
2286
2287 err_close_sqs:
2288 mlx5e_close_sqs_wait(c);
2289
2290 err_close_rx_cq:
2291 mlx5e_close_cq(&c->rq.cq);
2292
2293 err_close_tx_cqs:
2294 mlx5e_close_tx_cqs(c);
2295
2296 err_free:
2297 return (err);
2298 }
2299
2300 static void
mlx5e_close_channel(struct mlx5e_channel * c)2301 mlx5e_close_channel(struct mlx5e_channel *c)
2302 {
2303 mlx5e_close_rq(&c->rq);
2304 }
2305
2306 static void
mlx5e_close_channel_wait(struct mlx5e_channel * c)2307 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2308 {
2309 mlx5e_close_rq_wait(&c->rq);
2310 mlx5e_iq_close(&c->iq);
2311 mlx5e_close_sqs_wait(c);
2312 mlx5e_close_tx_cqs(c);
2313 }
2314
2315 static int
mlx5e_get_wqe_sz(struct mlx5e_priv * priv,u32 * wqe_sz,u32 * nsegs)2316 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2317 {
2318 u32 r, n;
2319
2320 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2321 MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2322 if (r > MJUM16BYTES)
2323 return (-ENOMEM);
2324
2325 if (r > MJUM9BYTES)
2326 r = MJUM16BYTES;
2327 else if (r > MJUMPAGESIZE)
2328 r = MJUM9BYTES;
2329 else if (r > MCLBYTES)
2330 r = MJUMPAGESIZE;
2331 else
2332 r = MCLBYTES;
2333
2334 /*
2335 * n + 1 must be a power of two, because stride size must be.
2336 * Stride size is 16 * (n + 1), as the first segment is
2337 * control.
2338 */
2339 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2340 ;
2341
2342 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2343 return (-ENOMEM);
2344
2345 *wqe_sz = r;
2346 *nsegs = n;
2347 return (0);
2348 }
2349
2350 static void
mlx5e_build_rq_param(struct mlx5e_priv * priv,struct mlx5e_rq_param * param)2351 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2352 struct mlx5e_rq_param *param)
2353 {
2354 void *rqc = param->rqc;
2355 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2356 u32 wqe_sz, nsegs;
2357
2358 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2359 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2360 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2361 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2362 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2363 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2364 MLX5_SET(wq, wq, pd, priv->pdn);
2365
2366 param->wq.linear = 1;
2367 }
2368
2369 static void
mlx5e_build_sq_param(struct mlx5e_priv * priv,struct mlx5e_sq_param * param)2370 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2371 struct mlx5e_sq_param *param)
2372 {
2373 void *sqc = param->sqc;
2374 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2375
2376 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2377 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2378 MLX5_SET(wq, wq, pd, priv->pdn);
2379
2380 param->wq.linear = 1;
2381 }
2382
2383 static void
mlx5e_build_common_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2384 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2385 struct mlx5e_cq_param *param)
2386 {
2387 void *cqc = param->cqc;
2388
2389 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2390 }
2391
2392 static void
mlx5e_get_default_profile(struct mlx5e_priv * priv,int mode,struct net_dim_cq_moder * ptr)2393 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2394 {
2395
2396 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2397
2398 /* apply LRO restrictions */
2399 if (priv->params.hw_lro_en &&
2400 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2401 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2402 }
2403 }
2404
2405 static void
mlx5e_build_rx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2406 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2407 struct mlx5e_cq_param *param)
2408 {
2409 struct net_dim_cq_moder curr;
2410 void *cqc = param->cqc;
2411
2412 /*
2413 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2414 * format is more beneficial for FreeBSD use case.
2415 *
2416 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2417 * in mlx5e_decompress_cqe.
2418 */
2419 if (priv->params.cqe_zipping_en) {
2420 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2421 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2422 }
2423
2424 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2425
2426 switch (priv->params.rx_cq_moderation_mode) {
2427 case 0:
2428 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2429 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2430 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2431 break;
2432 case 1:
2433 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2434 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2435 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2436 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2437 else
2438 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2439 break;
2440 case 2:
2441 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2442 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2443 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2444 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2445 break;
2446 case 3:
2447 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2448 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2449 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2450 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2451 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2452 else
2453 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2454 break;
2455 default:
2456 break;
2457 }
2458
2459 mlx5e_dim_build_cq_param(priv, param);
2460
2461 mlx5e_build_common_cq_param(priv, param);
2462 }
2463
2464 static void
mlx5e_build_tx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2465 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2466 struct mlx5e_cq_param *param)
2467 {
2468 void *cqc = param->cqc;
2469
2470 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2471 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2472 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2473
2474 switch (priv->params.tx_cq_moderation_mode) {
2475 case 0:
2476 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2477 break;
2478 default:
2479 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2480 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2481 else
2482 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2483 break;
2484 }
2485
2486 mlx5e_build_common_cq_param(priv, param);
2487 }
2488
2489 static void
mlx5e_build_channel_param(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam)2490 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2491 struct mlx5e_channel_param *cparam)
2492 {
2493 memset(cparam, 0, sizeof(*cparam));
2494
2495 mlx5e_build_rq_param(priv, &cparam->rq);
2496 mlx5e_build_sq_param(priv, &cparam->sq);
2497 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2498 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2499 }
2500
2501 static int
mlx5e_open_channels(struct mlx5e_priv * priv)2502 mlx5e_open_channels(struct mlx5e_priv *priv)
2503 {
2504 struct mlx5e_channel_param *cparam;
2505 int err;
2506 int i;
2507 int j;
2508
2509 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2510
2511 mlx5e_build_channel_param(priv, cparam);
2512 for (i = 0; i < priv->params.num_channels; i++) {
2513 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2514 if (err)
2515 goto err_close_channels;
2516
2517 /* Bind interrupt vectors, if any. */
2518 if (priv->params_ethtool.irq_cpu_base > -1) {
2519 cpuset_t cpuset;
2520 int cpu;
2521 int irq;
2522 int eqn;
2523 int nirq;
2524
2525 err = mlx5_vector2eqn(priv->mdev, i,
2526 &eqn, &nirq);
2527
2528 /* error here is non-fatal */
2529 if (err != 0)
2530 continue;
2531
2532 irq = priv->mdev->priv.msix_arr[nirq].vector;
2533 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base +
2534 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus;
2535
2536 CPU_ZERO(&cpuset);
2537 CPU_SET(cpu, &cpuset);
2538 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset);
2539 }
2540 }
2541
2542 for (j = 0; j < priv->params.num_channels; j++) {
2543 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2544 if (err)
2545 goto err_close_channels;
2546 }
2547 free(cparam, M_MLX5EN);
2548 return (0);
2549
2550 err_close_channels:
2551 while (i--) {
2552 mlx5e_close_channel(&priv->channel[i]);
2553 mlx5e_close_channel_wait(&priv->channel[i]);
2554 }
2555 free(cparam, M_MLX5EN);
2556 return (err);
2557 }
2558
2559 static void
mlx5e_close_channels(struct mlx5e_priv * priv)2560 mlx5e_close_channels(struct mlx5e_priv *priv)
2561 {
2562 int i;
2563
2564 for (i = 0; i < priv->params.num_channels; i++)
2565 mlx5e_close_channel(&priv->channel[i]);
2566 for (i = 0; i < priv->params.num_channels; i++)
2567 mlx5e_close_channel_wait(&priv->channel[i]);
2568 }
2569
2570 static int
mlx5e_refresh_sq_params(struct mlx5e_priv * priv,struct mlx5e_sq * sq)2571 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2572 {
2573
2574 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2575 uint8_t cq_mode;
2576
2577 switch (priv->params.tx_cq_moderation_mode) {
2578 case 0:
2579 case 2:
2580 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2581 break;
2582 default:
2583 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2584 break;
2585 }
2586
2587 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2588 priv->params.tx_cq_moderation_usec,
2589 priv->params.tx_cq_moderation_pkts,
2590 cq_mode));
2591 }
2592
2593 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2594 priv->params.tx_cq_moderation_usec,
2595 priv->params.tx_cq_moderation_pkts));
2596 }
2597
2598 static int
mlx5e_refresh_rq_params(struct mlx5e_priv * priv,struct mlx5e_rq * rq)2599 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2600 {
2601
2602 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2603 uint8_t cq_mode;
2604 uint8_t dim_mode;
2605 int retval;
2606
2607 switch (priv->params.rx_cq_moderation_mode) {
2608 case 0:
2609 case 2:
2610 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2611 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2612 break;
2613 default:
2614 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2615 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2616 break;
2617 }
2618
2619 /* tear down dynamic interrupt moderation */
2620 mtx_lock(&rq->mtx);
2621 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2622 mtx_unlock(&rq->mtx);
2623
2624 /* wait for dynamic interrupt moderation work task, if any */
2625 cancel_work_sync(&rq->dim.work);
2626
2627 if (priv->params.rx_cq_moderation_mode >= 2) {
2628 struct net_dim_cq_moder curr;
2629
2630 mlx5e_get_default_profile(priv, dim_mode, &curr);
2631
2632 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2633 curr.usec, curr.pkts, cq_mode);
2634
2635 /* set dynamic interrupt moderation mode and zero defaults */
2636 mtx_lock(&rq->mtx);
2637 rq->dim.mode = dim_mode;
2638 rq->dim.state = 0;
2639 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2640 mtx_unlock(&rq->mtx);
2641 } else {
2642 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2643 priv->params.rx_cq_moderation_usec,
2644 priv->params.rx_cq_moderation_pkts,
2645 cq_mode);
2646 }
2647 return (retval);
2648 }
2649
2650 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2651 priv->params.rx_cq_moderation_usec,
2652 priv->params.rx_cq_moderation_pkts));
2653 }
2654
2655 static int
mlx5e_refresh_channel_params_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)2656 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2657 {
2658 int err;
2659 int i;
2660
2661 err = mlx5e_refresh_rq_params(priv, &c->rq);
2662 if (err)
2663 goto done;
2664
2665 for (i = 0; i != priv->num_tc; i++) {
2666 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2667 if (err)
2668 goto done;
2669 }
2670 done:
2671 return (err);
2672 }
2673
2674 int
mlx5e_refresh_channel_params(struct mlx5e_priv * priv)2675 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2676 {
2677 int i;
2678
2679 /* check if channels are closed */
2680 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2681 return (EINVAL);
2682
2683 for (i = 0; i < priv->params.num_channels; i++) {
2684 int err;
2685
2686 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2687 if (err)
2688 return (err);
2689 }
2690 return (0);
2691 }
2692
2693 static int
mlx5e_open_tis(struct mlx5e_priv * priv,int tc)2694 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2695 {
2696 struct mlx5_core_dev *mdev = priv->mdev;
2697 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2698 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2699
2700 memset(in, 0, sizeof(in));
2701
2702 MLX5_SET(tisc, tisc, prio, tc);
2703 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2704
2705 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2706 }
2707
2708 static void
mlx5e_close_tis(struct mlx5e_priv * priv,int tc)2709 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2710 {
2711 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2712 }
2713
2714 static int
mlx5e_open_tises(struct mlx5e_priv * priv)2715 mlx5e_open_tises(struct mlx5e_priv *priv)
2716 {
2717 int num_tc = priv->num_tc;
2718 int err;
2719 int tc;
2720
2721 for (tc = 0; tc < num_tc; tc++) {
2722 err = mlx5e_open_tis(priv, tc);
2723 if (err)
2724 goto err_close_tises;
2725 }
2726
2727 return (0);
2728
2729 err_close_tises:
2730 for (tc--; tc >= 0; tc--)
2731 mlx5e_close_tis(priv, tc);
2732
2733 return (err);
2734 }
2735
2736 static void
mlx5e_close_tises(struct mlx5e_priv * priv)2737 mlx5e_close_tises(struct mlx5e_priv *priv)
2738 {
2739 int num_tc = priv->num_tc;
2740 int tc;
2741
2742 for (tc = 0; tc < num_tc; tc++)
2743 mlx5e_close_tis(priv, tc);
2744 }
2745
2746 static int
mlx5e_open_default_rqt(struct mlx5e_priv * priv,u32 * prqtn,int sz)2747 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz)
2748 {
2749 u32 *in;
2750 void *rqtc;
2751 int inlen;
2752 int err;
2753 int i;
2754
2755 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2756 in = mlx5_vzalloc(inlen);
2757 if (in == NULL)
2758 return (-ENOMEM);
2759 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2760
2761 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2762 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2763
2764 for (i = 0; i != sz; i++)
2765 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2766
2767 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn);
2768 kvfree(in);
2769
2770 return (err);
2771 }
2772
2773 static int
mlx5e_open_rqts(struct mlx5e_priv * priv)2774 mlx5e_open_rqts(struct mlx5e_priv *priv)
2775 {
2776 int err;
2777 int i;
2778
2779 err = mlx5e_open_default_rqt(priv, &priv->rqtn,
2780 1 << priv->params.rx_hash_log_tbl_sz);
2781 if (err)
2782 goto err_default;
2783
2784 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2785 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1);
2786 if (err)
2787 goto err_channel;
2788 }
2789 return (0);
2790
2791 err_channel:
2792 while (i--)
2793 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn);
2794
2795 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn);
2796
2797 err_default:
2798 return (err);
2799 }
2800
2801 static void
mlx5e_close_rqts(struct mlx5e_priv * priv)2802 mlx5e_close_rqts(struct mlx5e_priv *priv)
2803 {
2804 int i;
2805
2806 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++)
2807 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn);
2808
2809 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn);
2810 }
2811
2812 static int
mlx5e_activate_rqt(struct mlx5e_priv * priv)2813 mlx5e_activate_rqt(struct mlx5e_priv *priv)
2814 {
2815 u32 *in;
2816 void *rqtc;
2817 int inlen;
2818 int err;
2819 int sz;
2820 int i;
2821
2822 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2823
2824 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2825 in = mlx5_vzalloc(inlen);
2826 if (in == NULL)
2827 return (-ENOMEM);
2828
2829 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2830
2831 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2832 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2833
2834 for (i = 0; i != sz; i++) {
2835 int ix;
2836 #ifdef RSS
2837 ix = rss_get_indirection_to_bucket(i);
2838 #else
2839 ix = i;
2840 #endif
2841 /* ensure we don't overflow */
2842 ix %= priv->params.num_channels;
2843
2844 /* apply receive side scaling stride, if any */
2845 ix -= ix % (int)priv->params.channels_rsss;
2846
2847 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2848 }
2849
2850 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2851 if (err)
2852 goto err_modify;
2853
2854 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32);
2855
2856 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
2857
2858 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2859 int ix;
2860 #ifdef RSS
2861 ix = rss_get_indirection_to_bucket(i);
2862 #else
2863 ix = i;
2864 #endif
2865 /* ensure we don't overflow */
2866 ix %= priv->params.num_channels;
2867
2868 /* apply receive side scaling stride, if any */
2869 ix -= ix % (int)priv->params.channels_rsss;
2870
2871 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn);
2872
2873 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2874 if (err)
2875 goto err_modify;
2876 }
2877
2878 err_modify:
2879 kvfree(in);
2880 return (err);
2881 }
2882
2883 static int
mlx5e_deactivate_rqt(struct mlx5e_priv * priv)2884 mlx5e_deactivate_rqt(struct mlx5e_priv *priv)
2885 {
2886 u32 *in;
2887 void *rqtc;
2888 int inlen;
2889 int err;
2890 int sz;
2891 int i;
2892
2893 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2894
2895 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2896 in = mlx5_vzalloc(inlen);
2897 if (in == NULL)
2898 return (-ENOMEM);
2899
2900 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2901
2902 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2903 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2904
2905 for (i = 0; i != sz; i++)
2906 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2907
2908 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2909 if (err)
2910 goto err_modify;
2911
2912 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32);
2913
2914 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
2915
2916 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2917 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn);
2918
2919 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2920 if (err)
2921 goto err_modify;
2922 }
2923
2924 err_modify:
2925 kvfree(in);
2926 return (err);
2927 }
2928
2929 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */
2930
2931 static void
mlx5e_get_rss_key(void * key_ptr)2932 mlx5e_get_rss_key(void *key_ptr)
2933 {
2934 #ifdef RSS
2935 rss_getkey(key_ptr);
2936 #else
2937 static const u32 rsskey[] = {
2938 cpu_to_be32(0xD181C62C),
2939 cpu_to_be32(0xF7F4DB5B),
2940 cpu_to_be32(0x1983A2FC),
2941 cpu_to_be32(0x943E1ADB),
2942 cpu_to_be32(0xD9389E6B),
2943 cpu_to_be32(0xD1039C2C),
2944 cpu_to_be32(0xA74499AD),
2945 cpu_to_be32(0x593D56D9),
2946 cpu_to_be32(0xF3253C06),
2947 cpu_to_be32(0x2ADC1FFC),
2948 };
2949 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE);
2950 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE);
2951 #endif
2952 }
2953
2954 static void
mlx5e_build_tir_ctx(struct mlx5e_priv * priv,u32 * tirc,int tt,bool inner_vxlan)2955 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan)
2956 {
2957 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2958 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
2959 void *hfs = inner_vxlan ? hfsi : hfso;
2960 __be32 *hkey;
2961
2962 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2963
2964 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2965
2966 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2967 MLX5_HASH_FIELD_SEL_DST_IP)
2968
2969 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2970 MLX5_HASH_FIELD_SEL_DST_IP |\
2971 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2972 MLX5_HASH_FIELD_SEL_L4_DPORT)
2973
2974 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2975 MLX5_HASH_FIELD_SEL_DST_IP |\
2976 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2977
2978 if (priv->params.hw_lro_en) {
2979 MLX5_SET(tirc, tirc, lro_enable_mask,
2980 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2981 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2982 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2983 (priv->params.lro_wqe_sz -
2984 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2985 /* TODO: add the option to choose timer value dynamically */
2986 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2987 MLX5_CAP_ETH(priv->mdev,
2988 lro_timer_supported_periods[2]));
2989 }
2990
2991 if (inner_vxlan)
2992 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
2993
2994 /*
2995 * All packets must go through the indirection table, RQT,
2996 * because it is not possible to modify the RQN of the TIR
2997 * for direct dispatchment after it is created, typically
2998 * when the link goes up and down.
2999 */
3000 MLX5_SET(tirc, tirc, disp_type,
3001 MLX5_TIRC_DISP_TYPE_INDIRECT);
3002 MLX5_SET(tirc, tirc, indirect_table,
3003 priv->rqtn);
3004 MLX5_SET(tirc, tirc, rx_hash_fn,
3005 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
3006 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
3007
3008 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >=
3009 MLX5E_RSS_KEY_SIZE);
3010 #ifdef RSS
3011 /*
3012 * The FreeBSD RSS implementation does currently not
3013 * support symmetric Toeplitz hashes:
3014 */
3015 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
3016 #else
3017 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
3018 #endif
3019 mlx5e_get_rss_key(hkey);
3020
3021 switch (tt) {
3022 case MLX5E_TT_IPV4_TCP:
3023 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3024 MLX5_L3_PROT_TYPE_IPV4);
3025 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3026 MLX5_L4_PROT_TYPE_TCP);
3027 #ifdef RSS
3028 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
3029 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3030 MLX5_HASH_IP);
3031 } else
3032 #endif
3033 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3034 MLX5_HASH_ALL);
3035 break;
3036
3037 case MLX5E_TT_IPV6_TCP:
3038 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3039 MLX5_L3_PROT_TYPE_IPV6);
3040 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3041 MLX5_L4_PROT_TYPE_TCP);
3042 #ifdef RSS
3043 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
3044 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3045 MLX5_HASH_IP);
3046 } else
3047 #endif
3048 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3049 MLX5_HASH_ALL);
3050 break;
3051
3052 case MLX5E_TT_IPV4_UDP:
3053 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3054 MLX5_L3_PROT_TYPE_IPV4);
3055 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3056 MLX5_L4_PROT_TYPE_UDP);
3057 #ifdef RSS
3058 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
3059 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3060 MLX5_HASH_IP);
3061 } else
3062 #endif
3063 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3064 MLX5_HASH_ALL);
3065 break;
3066
3067 case MLX5E_TT_IPV6_UDP:
3068 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3069 MLX5_L3_PROT_TYPE_IPV6);
3070 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3071 MLX5_L4_PROT_TYPE_UDP);
3072 #ifdef RSS
3073 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
3074 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3075 MLX5_HASH_IP);
3076 } else
3077 #endif
3078 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3079 MLX5_HASH_ALL);
3080 break;
3081
3082 case MLX5E_TT_IPV4_IPSEC_AH:
3083 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3084 MLX5_L3_PROT_TYPE_IPV4);
3085 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3086 MLX5_HASH_IP_IPSEC_SPI);
3087 break;
3088
3089 case MLX5E_TT_IPV6_IPSEC_AH:
3090 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3091 MLX5_L3_PROT_TYPE_IPV6);
3092 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3093 MLX5_HASH_IP_IPSEC_SPI);
3094 break;
3095
3096 case MLX5E_TT_IPV4_IPSEC_ESP:
3097 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3098 MLX5_L3_PROT_TYPE_IPV4);
3099 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3100 MLX5_HASH_IP_IPSEC_SPI);
3101 break;
3102
3103 case MLX5E_TT_IPV6_IPSEC_ESP:
3104 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3105 MLX5_L3_PROT_TYPE_IPV6);
3106 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3107 MLX5_HASH_IP_IPSEC_SPI);
3108 break;
3109
3110 case MLX5E_TT_IPV4:
3111 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3112 MLX5_L3_PROT_TYPE_IPV4);
3113 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3114 MLX5_HASH_IP);
3115 break;
3116
3117 case MLX5E_TT_IPV6:
3118 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3119 MLX5_L3_PROT_TYPE_IPV6);
3120 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3121 MLX5_HASH_IP);
3122 break;
3123
3124 default:
3125 break;
3126 }
3127 }
3128
3129 static int
mlx5e_open_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)3130 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3131 {
3132 struct mlx5_core_dev *mdev = priv->mdev;
3133 u32 *in;
3134 void *tirc;
3135 int inlen;
3136 int err;
3137
3138 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3139 in = mlx5_vzalloc(inlen);
3140 if (in == NULL)
3141 return (-ENOMEM);
3142 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
3143
3144 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan);
3145
3146 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ?
3147 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]);
3148
3149 kvfree(in);
3150
3151 return (err);
3152 }
3153
3154 static void
mlx5e_close_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)3155 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3156 {
3157 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ?
3158 priv->tirn_inner_vxlan[tt] : priv->tirn[tt]);
3159 }
3160
3161 static int
mlx5e_open_tirs(struct mlx5e_priv * priv)3162 mlx5e_open_tirs(struct mlx5e_priv *priv)
3163 {
3164 int err;
3165 int i;
3166
3167 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) {
3168 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false);
3169 if (err)
3170 goto err_close_tirs;
3171 }
3172
3173 return (0);
3174
3175 err_close_tirs:
3176 for (i--; i >= 0; i--)
3177 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3178
3179 return (err);
3180 }
3181
3182 static void
mlx5e_close_tirs(struct mlx5e_priv * priv)3183 mlx5e_close_tirs(struct mlx5e_priv *priv)
3184 {
3185 int i;
3186
3187 for (i = 0; i != 2 * MLX5E_NUM_TT; i++)
3188 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3189 }
3190
3191 /*
3192 * SW MTU does not include headers,
3193 * HW MTU includes all headers and checksums.
3194 */
3195 static int
mlx5e_set_dev_port_mtu(struct ifnet * ifp,int sw_mtu)3196 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
3197 {
3198 struct mlx5e_priv *priv = ifp->if_softc;
3199 struct mlx5_core_dev *mdev = priv->mdev;
3200 int hw_mtu;
3201 int err;
3202
3203 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
3204
3205 err = mlx5_set_port_mtu(mdev, hw_mtu);
3206 if (err) {
3207 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
3208 sw_mtu, err);
3209 return (err);
3210 }
3211
3212 /* Update vport context MTU */
3213 err = mlx5_set_vport_mtu(mdev, hw_mtu);
3214 if (err) {
3215 mlx5_en_err(ifp,
3216 "Failed updating vport context with MTU size, err=%d\n",
3217 err);
3218 }
3219
3220 ifp->if_mtu = sw_mtu;
3221
3222 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3223 if (err || !hw_mtu) {
3224 /* fallback to port oper mtu */
3225 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3226 }
3227 if (err) {
3228 mlx5_en_err(ifp,
3229 "Query port MTU, after setting new MTU value, failed\n");
3230 return (err);
3231 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3232 err = -E2BIG,
3233 mlx5_en_err(ifp,
3234 "Port MTU %d is smaller than ifp mtu %d\n",
3235 hw_mtu, sw_mtu);
3236 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3237 err = -EINVAL;
3238 mlx5_en_err(ifp,
3239 "Port MTU %d is bigger than ifp mtu %d\n",
3240 hw_mtu, sw_mtu);
3241 }
3242 priv->params_ethtool.hw_mtu = hw_mtu;
3243
3244 /* compute MSB */
3245 while (hw_mtu & (hw_mtu - 1))
3246 hw_mtu &= (hw_mtu - 1);
3247 priv->params_ethtool.hw_mtu_msb = hw_mtu;
3248
3249 return (err);
3250 }
3251
3252 int
mlx5e_open_locked(struct ifnet * ifp)3253 mlx5e_open_locked(struct ifnet *ifp)
3254 {
3255 struct mlx5e_priv *priv = ifp->if_softc;
3256 int err;
3257 u16 set_id;
3258
3259 /* check if already opened */
3260 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3261 return (0);
3262
3263 #ifdef RSS
3264 if (rss_getnumbuckets() > priv->params.num_channels) {
3265 mlx5_en_info(ifp,
3266 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3267 rss_getnumbuckets(), priv->params.num_channels);
3268 }
3269 #endif
3270 err = mlx5e_open_tises(priv);
3271 if (err) {
3272 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3273 return (err);
3274 }
3275 err = mlx5_vport_alloc_q_counter(priv->mdev,
3276 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3277 if (err) {
3278 mlx5_en_err(priv->ifp,
3279 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3280 goto err_close_tises;
3281 }
3282 /* store counter set ID */
3283 priv->counter_set_id = set_id;
3284
3285 err = mlx5e_open_channels(priv);
3286 if (err) {
3287 mlx5_en_err(ifp,
3288 "mlx5e_open_channels failed, %d\n", err);
3289 goto err_dalloc_q_counter;
3290 }
3291 err = mlx5e_activate_rqt(priv);
3292 if (err) {
3293 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err);
3294 goto err_close_channels;
3295 }
3296
3297 set_bit(MLX5E_STATE_OPENED, &priv->state);
3298
3299 mlx5e_update_carrier(priv);
3300
3301 return (0);
3302
3303 err_close_channels:
3304 mlx5e_close_channels(priv);
3305
3306 err_dalloc_q_counter:
3307 mlx5_vport_dealloc_q_counter(priv->mdev,
3308 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3309
3310 err_close_tises:
3311 mlx5e_close_tises(priv);
3312
3313 return (err);
3314 }
3315
3316 static void
mlx5e_open(void * arg)3317 mlx5e_open(void *arg)
3318 {
3319 struct mlx5e_priv *priv = arg;
3320
3321 PRIV_LOCK(priv);
3322 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3323 mlx5_en_err(priv->ifp,
3324 "Setting port status to up failed\n");
3325
3326 mlx5e_open_locked(priv->ifp);
3327 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3328 PRIV_UNLOCK(priv);
3329 }
3330
3331 int
mlx5e_close_locked(struct ifnet * ifp)3332 mlx5e_close_locked(struct ifnet *ifp)
3333 {
3334 struct mlx5e_priv *priv = ifp->if_softc;
3335
3336 /* check if already closed */
3337 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3338 return (0);
3339
3340 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3341
3342 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3343
3344 mlx5e_deactivate_rqt(priv);
3345 mlx5e_close_channels(priv);
3346 mlx5_vport_dealloc_q_counter(priv->mdev,
3347 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3348 mlx5e_close_tises(priv);
3349
3350 return (0);
3351 }
3352
3353 static uint64_t
mlx5e_get_counter(struct ifnet * ifp,ift_counter cnt)3354 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3355 {
3356 struct mlx5e_priv *priv = ifp->if_softc;
3357 u64 retval;
3358
3359 /* PRIV_LOCK(priv); XXX not allowed */
3360 switch (cnt) {
3361 case IFCOUNTER_IPACKETS:
3362 retval = priv->stats.vport.rx_packets;
3363 break;
3364 case IFCOUNTER_IERRORS:
3365 retval = priv->stats.pport.in_range_len_errors +
3366 priv->stats.pport.out_of_range_len +
3367 priv->stats.pport.too_long_errors +
3368 priv->stats.pport.check_seq_err +
3369 priv->stats.pport.alignment_err;
3370 break;
3371 case IFCOUNTER_IQDROPS:
3372 retval = priv->stats.vport.rx_out_of_buffer;
3373 break;
3374 case IFCOUNTER_OPACKETS:
3375 retval = priv->stats.vport.tx_packets;
3376 break;
3377 case IFCOUNTER_OERRORS:
3378 retval = priv->stats.port_stats_debug.out_discards;
3379 break;
3380 case IFCOUNTER_IBYTES:
3381 retval = priv->stats.vport.rx_bytes;
3382 break;
3383 case IFCOUNTER_OBYTES:
3384 retval = priv->stats.vport.tx_bytes;
3385 break;
3386 case IFCOUNTER_IMCASTS:
3387 retval = priv->stats.vport.rx_multicast_packets;
3388 break;
3389 case IFCOUNTER_OMCASTS:
3390 retval = priv->stats.vport.tx_multicast_packets;
3391 break;
3392 case IFCOUNTER_OQDROPS:
3393 retval = priv->stats.vport.tx_queue_dropped;
3394 break;
3395 case IFCOUNTER_COLLISIONS:
3396 retval = priv->stats.pport.collisions;
3397 break;
3398 default:
3399 retval = if_get_counter_default(ifp, cnt);
3400 break;
3401 }
3402 /* PRIV_UNLOCK(priv); XXX not allowed */
3403 return (retval);
3404 }
3405
3406 static void
mlx5e_set_rx_mode(struct ifnet * ifp)3407 mlx5e_set_rx_mode(struct ifnet *ifp)
3408 {
3409 struct mlx5e_priv *priv = ifp->if_softc;
3410
3411 queue_work(priv->wq, &priv->set_rx_mode_work);
3412 }
3413
3414 static int
mlx5e_ioctl(struct ifnet * ifp,u_long command,caddr_t data)3415 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3416 {
3417 struct mlx5e_priv *priv;
3418 struct ifreq *ifr;
3419 struct ifdownreason *ifdr;
3420 struct ifi2creq i2c;
3421 struct ifrsskey *ifrk;
3422 struct ifrsshash *ifrh;
3423 int error = 0;
3424 int mask = 0;
3425 int size_read = 0;
3426 int module_status;
3427 int module_num;
3428 int max_mtu;
3429 uint8_t read_addr;
3430
3431 priv = ifp->if_softc;
3432
3433 /* check if detaching */
3434 if (priv == NULL || priv->gone != 0)
3435 return (ENXIO);
3436
3437 switch (command) {
3438 case SIOCSIFMTU:
3439 ifr = (struct ifreq *)data;
3440
3441 PRIV_LOCK(priv);
3442 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3443
3444 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3445 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3446 int was_opened;
3447
3448 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3449 if (was_opened)
3450 mlx5e_close_locked(ifp);
3451
3452 /* set new MTU */
3453 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3454
3455 if (was_opened)
3456 mlx5e_open_locked(ifp);
3457 } else {
3458 error = EINVAL;
3459 mlx5_en_err(ifp,
3460 "Invalid MTU value. Min val: %d, Max val: %d\n",
3461 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3462 }
3463 PRIV_UNLOCK(priv);
3464 break;
3465 case SIOCSIFFLAGS:
3466 if ((ifp->if_flags & IFF_UP) &&
3467 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3468 mlx5e_set_rx_mode(ifp);
3469 break;
3470 }
3471 PRIV_LOCK(priv);
3472 if (ifp->if_flags & IFF_UP) {
3473 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3474 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3475 mlx5e_open_locked(ifp);
3476 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3477 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3478 }
3479 } else {
3480 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3481 mlx5_set_port_status(priv->mdev,
3482 MLX5_PORT_DOWN);
3483 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3484 mlx5e_close_locked(ifp);
3485 mlx5e_update_carrier(priv);
3486 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3487 }
3488 }
3489 PRIV_UNLOCK(priv);
3490 break;
3491 case SIOCADDMULTI:
3492 case SIOCDELMULTI:
3493 mlx5e_set_rx_mode(ifp);
3494 break;
3495 case SIOCSIFMEDIA:
3496 case SIOCGIFMEDIA:
3497 case SIOCGIFXMEDIA:
3498 ifr = (struct ifreq *)data;
3499 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3500 break;
3501 case SIOCSIFCAP:
3502 ifr = (struct ifreq *)data;
3503 PRIV_LOCK(priv);
3504 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3505
3506 if (mask & IFCAP_TXCSUM) {
3507 ifp->if_capenable ^= IFCAP_TXCSUM;
3508 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3509
3510 if (IFCAP_TSO4 & ifp->if_capenable &&
3511 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3512 mask &= ~IFCAP_TSO4;
3513 ifp->if_capenable &= ~IFCAP_TSO4;
3514 ifp->if_hwassist &= ~CSUM_IP_TSO;
3515 mlx5_en_err(ifp,
3516 "tso4 disabled due to -txcsum.\n");
3517 }
3518 }
3519 if (mask & IFCAP_TXCSUM_IPV6) {
3520 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3521 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3522
3523 if (IFCAP_TSO6 & ifp->if_capenable &&
3524 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3525 mask &= ~IFCAP_TSO6;
3526 ifp->if_capenable &= ~IFCAP_TSO6;
3527 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3528 mlx5_en_err(ifp,
3529 "tso6 disabled due to -txcsum6.\n");
3530 }
3531 }
3532 if (mask & IFCAP_MEXTPG)
3533 ifp->if_capenable ^= IFCAP_MEXTPG;
3534 if (mask & IFCAP_TXTLS4)
3535 ifp->if_capenable ^= IFCAP_TXTLS4;
3536 if (mask & IFCAP_TXTLS6)
3537 ifp->if_capenable ^= IFCAP_TXTLS6;
3538 #ifdef RATELIMIT
3539 if (mask & IFCAP_TXTLS_RTLMT)
3540 ifp->if_capenable ^= IFCAP_TXTLS_RTLMT;
3541 #endif
3542 if (mask & IFCAP_RXCSUM)
3543 ifp->if_capenable ^= IFCAP_RXCSUM;
3544 if (mask & IFCAP_RXCSUM_IPV6)
3545 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3546 if (mask & IFCAP_TSO4) {
3547 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3548 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3549 mlx5_en_err(ifp, "enable txcsum first.\n");
3550 error = EAGAIN;
3551 goto out;
3552 }
3553 ifp->if_capenable ^= IFCAP_TSO4;
3554 ifp->if_hwassist ^= CSUM_IP_TSO;
3555 }
3556 if (mask & IFCAP_TSO6) {
3557 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3558 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3559 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3560 error = EAGAIN;
3561 goto out;
3562 }
3563 ifp->if_capenable ^= IFCAP_TSO6;
3564 ifp->if_hwassist ^= CSUM_IP6_TSO;
3565 }
3566 if (mask & IFCAP_VLAN_HWTSO)
3567 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3568 if (mask & IFCAP_VLAN_HWFILTER) {
3569 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3570 mlx5e_disable_vlan_filter(priv);
3571 else
3572 mlx5e_enable_vlan_filter(priv);
3573
3574 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3575 }
3576 if (mask & IFCAP_VLAN_HWTAGGING)
3577 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3578 if (mask & IFCAP_WOL_MAGIC)
3579 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3580 if (mask & IFCAP_VXLAN_HWCSUM) {
3581 const bool was_enabled =
3582 (ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0;
3583 if (was_enabled)
3584 mlx5e_del_all_vxlan_rules(priv);
3585 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM;
3586 ifp->if_hwassist ^= CSUM_INNER_IP | CSUM_INNER_IP_UDP |
3587 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP |
3588 CSUM_INNER_IP6_TCP;
3589 if (!was_enabled) {
3590 int err = mlx5e_add_all_vxlan_rules(priv);
3591 if (err != 0) {
3592 mlx5_en_err(ifp,
3593 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err);
3594 }
3595 }
3596 }
3597 if (mask & IFCAP_VXLAN_HWTSO) {
3598 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO;
3599 ifp->if_hwassist ^= CSUM_INNER_IP_TSO |
3600 CSUM_INNER_IP6_TSO;
3601 }
3602
3603 VLAN_CAPABILITIES(ifp);
3604 /* turn off LRO means also turn of HW LRO - if it's on */
3605 if (mask & IFCAP_LRO) {
3606 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3607 bool need_restart = false;
3608
3609 ifp->if_capenable ^= IFCAP_LRO;
3610
3611 /* figure out if updating HW LRO is needed */
3612 if (!(ifp->if_capenable & IFCAP_LRO)) {
3613 if (priv->params.hw_lro_en) {
3614 priv->params.hw_lro_en = false;
3615 need_restart = true;
3616 }
3617 } else {
3618 if (priv->params.hw_lro_en == false &&
3619 priv->params_ethtool.hw_lro != 0) {
3620 priv->params.hw_lro_en = true;
3621 need_restart = true;
3622 }
3623 }
3624 if (was_opened && need_restart) {
3625 mlx5e_close_locked(ifp);
3626 mlx5e_open_locked(ifp);
3627 }
3628 }
3629 if (mask & IFCAP_HWRXTSTMP) {
3630 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3631 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3632 if (priv->clbr_done == 0)
3633 mlx5e_reset_calibration_callout(priv);
3634 } else {
3635 callout_drain(&priv->tstmp_clbr);
3636 priv->clbr_done = 0;
3637 }
3638 }
3639 out:
3640 PRIV_UNLOCK(priv);
3641 break;
3642
3643 case SIOCGI2C:
3644 ifr = (struct ifreq *)data;
3645
3646 /*
3647 * Copy from the user-space address ifr_data to the
3648 * kernel-space address i2c
3649 */
3650 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3651 if (error)
3652 break;
3653
3654 if (i2c.len > sizeof(i2c.data)) {
3655 error = EINVAL;
3656 break;
3657 }
3658
3659 PRIV_LOCK(priv);
3660 /* Get module_num which is required for the query_eeprom */
3661 error = mlx5_query_module_num(priv->mdev, &module_num);
3662 if (error) {
3663 mlx5_en_err(ifp,
3664 "Query module num failed, eeprom reading is not supported\n");
3665 error = EINVAL;
3666 goto err_i2c;
3667 }
3668 /* Check if module is present before doing an access */
3669 module_status = mlx5_query_module_status(priv->mdev, module_num);
3670 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3671 error = EINVAL;
3672 goto err_i2c;
3673 }
3674 /*
3675 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3676 * The internal conversion is as follows:
3677 */
3678 if (i2c.dev_addr == 0xA0)
3679 read_addr = MLX5_I2C_ADDR_LOW;
3680 else if (i2c.dev_addr == 0xA2)
3681 read_addr = MLX5_I2C_ADDR_HIGH;
3682 else {
3683 mlx5_en_err(ifp,
3684 "Query eeprom failed, Invalid Address: %X\n",
3685 i2c.dev_addr);
3686 error = EINVAL;
3687 goto err_i2c;
3688 }
3689 error = mlx5_query_eeprom(priv->mdev,
3690 read_addr, MLX5_EEPROM_LOW_PAGE,
3691 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3692 (uint32_t *)i2c.data, &size_read);
3693 if (error) {
3694 mlx5_en_err(ifp,
3695 "Query eeprom failed, eeprom reading is not supported\n");
3696 error = EINVAL;
3697 goto err_i2c;
3698 }
3699
3700 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3701 error = mlx5_query_eeprom(priv->mdev,
3702 read_addr, MLX5_EEPROM_LOW_PAGE,
3703 (uint32_t)(i2c.offset + size_read),
3704 (uint32_t)(i2c.len - size_read), module_num,
3705 (uint32_t *)(i2c.data + size_read), &size_read);
3706 }
3707 if (error) {
3708 mlx5_en_err(ifp,
3709 "Query eeprom failed, eeprom reading is not supported\n");
3710 error = EINVAL;
3711 goto err_i2c;
3712 }
3713
3714 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3715 err_i2c:
3716 PRIV_UNLOCK(priv);
3717 break;
3718 case SIOCGIFDOWNREASON:
3719 ifdr = (struct ifdownreason *)data;
3720 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3721 PRIV_LOCK(priv);
3722 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3723 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3724 PRIV_UNLOCK(priv);
3725 if (error == 0)
3726 ifdr->ifdr_reason = IFDR_REASON_MSG;
3727 break;
3728
3729 case SIOCGIFRSSKEY:
3730 ifrk = (struct ifrsskey *)data;
3731 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ;
3732 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE;
3733 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE);
3734 mlx5e_get_rss_key(ifrk->ifrk_key);
3735 break;
3736
3737 case SIOCGIFRSSHASH:
3738 ifrh = (struct ifrsshash *)data;
3739 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ;
3740 ifrh->ifrh_types =
3741 RSS_TYPE_IPV4 |
3742 RSS_TYPE_TCP_IPV4 |
3743 RSS_TYPE_UDP_IPV4 |
3744 RSS_TYPE_IPV6 |
3745 RSS_TYPE_TCP_IPV6 |
3746 RSS_TYPE_UDP_IPV6;
3747 break;
3748
3749 default:
3750 error = ether_ioctl(ifp, command, data);
3751 break;
3752 }
3753 return (error);
3754 }
3755
3756 static int
mlx5e_check_required_hca_cap(struct mlx5_core_dev * mdev)3757 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3758 {
3759 /*
3760 * TODO: uncoment once FW really sets all these bits if
3761 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3762 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3763 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3764 * -ENOTSUPP;
3765 */
3766
3767 /* TODO: add more must-to-have features */
3768
3769 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3770 return (-ENODEV);
3771
3772 return (0);
3773 }
3774
3775 static u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev * mdev)3776 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3777 {
3778 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3779 const int max_size = MLX5E_MAX_TX_INLINE;
3780 const int bf_buf_size =
3781 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3782 (sizeof(struct mlx5e_tx_wqe) - 2);
3783
3784 /* verify against driver limits */
3785 if (bf_buf_size > max_size)
3786 return (max_size);
3787 else if (bf_buf_size < min_size)
3788 return (min_size);
3789 else
3790 return (bf_buf_size);
3791 }
3792
3793 static int
mlx5e_build_ifp_priv(struct mlx5_core_dev * mdev,struct mlx5e_priv * priv,int num_comp_vectors)3794 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3795 struct mlx5e_priv *priv,
3796 int num_comp_vectors)
3797 {
3798 int err;
3799
3800 /*
3801 * TODO: Consider link speed for setting "log_sq_size",
3802 * "log_rq_size" and "cq_moderation_xxx":
3803 */
3804 priv->params.log_sq_size =
3805 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3806 priv->params.log_rq_size =
3807 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3808 priv->params.rx_cq_moderation_usec =
3809 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3810 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3811 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3812 priv->params.rx_cq_moderation_mode =
3813 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3814 priv->params.rx_cq_moderation_pkts =
3815 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3816 priv->params.tx_cq_moderation_usec =
3817 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3818 priv->params.tx_cq_moderation_pkts =
3819 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3820 priv->params.min_rx_wqes =
3821 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3822 priv->params.rx_hash_log_tbl_sz =
3823 (order_base_2(num_comp_vectors) >
3824 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3825 order_base_2(num_comp_vectors) :
3826 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3827 priv->params.num_tc = 1;
3828 priv->params.default_vlan_prio = 0;
3829 priv->counter_set_id = -1;
3830 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3831
3832 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3833 if (err)
3834 return (err);
3835
3836 /*
3837 * hw lro is currently defaulted to off. when it won't anymore we
3838 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3839 */
3840 priv->params.hw_lro_en = false;
3841 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3842
3843 /*
3844 * CQE zipping is currently defaulted to off. when it won't
3845 * anymore we will consider the HW capability:
3846 * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3847 */
3848 priv->params.cqe_zipping_en = false;
3849
3850 priv->mdev = mdev;
3851 priv->params.num_channels = num_comp_vectors;
3852 priv->params.channels_rsss = 1;
3853 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3854 priv->queue_mapping_channel_mask =
3855 roundup_pow_of_two(num_comp_vectors) - 1;
3856 priv->num_tc = priv->params.num_tc;
3857 priv->default_vlan_prio = priv->params.default_vlan_prio;
3858
3859 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3860 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3861 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3862
3863 return (0);
3864 }
3865
3866 static void
mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev * mdev,void * mkc)3867 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
3868 {
3869 bool ro_pci_enable =
3870 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev);
3871 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
3872 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
3873
3874 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
3875 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
3876 }
3877
3878 static int
mlx5e_create_mkey(struct mlx5e_priv * priv,u32 pdn,struct mlx5_core_mr * mkey)3879 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3880 struct mlx5_core_mr *mkey)
3881 {
3882 struct ifnet *ifp = priv->ifp;
3883 struct mlx5_core_dev *mdev = priv->mdev;
3884 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3885 void *mkc;
3886 u32 *in;
3887 int err;
3888
3889 in = mlx5_vzalloc(inlen);
3890 if (in == NULL) {
3891 mlx5_en_err(ifp, "failed to allocate inbox\n");
3892 return (-ENOMEM);
3893 }
3894
3895 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3896 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3897 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */
3898 MLX5_SET(mkc, mkc, lw, 1);
3899 MLX5_SET(mkc, mkc, lr, 1);
3900 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
3901 MLX5_SET(mkc, mkc, pd, pdn);
3902 MLX5_SET(mkc, mkc, length64, 1);
3903 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3904
3905 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3906 if (err)
3907 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3908 err);
3909
3910 kvfree(in);
3911 return (err);
3912 }
3913
3914 static const char *mlx5e_vport_stats_desc[] = {
3915 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3916 };
3917
3918 static const char *mlx5e_pport_stats_desc[] = {
3919 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3920 };
3921
3922 static int
mlx5e_priv_static_init(struct mlx5e_priv * priv,struct mlx5_core_dev * mdev,const uint32_t channels)3923 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
3924 const uint32_t channels)
3925 {
3926 uint32_t x;
3927 int err;
3928
3929 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3930 sx_init(&priv->state_lock, "mlx5state");
3931 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3932 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3933 for (x = 0; x != channels; x++)
3934 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3935
3936 for (x = 0; x != channels; x++) {
3937 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false);
3938 if (err)
3939 goto err_alloc_bfreg;
3940 }
3941 return (0);
3942
3943 err_alloc_bfreg:
3944 while (x--)
3945 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
3946
3947 for (x = 0; x != channels; x++)
3948 mlx5e_chan_static_destroy(&priv->channel[x]);
3949 callout_drain(&priv->watchdog);
3950 mtx_destroy(&priv->async_events_mtx);
3951 sx_destroy(&priv->state_lock);
3952 return (err);
3953 }
3954
3955 static void
mlx5e_priv_static_destroy(struct mlx5e_priv * priv,struct mlx5_core_dev * mdev,const uint32_t channels)3956 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
3957 const uint32_t channels)
3958 {
3959 uint32_t x;
3960
3961 for (x = 0; x != channels; x++)
3962 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
3963 for (x = 0; x != channels; x++)
3964 mlx5e_chan_static_destroy(&priv->channel[x]);
3965 callout_drain(&priv->watchdog);
3966 mtx_destroy(&priv->async_events_mtx);
3967 sx_destroy(&priv->state_lock);
3968 }
3969
3970 static int
sysctl_firmware(SYSCTL_HANDLER_ARGS)3971 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3972 {
3973 /*
3974 * %d.%d%.d the string format.
3975 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3976 * We need at most 5 chars to store that.
3977 * It also has: two "." and NULL at the end, which means we need 18
3978 * (5*3 + 3) chars at most.
3979 */
3980 char fw[18];
3981 struct mlx5e_priv *priv = arg1;
3982 int error;
3983
3984 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3985 fw_rev_sub(priv->mdev));
3986 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3987 return (error);
3988 }
3989
3990 static void
mlx5e_disable_tx_dma(struct mlx5e_channel * ch)3991 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3992 {
3993 int i;
3994
3995 for (i = 0; i < ch->priv->num_tc; i++)
3996 mlx5e_drain_sq(&ch->sq[i]);
3997 }
3998
3999 static void
mlx5e_reset_sq_doorbell_record(struct mlx5e_sq * sq)4000 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
4001 {
4002
4003 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
4004 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
4005 mlx5e_tx_notify_hw(sq, true);
4006 }
4007
4008 void
mlx5e_resume_sq(struct mlx5e_sq * sq)4009 mlx5e_resume_sq(struct mlx5e_sq *sq)
4010 {
4011 int err;
4012
4013 /* check if already enabled */
4014 if (READ_ONCE(sq->running) != 0)
4015 return;
4016
4017 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
4018 MLX5_SQC_STATE_RST);
4019 if (err != 0) {
4020 mlx5_en_err(sq->ifp,
4021 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
4022 }
4023
4024 sq->cc = 0;
4025 sq->pc = 0;
4026
4027 /* reset doorbell prior to moving from RST to RDY */
4028 mlx5e_reset_sq_doorbell_record(sq);
4029
4030 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
4031 MLX5_SQC_STATE_RDY);
4032 if (err != 0) {
4033 mlx5_en_err(sq->ifp,
4034 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
4035 }
4036
4037 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
4038 WRITE_ONCE(sq->running, 1);
4039 }
4040
4041 static void
mlx5e_enable_tx_dma(struct mlx5e_channel * ch)4042 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
4043 {
4044 int i;
4045
4046 for (i = 0; i < ch->priv->num_tc; i++)
4047 mlx5e_resume_sq(&ch->sq[i]);
4048 }
4049
4050 static void
mlx5e_disable_rx_dma(struct mlx5e_channel * ch)4051 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
4052 {
4053 struct mlx5e_rq *rq = &ch->rq;
4054 struct epoch_tracker et;
4055 int err;
4056
4057 mtx_lock(&rq->mtx);
4058 rq->enabled = 0;
4059 callout_stop(&rq->watchdog);
4060 mtx_unlock(&rq->mtx);
4061
4062 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
4063 if (err != 0) {
4064 mlx5_en_err(rq->ifp,
4065 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
4066 }
4067
4068 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
4069 msleep(1);
4070 NET_EPOCH_ENTER(et);
4071 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4072 NET_EPOCH_EXIT(et);
4073 }
4074
4075 /*
4076 * Transitioning into RST state will allow the FW to track less ERR state queues,
4077 * thus reducing the recv queue flushing time
4078 */
4079 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
4080 if (err != 0) {
4081 mlx5_en_err(rq->ifp,
4082 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
4083 }
4084 }
4085
4086 static void
mlx5e_enable_rx_dma(struct mlx5e_channel * ch)4087 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
4088 {
4089 struct mlx5e_rq *rq = &ch->rq;
4090 struct epoch_tracker et;
4091 int err;
4092
4093 rq->wq.wqe_ctr = 0;
4094 mlx5_wq_ll_update_db_record(&rq->wq);
4095 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
4096 if (err != 0) {
4097 mlx5_en_err(rq->ifp,
4098 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
4099 }
4100
4101 rq->enabled = 1;
4102
4103 NET_EPOCH_ENTER(et);
4104 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4105 NET_EPOCH_EXIT(et);
4106 }
4107
4108 void
mlx5e_modify_tx_dma(struct mlx5e_priv * priv,uint8_t value)4109 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
4110 {
4111 int i;
4112
4113 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4114 return;
4115
4116 for (i = 0; i < priv->params.num_channels; i++) {
4117 if (value)
4118 mlx5e_disable_tx_dma(&priv->channel[i]);
4119 else
4120 mlx5e_enable_tx_dma(&priv->channel[i]);
4121 }
4122 }
4123
4124 void
mlx5e_modify_rx_dma(struct mlx5e_priv * priv,uint8_t value)4125 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
4126 {
4127 int i;
4128
4129 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4130 return;
4131
4132 for (i = 0; i < priv->params.num_channels; i++) {
4133 if (value)
4134 mlx5e_disable_rx_dma(&priv->channel[i]);
4135 else
4136 mlx5e_enable_rx_dma(&priv->channel[i]);
4137 }
4138 }
4139
4140 static void
mlx5e_add_hw_stats(struct mlx5e_priv * priv)4141 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
4142 {
4143 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4144 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
4145 priv, 0, sysctl_firmware, "A", "HCA firmware version");
4146
4147 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4148 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
4149 "Board ID");
4150 }
4151
4152 static int
mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)4153 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
4154 {
4155 struct mlx5e_priv *priv = arg1;
4156 uint8_t temp[MLX5E_MAX_PRIORITY];
4157 uint32_t tx_pfc;
4158 int err;
4159 int i;
4160
4161 PRIV_LOCK(priv);
4162
4163 tx_pfc = priv->params.tx_priority_flow_control;
4164
4165 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
4166 temp[i] = (tx_pfc >> i) & 1;
4167
4168 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
4169 if (err || !req->newptr)
4170 goto done;
4171 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
4172 if (err)
4173 goto done;
4174
4175 priv->params.tx_priority_flow_control = 0;
4176
4177 /* range check input value */
4178 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
4179 if (temp[i] > 1) {
4180 err = ERANGE;
4181 goto done;
4182 }
4183 priv->params.tx_priority_flow_control |= (temp[i] << i);
4184 }
4185
4186 /* check if update is required */
4187 if (tx_pfc != priv->params.tx_priority_flow_control)
4188 err = -mlx5e_set_port_pfc(priv);
4189 done:
4190 if (err != 0)
4191 priv->params.tx_priority_flow_control= tx_pfc;
4192 PRIV_UNLOCK(priv);
4193
4194 return (err);
4195 }
4196
4197 static int
mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)4198 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
4199 {
4200 struct mlx5e_priv *priv = arg1;
4201 uint8_t temp[MLX5E_MAX_PRIORITY];
4202 uint32_t rx_pfc;
4203 int err;
4204 int i;
4205
4206 PRIV_LOCK(priv);
4207
4208 rx_pfc = priv->params.rx_priority_flow_control;
4209
4210 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
4211 temp[i] = (rx_pfc >> i) & 1;
4212
4213 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
4214 if (err || !req->newptr)
4215 goto done;
4216 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
4217 if (err)
4218 goto done;
4219
4220 priv->params.rx_priority_flow_control = 0;
4221
4222 /* range check input value */
4223 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
4224 if (temp[i] > 1) {
4225 err = ERANGE;
4226 goto done;
4227 }
4228 priv->params.rx_priority_flow_control |= (temp[i] << i);
4229 }
4230
4231 /* check if update is required */
4232 if (rx_pfc != priv->params.rx_priority_flow_control) {
4233 err = -mlx5e_set_port_pfc(priv);
4234 if (err == 0 && priv->sw_is_port_buf_owner)
4235 err = mlx5e_update_buf_lossy(priv);
4236 }
4237 done:
4238 if (err != 0)
4239 priv->params.rx_priority_flow_control= rx_pfc;
4240 PRIV_UNLOCK(priv);
4241
4242 return (err);
4243 }
4244
4245 static void
mlx5e_setup_pauseframes(struct mlx5e_priv * priv)4246 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
4247 {
4248 int error;
4249
4250 /* enable pauseframes by default */
4251 priv->params.tx_pauseframe_control = 1;
4252 priv->params.rx_pauseframe_control = 1;
4253
4254 /* disable ports flow control, PFC, by default */
4255 priv->params.tx_priority_flow_control = 0;
4256 priv->params.rx_priority_flow_control = 0;
4257
4258 /* register pauseframe SYSCTLs */
4259 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4260 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
4261 &priv->params.tx_pauseframe_control, 0,
4262 "Set to enable TX pause frames. Clear to disable.");
4263
4264 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4265 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
4266 &priv->params.rx_pauseframe_control, 0,
4267 "Set to enable RX pause frames. Clear to disable.");
4268
4269 /* register priority flow control, PFC, SYSCTLs */
4270 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4271 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4272 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4273 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4274
4275 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4276 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4277 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4278 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4279
4280 PRIV_LOCK(priv);
4281
4282 /* range check */
4283 priv->params.tx_pauseframe_control =
4284 priv->params.tx_pauseframe_control ? 1 : 0;
4285 priv->params.rx_pauseframe_control =
4286 priv->params.rx_pauseframe_control ? 1 : 0;
4287
4288 /* update firmware */
4289 error = mlx5e_set_port_pause_and_pfc(priv);
4290 if (error == -EINVAL) {
4291 mlx5_en_err(priv->ifp,
4292 "Global pauseframes must be disabled before enabling PFC.\n");
4293 priv->params.rx_priority_flow_control = 0;
4294 priv->params.tx_priority_flow_control = 0;
4295
4296 /* update firmware */
4297 (void) mlx5e_set_port_pause_and_pfc(priv);
4298 }
4299 PRIV_UNLOCK(priv);
4300 }
4301
4302 int
mlx5e_ul_snd_tag_alloc(struct ifnet * ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4303 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4304 union if_snd_tag_alloc_params *params,
4305 struct m_snd_tag **ppmt)
4306 {
4307 struct mlx5e_priv *priv;
4308 struct mlx5e_channel *pch;
4309
4310 priv = ifp->if_softc;
4311
4312 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4313 return (EOPNOTSUPP);
4314 } else {
4315 /* keep this code synced with mlx5e_select_queue() */
4316 u32 ch = priv->params.num_channels;
4317 #ifdef RSS
4318 u32 temp;
4319
4320 if (rss_hash2bucket(params->hdr.flowid,
4321 params->hdr.flowtype, &temp) == 0)
4322 ch = temp % ch;
4323 else
4324 #endif
4325 ch = (params->hdr.flowid % 128) % ch;
4326
4327 /*
4328 * NOTE: The channels array is only freed at detach
4329 * and it safe to return a pointer to the send tag
4330 * inside the channels structure as long as we
4331 * reference the priv.
4332 */
4333 pch = priv->channel + ch;
4334
4335 /* check if send queue is not running */
4336 if (unlikely(pch->sq[0].running == 0))
4337 return (ENXIO);
4338 m_snd_tag_ref(&pch->tag);
4339 *ppmt = &pch->tag;
4340 return (0);
4341 }
4342 }
4343
4344 int
mlx5e_ul_snd_tag_query(struct m_snd_tag * pmt,union if_snd_tag_query_params * params)4345 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4346 {
4347 struct mlx5e_channel *pch =
4348 container_of(pmt, struct mlx5e_channel, tag);
4349
4350 params->unlimited.max_rate = -1ULL;
4351 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4352 return (0);
4353 }
4354
4355 void
mlx5e_ul_snd_tag_free(struct m_snd_tag * pmt)4356 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4357 {
4358 struct mlx5e_channel *pch =
4359 container_of(pmt, struct mlx5e_channel, tag);
4360
4361 complete(&pch->completion);
4362 }
4363
4364 static int
mlx5e_snd_tag_alloc(struct ifnet * ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4365 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4366 union if_snd_tag_alloc_params *params,
4367 struct m_snd_tag **ppmt)
4368 {
4369
4370 switch (params->hdr.type) {
4371 #ifdef RATELIMIT
4372 case IF_SND_TAG_TYPE_RATE_LIMIT:
4373 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4374 #ifdef KERN_TLS
4375 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4376 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4377 #endif
4378 #endif
4379 case IF_SND_TAG_TYPE_UNLIMITED:
4380 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4381 #ifdef KERN_TLS
4382 case IF_SND_TAG_TYPE_TLS:
4383 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4384 #endif
4385 default:
4386 return (EOPNOTSUPP);
4387 }
4388 }
4389
4390 static int
mlx5e_snd_tag_modify(struct m_snd_tag * pmt,union if_snd_tag_modify_params * params)4391 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4392 {
4393
4394 switch (pmt->type) {
4395 #ifdef RATELIMIT
4396 case IF_SND_TAG_TYPE_RATE_LIMIT:
4397 return (mlx5e_rl_snd_tag_modify(pmt, params));
4398 #ifdef KERN_TLS
4399 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4400 return (mlx5e_tls_snd_tag_modify(pmt, params));
4401 #endif
4402 #endif
4403 case IF_SND_TAG_TYPE_UNLIMITED:
4404 #ifdef KERN_TLS
4405 case IF_SND_TAG_TYPE_TLS:
4406 #endif
4407 default:
4408 return (EOPNOTSUPP);
4409 }
4410 }
4411
4412 static int
mlx5e_snd_tag_query(struct m_snd_tag * pmt,union if_snd_tag_query_params * params)4413 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4414 {
4415
4416 switch (pmt->type) {
4417 #ifdef RATELIMIT
4418 case IF_SND_TAG_TYPE_RATE_LIMIT:
4419 return (mlx5e_rl_snd_tag_query(pmt, params));
4420 #ifdef KERN_TLS
4421 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4422 return (mlx5e_tls_snd_tag_query(pmt, params));
4423 #endif
4424 #endif
4425 case IF_SND_TAG_TYPE_UNLIMITED:
4426 return (mlx5e_ul_snd_tag_query(pmt, params));
4427 #ifdef KERN_TLS
4428 case IF_SND_TAG_TYPE_TLS:
4429 return (mlx5e_tls_snd_tag_query(pmt, params));
4430 #endif
4431 default:
4432 return (EOPNOTSUPP);
4433 }
4434 }
4435
4436 #ifdef RATELIMIT
4437 #define NUM_HDWR_RATES_MLX 13
4438 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4439 135375, /* 1,083,000 */
4440 180500, /* 1,444,000 */
4441 270750, /* 2,166,000 */
4442 361000, /* 2,888,000 */
4443 541500, /* 4,332,000 */
4444 721875, /* 5,775,000 */
4445 1082875, /* 8,663,000 */
4446 1443875, /* 11,551,000 */
4447 2165750, /* 17,326,000 */
4448 2887750, /* 23,102,000 */
4449 4331625, /* 34,653,000 */
4450 5775500, /* 46,204,000 */
4451 8663125 /* 69,305,000 */
4452 };
4453
4454 static void
mlx5e_ratelimit_query(struct ifnet * ifp __unused,struct if_ratelimit_query_results * q)4455 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4456 {
4457 /*
4458 * This function needs updating by the driver maintainer!
4459 * For the MLX card there are currently (ConectX-4?) 13
4460 * pre-set rates and others i.e. ConnectX-5, 6, 7??
4461 *
4462 * This will change based on later adapters
4463 * and this code should be updated to look at ifp
4464 * and figure out the specific adapter type
4465 * settings i.e. how many rates as well
4466 * as if they are fixed (as is shown here) or
4467 * if they are dynamic (example chelsio t4). Also if there
4468 * is a maximum number of flows that the adapter
4469 * can handle that too needs to be updated in
4470 * the max_flows field.
4471 */
4472 q->rate_table = adapter_rates_mlx;
4473 q->flags = RT_IS_FIXED_TABLE;
4474 q->max_flows = 0; /* mlx has no limit */
4475 q->number_of_rates = NUM_HDWR_RATES_MLX;
4476 q->min_segment_burst = 1;
4477 }
4478 #endif
4479
4480 static void
mlx5e_snd_tag_free(struct m_snd_tag * pmt)4481 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4482 {
4483
4484 switch (pmt->type) {
4485 #ifdef RATELIMIT
4486 case IF_SND_TAG_TYPE_RATE_LIMIT:
4487 mlx5e_rl_snd_tag_free(pmt);
4488 break;
4489 #ifdef KERN_TLS
4490 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4491 mlx5e_tls_snd_tag_free(pmt);
4492 break;
4493 #endif
4494 #endif
4495 case IF_SND_TAG_TYPE_UNLIMITED:
4496 mlx5e_ul_snd_tag_free(pmt);
4497 break;
4498 #ifdef KERN_TLS
4499 case IF_SND_TAG_TYPE_TLS:
4500 mlx5e_tls_snd_tag_free(pmt);
4501 break;
4502 #endif
4503 default:
4504 break;
4505 }
4506 }
4507
4508 static void
mlx5e_ifm_add(struct mlx5e_priv * priv,int type)4509 mlx5e_ifm_add(struct mlx5e_priv *priv, int type)
4510 {
4511 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL);
4512 ifmedia_add(&priv->media, type | IFM_ETHER |
4513 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4514 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL);
4515 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL);
4516 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL);
4517 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4518 IFM_ETH_RXPAUSE, 0, NULL);
4519 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4520 IFM_ETH_TXPAUSE, 0, NULL);
4521 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4522 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4523 }
4524
4525 static void *
mlx5e_create_ifp(struct mlx5_core_dev * mdev)4526 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4527 {
4528 struct ifnet *ifp;
4529 struct mlx5e_priv *priv;
4530 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4531 struct sysctl_oid_list *child;
4532 int ncv = mdev->priv.eq_table.num_comp_vectors;
4533 char unit[16];
4534 struct pfil_head_args pa;
4535 int err;
4536 u32 eth_proto_cap;
4537 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4538 bool ext;
4539 struct media media_entry = {};
4540
4541 if (mlx5e_check_required_hca_cap(mdev)) {
4542 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4543 return (NULL);
4544 }
4545
4546 /*
4547 * Try to allocate the priv and make room for worst-case
4548 * number of channel structures:
4549 */
4550 priv = malloc_domainset(sizeof(*priv) +
4551 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4552 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO);
4553
4554 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4555 if (ifp == NULL) {
4556 mlx5_core_err(mdev, "if_alloc() failed\n");
4557 goto err_free_priv;
4558 }
4559 /* setup all static fields */
4560 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) {
4561 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n");
4562 goto err_free_ifp;
4563 }
4564
4565 ifp->if_softc = priv;
4566 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4567 ifp->if_mtu = ETHERMTU;
4568 ifp->if_init = mlx5e_open;
4569 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
4570 IFF_KNOWSEPOCH;
4571 ifp->if_ioctl = mlx5e_ioctl;
4572 ifp->if_transmit = mlx5e_xmit;
4573 ifp->if_qflush = if_qflush;
4574 ifp->if_get_counter = mlx5e_get_counter;
4575 ifp->if_snd.ifq_maxlen = ifqmaxlen;
4576 /*
4577 * Set driver features
4578 */
4579 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4580 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4581 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4582 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4583 ifp->if_capabilities |= IFCAP_LRO;
4584 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4585 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4586 ifp->if_capabilities |= IFCAP_MEXTPG;
4587 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6;
4588 #ifdef RATELIMIT
4589 ifp->if_capabilities |= IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT;
4590 #endif
4591 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO;
4592 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4593 ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4594 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4595 ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4596 #ifdef RATELIMIT
4597 ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4598 #endif
4599 /* set TSO limits so that we don't have to drop TX packets */
4600 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4601 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4602 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4603
4604 ifp->if_capenable = ifp->if_capabilities;
4605 ifp->if_hwassist = 0;
4606 if (ifp->if_capenable & IFCAP_TSO)
4607 ifp->if_hwassist |= CSUM_TSO;
4608 if (ifp->if_capenable & IFCAP_TXCSUM)
4609 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4610 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4611 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4612 if (ifp->if_capabilities & IFCAP_VXLAN_HWCSUM)
4613 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
4614 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP |
4615 CSUM_ENCAP_VXLAN;
4616 if (ifp->if_capabilities & IFCAP_VXLAN_HWTSO)
4617 ifp->if_hwassist |= CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO;
4618
4619 /* ifnet sysctl tree */
4620 sysctl_ctx_init(&priv->sysctl_ctx);
4621 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4622 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4623 "MLX5 ethernet - interface name");
4624 if (priv->sysctl_ifnet == NULL) {
4625 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4626 goto err_free_sysctl;
4627 }
4628 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4629 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4630 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4631 "MLX5 ethernet - interface unit");
4632 if (priv->sysctl_ifnet == NULL) {
4633 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4634 goto err_free_sysctl;
4635 }
4636
4637 /* HW sysctl tree */
4638 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4639 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4640 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4641 "MLX5 ethernet dev hw");
4642 if (priv->sysctl_hw == NULL) {
4643 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4644 goto err_free_sysctl;
4645 }
4646
4647 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4648 if (err) {
4649 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4650 goto err_free_sysctl;
4651 }
4652
4653 /* reuse mlx5core's watchdog workqueue */
4654 priv->wq = mdev->priv.health.wq_watchdog;
4655
4656 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4657 if (err) {
4658 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4659 goto err_free_wq;
4660 }
4661 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4662 if (err) {
4663 mlx5_en_err(ifp,
4664 "mlx5_alloc_transport_domain failed, %d\n", err);
4665 goto err_dealloc_pd;
4666 }
4667 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4668 if (err) {
4669 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4670 goto err_dealloc_transport_domain;
4671 }
4672 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4673
4674 /* check if we should generate a random MAC address */
4675 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4676 is_zero_ether_addr(dev_addr)) {
4677 random_ether_addr(dev_addr);
4678 mlx5_en_err(ifp, "Assigned random MAC address\n");
4679 }
4680
4681 err = mlx5e_rl_init(priv);
4682 if (err) {
4683 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4684 goto err_create_mkey;
4685 }
4686
4687 err = mlx5e_tls_init(priv);
4688 if (err) {
4689 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4690 goto err_rl_init;
4691 }
4692
4693 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4694 if (err) {
4695 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err);
4696 goto err_tls_init;
4697 }
4698
4699 err = mlx5e_open_rqts(priv);
4700 if (err) {
4701 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err);
4702 goto err_open_drop_rq;
4703 }
4704
4705 err = mlx5e_open_tirs(priv);
4706 if (err) {
4707 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err);
4708 goto err_open_rqts;
4709 }
4710
4711 err = mlx5e_open_flow_tables(priv);
4712 if (err) {
4713 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err);
4714 goto err_open_tirs;
4715 }
4716
4717 /* set default MTU */
4718 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4719
4720 /* Set default media status */
4721 priv->media_status_last = IFM_AVALID;
4722 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX;
4723
4724 /* setup default pauseframes configuration */
4725 mlx5e_setup_pauseframes(priv);
4726
4727 /* Setup supported medias */
4728 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4729 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4730 ptys_extended_ethernet);
4731 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4732 eth_proto_capability);
4733 } else {
4734 ext = false;
4735 eth_proto_cap = 0;
4736 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4737 }
4738
4739 ifmedia_init(&priv->media, IFM_IMASK,
4740 mlx5e_media_change, mlx5e_media_status);
4741
4742 if (ext) {
4743 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) {
4744 /* check if hardware has the right capability */
4745 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap)
4746 continue;
4747 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) {
4748 media_entry = mlx5e_ext_mode_table[i][j];
4749 if (media_entry.subtype == 0)
4750 continue;
4751 /* check if this subtype was already added */
4752 for (unsigned k = 0; k != i; k++) {
4753 /* check if hardware has the right capability */
4754 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap)
4755 continue;
4756 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) {
4757 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype)
4758 goto skip_ext_media;
4759 }
4760 }
4761 mlx5e_ifm_add(priv, media_entry.subtype);
4762 skip_ext_media:;
4763 }
4764 }
4765 } else {
4766 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) {
4767 media_entry = mlx5e_mode_table[i];
4768 if (media_entry.subtype == 0)
4769 continue;
4770 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap)
4771 continue;
4772 /* check if this subtype was already added */
4773 for (unsigned k = 0; k != i; k++) {
4774 if (media_entry.subtype == mlx5e_mode_table[k].subtype)
4775 goto skip_media;
4776 }
4777 mlx5e_ifm_add(priv, media_entry.subtype);
4778
4779 /* NOTE: 10G ER and LR shares the same entry */
4780 if (media_entry.subtype == IFM_10G_ER)
4781 mlx5e_ifm_add(priv, IFM_10G_LR);
4782 skip_media:;
4783 }
4784 }
4785
4786 mlx5e_ifm_add(priv, IFM_AUTO);
4787
4788 /* Set autoselect by default */
4789 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4790 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4791
4792 DEBUGNET_SET(ifp, mlx5_en);
4793
4794 ether_ifattach(ifp, dev_addr);
4795
4796 /* Register for VLAN events */
4797 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4798 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4799 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4800 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4801
4802 /* Register for VxLAN events */
4803 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start,
4804 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY);
4805 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop,
4806 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY);
4807
4808 /* Link is down by default */
4809 if_link_state_change(ifp, LINK_STATE_DOWN);
4810
4811 mlx5e_enable_async_events(priv);
4812
4813 mlx5e_add_hw_stats(priv);
4814
4815 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4816 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4817 priv->stats.vport.arg);
4818
4819 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4820 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4821 priv->stats.pport.arg);
4822
4823 mlx5e_create_ethtool(priv);
4824
4825 mtx_lock(&priv->async_events_mtx);
4826 mlx5e_update_stats(priv);
4827 mtx_unlock(&priv->async_events_mtx);
4828
4829 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4830 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4831 &priv->clbr_done, 0,
4832 "RX timestamps calibration state");
4833 callout_init(&priv->tstmp_clbr, 1);
4834 mlx5e_reset_calibration_callout(priv);
4835
4836 pa.pa_version = PFIL_VERSION;
4837 pa.pa_flags = PFIL_IN;
4838 pa.pa_type = PFIL_TYPE_ETHERNET;
4839 pa.pa_headname = ifp->if_xname;
4840 priv->pfil = pfil_head_register(&pa);
4841
4842 PRIV_LOCK(priv);
4843 err = mlx5e_open_flow_rules(priv);
4844 if (err) {
4845 mlx5_en_err(ifp,
4846 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err);
4847 }
4848 PRIV_UNLOCK(priv);
4849
4850 return (priv);
4851
4852 err_open_tirs:
4853 mlx5e_close_tirs(priv);
4854
4855 err_open_rqts:
4856 mlx5e_close_rqts(priv);
4857
4858 err_open_drop_rq:
4859 mlx5e_close_drop_rq(&priv->drop_rq);
4860
4861 err_tls_init:
4862 mlx5e_tls_cleanup(priv);
4863
4864 err_rl_init:
4865 mlx5e_rl_cleanup(priv);
4866
4867 err_create_mkey:
4868 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4869
4870 err_dealloc_transport_domain:
4871 mlx5_dealloc_transport_domain(mdev, priv->tdn);
4872
4873 err_dealloc_pd:
4874 mlx5_core_dealloc_pd(mdev, priv->pdn);
4875
4876 err_free_wq:
4877 flush_workqueue(priv->wq);
4878
4879 err_free_sysctl:
4880 sysctl_ctx_free(&priv->sysctl_ctx);
4881 if (priv->sysctl_debug)
4882 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4883 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
4884
4885 err_free_ifp:
4886 if_free(ifp);
4887
4888 err_free_priv:
4889 free(priv, M_MLX5EN);
4890 return (NULL);
4891 }
4892
4893 static void
mlx5e_destroy_ifp(struct mlx5_core_dev * mdev,void * vpriv)4894 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4895 {
4896 struct mlx5e_priv *priv = vpriv;
4897 struct ifnet *ifp = priv->ifp;
4898
4899 /* don't allow more IOCTLs */
4900 priv->gone = 1;
4901
4902 /* XXX wait a bit to allow IOCTL handlers to complete */
4903 pause("W", hz);
4904
4905 #ifdef RATELIMIT
4906 /*
4907 * The kernel can have reference(s) via the m_snd_tag's into
4908 * the ratelimit channels, and these must go away before
4909 * detaching:
4910 */
4911 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4912 mlx5_en_err(priv->ifp,
4913 "Waiting for all ratelimit connections to terminate\n");
4914 pause("W", hz);
4915 }
4916 #endif
4917
4918 #ifdef KERN_TLS
4919 /* wait for all TLS tags to get freed */
4920 while (priv->tls.init != 0 &&
4921 uma_zone_get_cur(priv->tls.zone) != 0) {
4922 mlx5_en_err(priv->ifp,
4923 "Waiting for all TLS connections to terminate\n");
4924 pause("W", hz);
4925 }
4926 #endif
4927 /* wait for all unlimited send tags to complete */
4928 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4929
4930 /* stop watchdog timer */
4931 callout_drain(&priv->watchdog);
4932
4933 callout_drain(&priv->tstmp_clbr);
4934
4935 if (priv->vlan_attach != NULL)
4936 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4937 if (priv->vlan_detach != NULL)
4938 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4939 if (priv->vxlan_start != NULL)
4940 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start);
4941 if (priv->vxlan_stop != NULL)
4942 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop);
4943
4944 /* make sure device gets closed */
4945 PRIV_LOCK(priv);
4946 mlx5e_close_locked(ifp);
4947 mlx5e_close_flow_rules(priv);
4948 PRIV_UNLOCK(priv);
4949
4950 /* deregister pfil */
4951 if (priv->pfil != NULL) {
4952 pfil_head_unregister(priv->pfil);
4953 priv->pfil = NULL;
4954 }
4955
4956 /* unregister device */
4957 ifmedia_removeall(&priv->media);
4958 ether_ifdetach(ifp);
4959
4960 mlx5e_close_flow_tables(priv);
4961 mlx5e_close_tirs(priv);
4962 mlx5e_close_rqts(priv);
4963 mlx5e_close_drop_rq(&priv->drop_rq);
4964 mlx5e_tls_cleanup(priv);
4965 mlx5e_rl_cleanup(priv);
4966
4967 /* destroy all remaining sysctl nodes */
4968 sysctl_ctx_free(&priv->stats.vport.ctx);
4969 sysctl_ctx_free(&priv->stats.pport.ctx);
4970 if (priv->sysctl_debug)
4971 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4972 sysctl_ctx_free(&priv->sysctl_ctx);
4973
4974 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4975 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4976 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4977 mlx5e_disable_async_events(priv);
4978 flush_workqueue(priv->wq);
4979 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
4980 if_free(ifp);
4981 free(priv, M_MLX5EN);
4982 }
4983
4984 #ifdef DEBUGNET
4985 static void
mlx5_en_debugnet_init(struct ifnet * dev,int * nrxr,int * ncl,int * clsize)4986 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize)
4987 {
4988 struct mlx5e_priv *priv = if_getsoftc(dev);
4989
4990 PRIV_LOCK(priv);
4991 *nrxr = priv->params.num_channels;
4992 *ncl = DEBUGNET_MAX_IN_FLIGHT;
4993 *clsize = MLX5E_MAX_RX_BYTES;
4994 PRIV_UNLOCK(priv);
4995 }
4996
4997 static void
mlx5_en_debugnet_event(struct ifnet * dev,enum debugnet_ev event)4998 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event)
4999 {
5000 }
5001
5002 static int
mlx5_en_debugnet_transmit(struct ifnet * dev,struct mbuf * m)5003 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m)
5004 {
5005 struct mlx5e_priv *priv = if_getsoftc(dev);
5006 struct mlx5e_sq *sq;
5007 int err;
5008
5009 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5010 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
5011 return (ENOENT);
5012
5013 sq = &priv->channel[0].sq[0];
5014
5015 if (sq->running == 0) {
5016 m_freem(m);
5017 return (ENOENT);
5018 }
5019
5020 if (mlx5e_sq_xmit(sq, &m) != 0) {
5021 m_freem(m);
5022 err = ENOBUFS;
5023 } else {
5024 err = 0;
5025 }
5026
5027 mlx5e_tx_notify_hw(sq, true);
5028
5029 return (err);
5030 }
5031
5032 static int
mlx5_en_debugnet_poll(struct ifnet * dev,int count)5033 mlx5_en_debugnet_poll(struct ifnet *dev, int count)
5034 {
5035 struct mlx5e_priv *priv = if_getsoftc(dev);
5036
5037 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
5038 (priv->media_status_last & IFM_ACTIVE) == 0)
5039 return (ENOENT);
5040
5041 mlx5_poll_interrupts(priv->mdev);
5042
5043 return (0);
5044 }
5045 #endif /* DEBUGNET */
5046
5047 static void *
mlx5e_get_ifp(void * vpriv)5048 mlx5e_get_ifp(void *vpriv)
5049 {
5050 struct mlx5e_priv *priv = vpriv;
5051
5052 return (priv->ifp);
5053 }
5054
5055 static struct mlx5_interface mlx5e_interface = {
5056 .add = mlx5e_create_ifp,
5057 .remove = mlx5e_destroy_ifp,
5058 .event = mlx5e_async_event,
5059 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5060 .get_dev = mlx5e_get_ifp,
5061 };
5062
5063 void
mlx5e_init(void)5064 mlx5e_init(void)
5065 {
5066 mlx5_register_interface(&mlx5e_interface);
5067 }
5068
5069 void
mlx5e_cleanup(void)5070 mlx5e_cleanup(void)
5071 {
5072 mlx5_unregister_interface(&mlx5e_interface);
5073 }
5074
5075 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
5076 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
5077
5078 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
5079 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
5080 MODULE_VERSION(mlx5en, 1);
5081