1 /*-
2 * Copyright (c) 2015-2016 Kevin Lo <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/condvar.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/sbuf.h>
37 #include <sys/socket.h>
38 #include <sys/sysctl.h>
39 #include <sys/unistd.h>
40
41 #include <net/if.h>
42 #include <net/if_var.h>
43 #include <net/if_media.h>
44
45 /* needed for checksum offload */
46 #include <netinet/in.h>
47 #include <netinet/ip.h>
48
49 #include <dev/mii/mii.h>
50 #include <dev/mii/miivar.h>
51
52 #include <dev/usb/usb.h>
53 #include <dev/usb/usbdi.h>
54 #include <dev/usb/usbdi_util.h>
55 #include "usbdevs.h"
56
57 #define USB_DEBUG_VAR ure_debug
58 #include <dev/usb/usb_debug.h>
59 #include <dev/usb/usb_process.h>
60
61 #include <dev/usb/net/usb_ethernet.h>
62 #include <dev/usb/net/if_urereg.h>
63
64 #include "miibus_if.h"
65
66 #include "opt_inet6.h"
67
68 #ifdef USB_DEBUG
69 static int ure_debug = 0;
70
71 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
72 "USB ure");
73 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
74 "Debug level");
75 #endif
76
77 #ifdef USB_DEBUG_VAR
78 #ifdef USB_DEBUG
79 #define DEVPRINTFN(n,dev,fmt,...) do { \
80 if ((USB_DEBUG_VAR) >= (n)) { \
81 device_printf((dev), "%s: " fmt, \
82 __FUNCTION__ ,##__VA_ARGS__); \
83 } \
84 } while (0)
85 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__)
86 #else
87 #define DEVPRINTF(...) do { } while (0)
88 #define DEVPRINTFN(...) do { } while (0)
89 #endif
90 #endif
91
92 /*
93 * Various supported device vendors/products.
94 */
95 static const STRUCT_USB_HOST_ID ure_devs[] = {
96 #define URE_DEV(v,p,i) { \
97 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \
98 USB_IFACE_CLASS(UICLASS_VENDOR), \
99 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) }
100 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153),
101 URE_DEV(LENOVO, TBT3LAN, 0),
102 URE_DEV(LENOVO, TBT3LANGEN2, 0),
103 URE_DEV(LENOVO, ONELINK, 0),
104 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153),
105 URE_DEV(LENOVO, ONELINKPLUS, URE_FLAG_8153),
106 URE_DEV(LENOVO, USBCLAN, 0),
107 URE_DEV(LENOVO, USBCLANGEN2, 0),
108 URE_DEV(LENOVO, USBCLANHYBRID, 0),
109 URE_DEV(MICROSOFT, WINDEVETH, 0),
110 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153),
111 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
112 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153),
113 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153),
114 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156),
115 #undef URE_DEV
116 };
117
118 static device_probe_t ure_probe;
119 static device_attach_t ure_attach;
120 static device_detach_t ure_detach;
121
122 static usb_callback_t ure_bulk_read_callback;
123 static usb_callback_t ure_bulk_write_callback;
124
125 static miibus_readreg_t ure_miibus_readreg;
126 static miibus_writereg_t ure_miibus_writereg;
127 static miibus_statchg_t ure_miibus_statchg;
128
129 static uether_fn_t ure_attach_post;
130 static uether_fn_t ure_init;
131 static uether_fn_t ure_stop;
132 static uether_fn_t ure_start;
133 static uether_fn_t ure_tick;
134 static uether_fn_t ure_rxfilter;
135
136 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
137 void *, int);
138 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
139 int);
140 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
141 int);
142 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
143 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
144 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
145 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
146 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
147 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
148 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
149 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
150 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t);
151
152 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS);
153
154 static void ure_read_chipver(struct ure_softc *);
155 static int ure_attach_post_sub(struct usb_ether *);
156 static void ure_reset(struct ure_softc *);
157 static int ure_ifmedia_upd(if_t);
158 static void ure_ifmedia_sts(if_t, struct ifmediareq *);
159 static void ure_add_media_types(struct ure_softc *);
160 static void ure_link_state(struct ure_softc *sc);
161 static int ure_get_link_status(struct ure_softc *);
162 static int ure_ioctl(if_t, u_long, caddr_t);
163 static void ure_rtl8152_init(struct ure_softc *);
164 static void ure_rtl8152_nic_reset(struct ure_softc *);
165 static void ure_rtl8153_init(struct ure_softc *);
166 static void ure_rtl8153b_init(struct ure_softc *);
167 static void ure_rtl8153b_nic_reset(struct ure_softc *);
168 static void ure_disable_teredo(struct ure_softc *);
169 static void ure_enable_aldps(struct ure_softc *, bool);
170 static uint16_t ure_phy_status(struct ure_softc *, uint16_t);
171 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m);
172 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout);
173
174 static device_method_t ure_methods[] = {
175 /* Device interface. */
176 DEVMETHOD(device_probe, ure_probe),
177 DEVMETHOD(device_attach, ure_attach),
178 DEVMETHOD(device_detach, ure_detach),
179
180 /* MII interface. */
181 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
182 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
183 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
184
185 DEVMETHOD_END
186 };
187
188 static driver_t ure_driver = {
189 .name = "ure",
190 .methods = ure_methods,
191 .size = sizeof(struct ure_softc),
192 };
193
194 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL);
195 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL);
196 MODULE_DEPEND(ure, uether, 1, 1, 1);
197 MODULE_DEPEND(ure, usb, 1, 1, 1);
198 MODULE_DEPEND(ure, ether, 1, 1, 1);
199 MODULE_DEPEND(ure, miibus, 1, 1, 1);
200 MODULE_VERSION(ure, 1);
201 USB_PNP_HOST_INFO(ure_devs);
202
203 static const struct usb_ether_methods ure_ue_methods = {
204 .ue_attach_post = ure_attach_post,
205 .ue_attach_post_sub = ure_attach_post_sub,
206 .ue_start = ure_start,
207 .ue_init = ure_init,
208 .ue_stop = ure_stop,
209 .ue_tick = ure_tick,
210 .ue_setmulti = ure_rxfilter,
211 .ue_setpromisc = ure_rxfilter,
212 .ue_mii_upd = ure_ifmedia_upd,
213 .ue_mii_sts = ure_ifmedia_sts,
214 };
215
216 #define URE_SETBIT_1(sc, reg, index, x) \
217 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
218 #define URE_SETBIT_2(sc, reg, index, x) \
219 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
220 #define URE_SETBIT_4(sc, reg, index, x) \
221 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
222
223 #define URE_CLRBIT_1(sc, reg, index, x) \
224 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
225 #define URE_CLRBIT_2(sc, reg, index, x) \
226 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
227 #define URE_CLRBIT_4(sc, reg, index, x) \
228 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
229
230 static int
ure_ctl(struct ure_softc * sc,uint8_t rw,uint16_t val,uint16_t index,void * buf,int len)231 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
232 void *buf, int len)
233 {
234 struct usb_device_request req;
235
236 URE_LOCK_ASSERT(sc, MA_OWNED);
237
238 if (rw == URE_CTL_WRITE)
239 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
240 else
241 req.bmRequestType = UT_READ_VENDOR_DEVICE;
242 req.bRequest = UR_SET_ADDRESS;
243 USETW(req.wValue, val);
244 USETW(req.wIndex, index);
245 USETW(req.wLength, len);
246
247 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
248 }
249
250 static int
ure_read_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)251 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
252 void *buf, int len)
253 {
254
255 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
256 }
257
258 static int
ure_write_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)259 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
260 void *buf, int len)
261 {
262
263 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
264 }
265
266 static uint8_t
ure_read_1(struct ure_softc * sc,uint16_t reg,uint16_t index)267 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
268 {
269 uint32_t val;
270 uint8_t temp[4];
271 uint8_t shift;
272
273 shift = (reg & 3) << 3;
274 reg &= ~3;
275
276 ure_read_mem(sc, reg, index, &temp, 4);
277 val = UGETDW(temp);
278 val >>= shift;
279
280 return (val & 0xff);
281 }
282
283 static uint16_t
ure_read_2(struct ure_softc * sc,uint16_t reg,uint16_t index)284 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
285 {
286 uint32_t val;
287 uint8_t temp[4];
288 uint8_t shift;
289
290 shift = (reg & 2) << 3;
291 reg &= ~3;
292
293 ure_read_mem(sc, reg, index, &temp, 4);
294 val = UGETDW(temp);
295 val >>= shift;
296
297 return (val & 0xffff);
298 }
299
300 static uint32_t
ure_read_4(struct ure_softc * sc,uint16_t reg,uint16_t index)301 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
302 {
303 uint8_t temp[4];
304
305 ure_read_mem(sc, reg, index, &temp, 4);
306 return (UGETDW(temp));
307 }
308
309 static int
ure_write_1(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)310 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
311 {
312 uint16_t byen;
313 uint8_t temp[4];
314 uint8_t shift;
315
316 byen = URE_BYTE_EN_BYTE;
317 shift = reg & 3;
318 val &= 0xff;
319
320 if (reg & 3) {
321 byen <<= shift;
322 val <<= (shift << 3);
323 reg &= ~3;
324 }
325
326 USETDW(temp, val);
327 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
328 }
329
330 static int
ure_write_2(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)331 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
332 {
333 uint16_t byen;
334 uint8_t temp[4];
335 uint8_t shift;
336
337 byen = URE_BYTE_EN_WORD;
338 shift = reg & 2;
339 val &= 0xffff;
340
341 if (reg & 2) {
342 byen <<= shift;
343 val <<= (shift << 3);
344 reg &= ~3;
345 }
346
347 USETDW(temp, val);
348 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
349 }
350
351 static int
ure_write_4(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)352 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
353 {
354 uint8_t temp[4];
355
356 USETDW(temp, val);
357 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
358 }
359
360 static uint16_t
ure_ocp_reg_read(struct ure_softc * sc,uint16_t addr)361 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
362 {
363 uint16_t reg;
364
365 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
366 reg = (addr & 0x0fff) | 0xb000;
367
368 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
369 }
370
371 static void
ure_ocp_reg_write(struct ure_softc * sc,uint16_t addr,uint16_t data)372 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
373 {
374 uint16_t reg;
375
376 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
377 reg = (addr & 0x0fff) | 0xb000;
378
379 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
380 }
381
382 static void
ure_sram_write(struct ure_softc * sc,uint16_t addr,uint16_t data)383 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
384 {
385 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr);
386 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data);
387 }
388
389 static int
ure_miibus_readreg(device_t dev,int phy,int reg)390 ure_miibus_readreg(device_t dev, int phy, int reg)
391 {
392 struct ure_softc *sc;
393 uint16_t val;
394 int locked;
395
396 sc = device_get_softc(dev);
397 locked = mtx_owned(&sc->sc_mtx);
398 if (!locked)
399 URE_LOCK(sc);
400
401 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
402 if (reg == URE_GMEDIASTAT) {
403 if (!locked)
404 URE_UNLOCK(sc);
405 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
406 }
407
408 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
409
410 if (!locked)
411 URE_UNLOCK(sc);
412 return (val);
413 }
414
415 static int
ure_miibus_writereg(device_t dev,int phy,int reg,int val)416 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
417 {
418 struct ure_softc *sc;
419 int locked;
420
421 sc = device_get_softc(dev);
422 if (sc->sc_phyno != phy)
423 return (0);
424
425 locked = mtx_owned(&sc->sc_mtx);
426 if (!locked)
427 URE_LOCK(sc);
428
429 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
430
431 if (!locked)
432 URE_UNLOCK(sc);
433 return (0);
434 }
435
436 static void
ure_miibus_statchg(device_t dev)437 ure_miibus_statchg(device_t dev)
438 {
439 struct ure_softc *sc;
440 struct mii_data *mii;
441 if_t ifp;
442 int locked;
443
444 sc = device_get_softc(dev);
445 mii = GET_MII(sc);
446 locked = mtx_owned(&sc->sc_mtx);
447 if (!locked)
448 URE_LOCK(sc);
449
450 ifp = uether_getifp(&sc->sc_ue);
451 if (mii == NULL || ifp == NULL ||
452 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
453 goto done;
454
455 sc->sc_flags &= ~URE_FLAG_LINK;
456 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
457 (IFM_ACTIVE | IFM_AVALID)) {
458 switch (IFM_SUBTYPE(mii->mii_media_active)) {
459 case IFM_10_T:
460 case IFM_100_TX:
461 sc->sc_flags |= URE_FLAG_LINK;
462 sc->sc_rxstarted = 0;
463 break;
464 case IFM_1000_T:
465 if ((sc->sc_flags & URE_FLAG_8152) != 0)
466 break;
467 sc->sc_flags |= URE_FLAG_LINK;
468 sc->sc_rxstarted = 0;
469 break;
470 default:
471 break;
472 }
473 }
474
475 /* Lost link, do nothing. */
476 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
477 goto done;
478 done:
479 if (!locked)
480 URE_UNLOCK(sc);
481 }
482
483 /*
484 * Probe for a RTL8152/RTL8153/RTL8156 chip.
485 */
486 static int
ure_probe(device_t dev)487 ure_probe(device_t dev)
488 {
489 struct usb_attach_arg *uaa;
490
491 uaa = device_get_ivars(dev);
492 if (uaa->usb_mode != USB_MODE_HOST)
493 return (ENXIO);
494 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
495 return (ENXIO);
496
497 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
498 }
499
500 /*
501 * Attach the interface. Allocate softc structures, do ifmedia
502 * setup and ethernet/BPF attach.
503 */
504 static int
ure_attach(device_t dev)505 ure_attach(device_t dev)
506 {
507 struct usb_attach_arg *uaa = device_get_ivars(dev);
508 struct ure_softc *sc = device_get_softc(dev);
509 struct usb_ether *ue = &sc->sc_ue;
510 struct usb_config ure_config_rx[URE_MAX_RX];
511 struct usb_config ure_config_tx[URE_MAX_TX];
512 uint8_t iface_index;
513 int error;
514 int i;
515
516 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
517 device_set_usb_desc(dev);
518 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
519
520 iface_index = URE_IFACE_IDX;
521
522 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B))
523 sc->sc_rxbufsz = URE_8153_RX_BUFSZ;
524 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
525 sc->sc_rxbufsz = URE_8156_RX_BUFSZ;
526 else
527 sc->sc_rxbufsz = URE_8152_RX_BUFSZ;
528
529 for (i = 0; i < URE_MAX_RX; i++) {
530 ure_config_rx[i] = (struct usb_config) {
531 .type = UE_BULK,
532 .endpoint = UE_ADDR_ANY,
533 .direction = UE_DIR_IN,
534 .bufsize = sc->sc_rxbufsz,
535 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
536 .callback = ure_bulk_read_callback,
537 .timeout = 0, /* no timeout */
538 };
539 }
540 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer,
541 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx);
542 if (error != 0) {
543 device_printf(dev, "allocating USB RX transfers failed\n");
544 goto detach;
545 }
546
547 for (i = 0; i < URE_MAX_TX; i++) {
548 ure_config_tx[i] = (struct usb_config) {
549 .type = UE_BULK,
550 .endpoint = UE_ADDR_ANY,
551 .direction = UE_DIR_OUT,
552 .bufsize = URE_TX_BUFSZ,
553 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
554 .callback = ure_bulk_write_callback,
555 .timeout = 10000, /* 10 seconds */
556 };
557 }
558 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer,
559 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx);
560 if (error != 0) {
561 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
562 device_printf(dev, "allocating USB TX transfers failed\n");
563 goto detach;
564 }
565
566 ue->ue_sc = sc;
567 ue->ue_dev = dev;
568 ue->ue_udev = uaa->device;
569 ue->ue_mtx = &sc->sc_mtx;
570 ue->ue_methods = &ure_ue_methods;
571
572 error = uether_ifattach(ue);
573 if (error != 0) {
574 device_printf(dev, "could not attach interface\n");
575 goto detach;
576 }
577 return (0); /* success */
578
579 detach:
580 ure_detach(dev);
581 return (ENXIO); /* failure */
582 }
583
584 static int
ure_detach(device_t dev)585 ure_detach(device_t dev)
586 {
587 struct ure_softc *sc = device_get_softc(dev);
588 struct usb_ether *ue = &sc->sc_ue;
589
590 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX);
591 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
592 uether_ifdetach(ue);
593 mtx_destroy(&sc->sc_mtx);
594
595 return (0);
596 }
597
598 /*
599 * Copy from USB buffers to a new mbuf chain with pkt header.
600 *
601 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf
602 * clusters as necessary.
603 */
604 static struct mbuf *
ure_makembuf(struct usb_page_cache * pc,usb_frlength_t offset,usb_frlength_t len)605 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset,
606 usb_frlength_t len)
607 {
608 struct usb_page_search_res;
609 struct mbuf *m, *mb;
610 usb_frlength_t tlen;
611
612 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR);
613 if (m == NULL)
614 return (m);
615
616 /* uether_newbuf does this. */
617 m_adj(m, ETHER_ALIGN);
618
619 m->m_pkthdr.len = len;
620
621 for (mb = m; len > 0; mb = mb->m_next) {
622 tlen = MIN(len, M_TRAILINGSPACE(mb));
623
624 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen);
625 mb->m_len = tlen;
626
627 offset += tlen;
628 len -= tlen;
629 }
630
631 return (m);
632 }
633
634 static void
ure_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)635 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
636 {
637 struct ure_softc *sc = usbd_xfer_softc(xfer);
638 struct usb_ether *ue = &sc->sc_ue;
639 if_t ifp = uether_getifp(ue);
640 struct usb_page_cache *pc;
641 struct mbuf *m;
642 struct ure_rxpkt pkt;
643 int actlen, off, len;
644 int caps;
645 uint32_t pktcsum;
646
647 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
648
649 switch (USB_GET_STATE(xfer)) {
650 case USB_ST_TRANSFERRED:
651 off = 0;
652 pc = usbd_xfer_get_frame(xfer, 0);
653 caps = if_getcapenable(ifp);
654 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n");
655 while (actlen > 0) {
656 if (actlen < (int)(sizeof(pkt))) {
657 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
658 goto tr_setup;
659 }
660 usbd_copy_out(pc, off, &pkt, sizeof(pkt));
661
662 off += sizeof(pkt);
663 actlen -= sizeof(pkt);
664
665 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
666
667 DEVPRINTFN(13, sc->sc_ue.ue_dev,
668 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n",
669 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc,
670 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4);
671 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len);
672
673 if (len >= URE_RXPKT_LEN_MASK) {
674 /*
675 * drop the rest of this segment. With out
676 * more information, we cannot know where next
677 * packet starts. Blindly continuing would
678 * cause a packet in packet attack, allowing
679 * one VLAN to inject packets w/o a VLAN tag,
680 * or injecting packets into other VLANs.
681 */
682 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
683 goto tr_setup;
684 }
685
686 if (actlen < len) {
687 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
688 goto tr_setup;
689 }
690
691 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN))
692 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN);
693 else
694 m = NULL;
695 if (m == NULL) {
696 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
697 } else {
698 /* make mbuf and queue */
699 pktcsum = le32toh(pkt.ure_csum);
700 if (caps & IFCAP_VLAN_HWTAGGING &&
701 pktcsum & URE_RXPKT_RX_VLAN_TAG) {
702 m->m_pkthdr.ether_vtag =
703 bswap16(pktcsum &
704 URE_RXPKT_VLAN_MASK);
705 m->m_flags |= M_VLANTAG;
706 }
707
708 /* set the necessary flags for rx checksum */
709 ure_rxcsum(caps, &pkt, m);
710
711 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN);
712 }
713
714 off += roundup(len, URE_RXPKT_ALIGN);
715 actlen -= roundup(len, URE_RXPKT_ALIGN);
716 }
717 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n");
718
719 /* FALLTHROUGH */
720 case USB_ST_SETUP:
721 tr_setup:
722 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
723 usbd_transfer_submit(xfer);
724 uether_rxflush(ue);
725 return;
726
727 default: /* Error */
728 DPRINTF("bulk read error, %s\n",
729 usbd_errstr(error));
730
731 if (error != USB_ERR_CANCELLED) {
732 /* try to clear stall first */
733 usbd_xfer_set_stall(xfer);
734 goto tr_setup;
735 }
736 return;
737 }
738 }
739
740 static void
ure_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)741 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
742 {
743 struct ure_softc *sc = usbd_xfer_softc(xfer);
744 if_t ifp = uether_getifp(&sc->sc_ue);
745 struct usb_page_cache *pc;
746 struct mbuf *m;
747 struct ure_txpkt txpkt;
748 uint32_t regtmp;
749 int len, pos;
750 int rem;
751 int caps;
752
753 switch (USB_GET_STATE(xfer)) {
754 case USB_ST_TRANSFERRED:
755 DPRINTFN(11, "transfer complete\n");
756 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
757
758 /* FALLTHROUGH */
759 case USB_ST_SETUP:
760 tr_setup:
761 if ((sc->sc_flags & URE_FLAG_LINK) == 0) {
762 /* don't send anything if there is no link! */
763 break;
764 }
765
766 pc = usbd_xfer_get_frame(xfer, 0);
767 caps = if_getcapenable(ifp);
768
769 pos = 0;
770 rem = URE_TX_BUFSZ;
771 while (rem > sizeof(txpkt)) {
772 m = if_dequeue(ifp);
773 if (m == NULL)
774 break;
775
776 /*
777 * make sure we don't ever send too large of a
778 * packet
779 */
780 len = m->m_pkthdr.len;
781 if ((len & URE_TXPKT_LEN_MASK) != len) {
782 device_printf(sc->sc_ue.ue_dev,
783 "pkt len too large: %#x", len);
784 pkterror:
785 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
786 m_freem(m);
787 continue;
788 }
789
790 if (sizeof(txpkt) +
791 roundup(len, URE_TXPKT_ALIGN) > rem) {
792 /* out of space */
793 if_sendq_prepend(ifp, m);
794 m = NULL;
795 break;
796 }
797
798 txpkt = (struct ure_txpkt){};
799 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
800 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
801 if (m->m_flags & M_VLANTAG) {
802 txpkt.ure_csum = htole32(
803 bswap16(m->m_pkthdr.ether_vtag &
804 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN);
805 }
806 if (ure_txcsum(m, caps, ®tmp)) {
807 device_printf(sc->sc_ue.ue_dev,
808 "pkt l4 off too large");
809 goto pkterror;
810 }
811 txpkt.ure_csum |= htole32(regtmp);
812
813 DEVPRINTFN(13, sc->sc_ue.ue_dev,
814 "txpkt: mbflg: %#x, %#x, %#x\n",
815 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen),
816 le32toh(txpkt.ure_csum));
817
818 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
819
820 pos += sizeof(txpkt);
821 rem -= sizeof(txpkt);
822
823 usbd_m_copy_in(pc, pos, m, 0, len);
824
825 pos += roundup(len, URE_TXPKT_ALIGN);
826 rem -= roundup(len, URE_TXPKT_ALIGN);
827
828 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
829
830 /*
831 * If there's a BPF listener, bounce a copy
832 * of this frame to him.
833 */
834 BPF_MTAP(ifp, m);
835
836 m_freem(m);
837 }
838
839 /* no packets to send */
840 if (pos == 0)
841 break;
842
843 /* Set frame length. */
844 usbd_xfer_set_frame_len(xfer, 0, pos);
845
846 usbd_transfer_submit(xfer);
847
848 return;
849
850 default: /* Error */
851 DPRINTFN(11, "transfer error, %s\n",
852 usbd_errstr(error));
853
854 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
855 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
856
857 if (error == USB_ERR_TIMEOUT) {
858 DEVPRINTFN(12, sc->sc_ue.ue_dev,
859 "pkt tx timeout\n");
860 }
861
862 if (error != USB_ERR_CANCELLED) {
863 /* try to clear stall first */
864 usbd_xfer_set_stall(xfer);
865 goto tr_setup;
866 }
867 }
868 }
869
870 static void
ure_read_chipver(struct ure_softc * sc)871 ure_read_chipver(struct ure_softc *sc)
872 {
873 uint16_t ver;
874
875 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
876 sc->sc_ver = ver;
877 switch (ver) {
878 case 0x4c00:
879 sc->sc_chip |= URE_CHIP_VER_4C00;
880 sc->sc_flags = URE_FLAG_8152;
881 break;
882 case 0x4c10:
883 sc->sc_chip |= URE_CHIP_VER_4C10;
884 sc->sc_flags = URE_FLAG_8152;
885 break;
886 case 0x5c00:
887 sc->sc_chip |= URE_CHIP_VER_5C00;
888 sc->sc_flags = URE_FLAG_8153;
889 break;
890 case 0x5c10:
891 sc->sc_chip |= URE_CHIP_VER_5C10;
892 sc->sc_flags = URE_FLAG_8153;
893 break;
894 case 0x5c20:
895 sc->sc_chip |= URE_CHIP_VER_5C20;
896 sc->sc_flags = URE_FLAG_8153;
897 break;
898 case 0x5c30:
899 sc->sc_chip |= URE_CHIP_VER_5C30;
900 sc->sc_flags = URE_FLAG_8153;
901 break;
902 case 0x6000:
903 sc->sc_flags = URE_FLAG_8153B;
904 sc->sc_chip |= URE_CHIP_VER_6000;
905 break;
906 case 0x6010:
907 sc->sc_flags = URE_FLAG_8153B;
908 sc->sc_chip |= URE_CHIP_VER_6010;
909 break;
910 case 0x7020:
911 sc->sc_flags = URE_FLAG_8156;
912 sc->sc_chip |= URE_CHIP_VER_7020;
913 break;
914 case 0x7030:
915 sc->sc_flags = URE_FLAG_8156;
916 sc->sc_chip |= URE_CHIP_VER_7030;
917 break;
918 case 0x7400:
919 sc->sc_flags = URE_FLAG_8156B;
920 sc->sc_chip |= URE_CHIP_VER_7400;
921 break;
922 case 0x7410:
923 sc->sc_flags = URE_FLAG_8156B;
924 sc->sc_chip |= URE_CHIP_VER_7410;
925 break;
926 default:
927 device_printf(sc->sc_ue.ue_dev,
928 "unknown version 0x%04x\n", ver);
929 break;
930 }
931 }
932
933 static int
ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)934 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)
935 {
936 struct sbuf sb;
937 struct ure_softc *sc = arg1;
938 int error;
939
940 sbuf_new_for_sysctl(&sb, NULL, 0, req);
941
942 sbuf_printf(&sb, "%04x", sc->sc_ver);
943
944 error = sbuf_finish(&sb);
945 sbuf_delete(&sb);
946
947 return (error);
948 }
949
950 static void
ure_attach_post(struct usb_ether * ue)951 ure_attach_post(struct usb_ether *ue)
952 {
953 struct ure_softc *sc = uether_getsc(ue);
954
955 sc->sc_rxstarted = 0;
956 sc->sc_phyno = 0;
957
958 /* Determine the chip version. */
959 ure_read_chipver(sc);
960
961 /* Initialize controller and get station address. */
962 if (sc->sc_flags & URE_FLAG_8152)
963 ure_rtl8152_init(sc);
964 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
965 ure_rtl8153b_init(sc);
966 else
967 ure_rtl8153_init(sc);
968
969 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
970 (sc->sc_chip & URE_CHIP_VER_4C10))
971 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
972 ue->ue_eaddr, 8);
973 else
974 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
975 ue->ue_eaddr, 8);
976
977 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
978 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
979 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
980 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
981 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
982 }
983 }
984
985 static int
ure_attach_post_sub(struct usb_ether * ue)986 ure_attach_post_sub(struct usb_ether *ue)
987 {
988 struct sysctl_ctx_list *sctx;
989 struct sysctl_oid *soid;
990 struct ure_softc *sc;
991 if_t ifp;
992 int error;
993
994 sc = uether_getsc(ue);
995 ifp = ue->ue_ifp;
996 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
997 if_setstartfn(ifp, uether_start);
998 if_setioctlfn(ifp, ure_ioctl);
999 if_setinitfn(ifp, uether_init);
1000 /*
1001 * Try to keep two transfers full at a time.
1002 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight)
1003 */
1004 if_setsendqlen(ifp, 512);
1005 if_setsendqready(ifp);
1006
1007 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1008 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
1009 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);
1010 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1011 #ifdef INET6
1012 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);
1013 #endif
1014 if_setcapenable(ifp, if_getcapabilities(ifp));
1015
1016 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1017 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd,
1018 ure_ifmedia_sts);
1019 ure_add_media_types(sc);
1020 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1021 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
1022 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
1023 error = 0;
1024 } else {
1025 bus_topo_lock();
1026 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
1027 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
1028 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
1029 bus_topo_unlock();
1030 }
1031
1032 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev);
1033 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev);
1034 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver",
1035 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1036 ure_sysctl_chipver, "A",
1037 "Return string with chip version.");
1038
1039 return (error);
1040 }
1041
1042 static void
ure_init(struct usb_ether * ue)1043 ure_init(struct usb_ether *ue)
1044 {
1045 struct ure_softc *sc = uether_getsc(ue);
1046 if_t ifp = uether_getifp(ue);
1047 uint16_t cpcr;
1048 uint32_t reg;
1049
1050 URE_LOCK_ASSERT(sc, MA_OWNED);
1051
1052 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1053 return;
1054
1055 /* Cancel pending I/O. */
1056 ure_stop(ue);
1057
1058 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1059 ure_rtl8153b_nic_reset(sc);
1060 else
1061 ure_reset(sc);
1062
1063 /* Set MAC address. */
1064 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1065 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
1066 if_getlladdr(ifp), 8);
1067 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1068
1069 /* Set RX EARLY timeout and size */
1070 if (sc->sc_flags & URE_FLAG_8153) {
1071 switch (usbd_get_speed(sc->sc_ue.ue_udev)) {
1072 case USB_SPEED_SUPER:
1073 reg = URE_COALESCE_SUPER / 8;
1074 break;
1075 case USB_SPEED_HIGH:
1076 reg = URE_COALESCE_HIGH / 8;
1077 break;
1078 default:
1079 reg = URE_COALESCE_SLOW / 8;
1080 break;
1081 }
1082 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg);
1083 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1084 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1085 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4);
1086 } else if (sc->sc_flags & URE_FLAG_8153B) {
1087 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158);
1088 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1089 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1090 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1091 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1092 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1093 URE_OWN_UPDATE | URE_OWN_CLEAR);
1094 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1095 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80);
1096 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1097 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1098 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1099 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1100 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1101 URE_OWN_UPDATE | URE_OWN_CLEAR);
1102 }
1103
1104 if (sc->sc_flags & URE_FLAG_8156B) {
1105 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1106 uether_pause(&sc->sc_ue, hz / 500);
1107 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1108 }
1109
1110 /* Reset the packet filter. */
1111 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1112 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1113
1114 /* Enable RX VLANs if enabled */
1115 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
1116 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1117 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n");
1118 cpcr |= URE_CPCR_RX_VLAN;
1119 } else {
1120 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n");
1121 cpcr &= ~URE_CPCR_RX_VLAN;
1122 }
1123 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr);
1124
1125 /* Enable transmit and receive. */
1126 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1127
1128 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1129
1130 /* Configure RX filters. */
1131 ure_rxfilter(ue);
1132
1133 usbd_xfer_set_stall(sc->sc_tx_xfer[0]);
1134
1135 /* Indicate we are up and running. */
1136 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1137
1138 /* Switch to selected media. */
1139 ure_ifmedia_upd(ifp);
1140 }
1141
1142 static void
ure_tick(struct usb_ether * ue)1143 ure_tick(struct usb_ether *ue)
1144 {
1145 struct ure_softc *sc = uether_getsc(ue);
1146 if_t ifp = uether_getifp(ue);
1147 struct mii_data *mii;
1148
1149 URE_LOCK_ASSERT(sc, MA_OWNED);
1150
1151 (void)ifp;
1152 for (int i = 0; i < URE_MAX_RX; i++)
1153 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1154 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i]));
1155
1156 for (int i = 0; i < URE_MAX_TX; i++)
1157 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1158 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i]));
1159
1160 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1161 ure_link_state(sc);
1162 } else {
1163 mii = GET_MII(sc);
1164 mii_tick(mii);
1165 if ((sc->sc_flags & URE_FLAG_LINK) == 0
1166 && mii->mii_media_status & IFM_ACTIVE &&
1167 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1168 sc->sc_flags |= URE_FLAG_LINK;
1169 sc->sc_rxstarted = 0;
1170 ure_start(ue);
1171 }
1172 }
1173 }
1174
1175 static u_int
ure_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1176 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1177 {
1178 uint32_t h, *hashes = arg;
1179
1180 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
1181 if (h < 32)
1182 hashes[0] |= (1 << h);
1183 else
1184 hashes[1] |= (1 << (h - 32));
1185 return (1);
1186 }
1187
1188 /*
1189 * Program the 64-bit multicast hash filter.
1190 */
1191 static void
ure_rxfilter(struct usb_ether * ue)1192 ure_rxfilter(struct usb_ether *ue)
1193 {
1194 struct ure_softc *sc = uether_getsc(ue);
1195 if_t ifp = uether_getifp(ue);
1196 uint32_t rxmode;
1197 uint32_t h, hashes[2] = { 0, 0 };
1198
1199 URE_LOCK_ASSERT(sc, MA_OWNED);
1200
1201 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
1202 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM);
1203 rxmode |= URE_RCR_APM; /* accept physical match packets */
1204 rxmode |= URE_RCR_AB; /* always accept broadcasts */
1205 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
1206 if (if_getflags(ifp) & IFF_PROMISC)
1207 rxmode |= URE_RCR_AAP;
1208 rxmode |= URE_RCR_AM;
1209 hashes[0] = hashes[1] = 0xffffffff;
1210 goto done;
1211 }
1212
1213 /* calculate multicast masks */
1214 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
1215
1216 h = bswap32(hashes[0]);
1217 hashes[0] = bswap32(hashes[1]);
1218 hashes[1] = h;
1219 rxmode |= URE_RCR_AM; /* accept multicast packets */
1220
1221 done:
1222 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n",
1223 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1224 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
1225 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
1226 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
1227 }
1228
1229 static void
ure_start(struct usb_ether * ue)1230 ure_start(struct usb_ether *ue)
1231 {
1232 struct ure_softc *sc = uether_getsc(ue);
1233 unsigned i;
1234
1235 URE_LOCK_ASSERT(sc, MA_OWNED);
1236
1237 if (!sc->sc_rxstarted) {
1238 sc->sc_rxstarted = 1;
1239 for (i = 0; i != URE_MAX_RX; i++)
1240 usbd_transfer_start(sc->sc_rx_xfer[i]);
1241 }
1242
1243 for (i = 0; i != URE_MAX_TX; i++)
1244 usbd_transfer_start(sc->sc_tx_xfer[i]);
1245 }
1246
1247 static void
ure_reset(struct ure_softc * sc)1248 ure_reset(struct ure_softc *sc)
1249 {
1250 int i;
1251
1252 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
1253
1254 for (i = 0; i < URE_TIMEOUT; i++) {
1255 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
1256 URE_CR_RST))
1257 break;
1258 uether_pause(&sc->sc_ue, hz / 100);
1259 }
1260 if (i == URE_TIMEOUT)
1261 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
1262 }
1263
1264 /*
1265 * Set media options.
1266 */
1267 static int
ure_ifmedia_upd(if_t ifp)1268 ure_ifmedia_upd(if_t ifp)
1269 {
1270 struct ure_softc *sc = if_getsoftc(ifp);
1271 struct ifmedia *ifm;
1272 struct mii_data *mii;
1273 struct mii_softc *miisc;
1274 int gig;
1275 int reg;
1276 int anar;
1277 int locked;
1278 int error;
1279
1280 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1281 ifm = &sc->sc_ifmedia;
1282 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1283 return (EINVAL);
1284
1285 locked = mtx_owned(&sc->sc_mtx);
1286 if (!locked)
1287 URE_LOCK(sc);
1288 reg = ure_ocp_reg_read(sc, 0xa5d4);
1289 reg &= ~URE_ADV_2500TFDX;
1290
1291 anar = gig = 0;
1292 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1293 case IFM_AUTO:
1294 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1295 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1296 reg |= URE_ADV_2500TFDX;
1297 break;
1298 case IFM_2500_T:
1299 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1300 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1301 reg |= URE_ADV_2500TFDX;
1302 if_setbaudrate(ifp, IF_Mbps(2500));
1303 break;
1304 case IFM_1000_T:
1305 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1306 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1307 if_setbaudrate(ifp, IF_Gbps(1));
1308 break;
1309 case IFM_100_TX:
1310 anar |= ANAR_TX | ANAR_TX_FD;
1311 if_setbaudrate(ifp, IF_Mbps(100));
1312 break;
1313 case IFM_10_T:
1314 anar |= ANAR_10 | ANAR_10_FD;
1315 if_setbaudrate(ifp, IF_Mbps(10));
1316 break;
1317 default:
1318 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n");
1319 if (!locked)
1320 URE_UNLOCK(sc);
1321 return (EINVAL);
1322 }
1323
1324 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
1325 anar | ANAR_PAUSE_ASYM | ANAR_FC);
1326 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
1327 ure_ocp_reg_write(sc, 0xa5d4, reg);
1328 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR,
1329 BMCR_AUTOEN | BMCR_STARTNEG);
1330 if (!locked)
1331 URE_UNLOCK(sc);
1332 return (0);
1333 }
1334
1335 mii = GET_MII(sc);
1336
1337 URE_LOCK_ASSERT(sc, MA_OWNED);
1338 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1339 PHY_RESET(miisc);
1340 error = mii_mediachg(mii);
1341 return (error);
1342 }
1343
1344 /*
1345 * Report current media status.
1346 */
1347 static void
ure_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1348 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1349 {
1350 struct ure_softc *sc;
1351 struct mii_data *mii;
1352 uint16_t status;
1353
1354 sc = if_getsoftc(ifp);
1355 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1356 URE_LOCK(sc);
1357 ifmr->ifm_status = IFM_AVALID;
1358 if (ure_get_link_status(sc)) {
1359 ifmr->ifm_status |= IFM_ACTIVE;
1360 status = ure_read_2(sc, URE_PLA_PHYSTATUS,
1361 URE_MCU_TYPE_PLA);
1362 if ((status & URE_PHYSTATUS_FDX) ||
1363 (status & URE_PHYSTATUS_2500MBPS))
1364 ifmr->ifm_active |= IFM_FDX;
1365 else
1366 ifmr->ifm_active |= IFM_HDX;
1367 if (status & URE_PHYSTATUS_10MBPS)
1368 ifmr->ifm_active |= IFM_10_T;
1369 else if (status & URE_PHYSTATUS_100MBPS)
1370 ifmr->ifm_active |= IFM_100_TX;
1371 else if (status & URE_PHYSTATUS_1000MBPS)
1372 ifmr->ifm_active |= IFM_1000_T;
1373 else if (status & URE_PHYSTATUS_2500MBPS)
1374 ifmr->ifm_active |= IFM_2500_T;
1375 }
1376 URE_UNLOCK(sc);
1377 return;
1378 }
1379
1380 mii = GET_MII(sc);
1381
1382 URE_LOCK(sc);
1383 mii_pollstat(mii);
1384 ifmr->ifm_active = mii->mii_media_active;
1385 ifmr->ifm_status = mii->mii_media_status;
1386 URE_UNLOCK(sc);
1387 }
1388
1389 static void
ure_add_media_types(struct ure_softc * sc)1390 ure_add_media_types(struct ure_softc *sc)
1391 {
1392 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1393 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1394 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1395 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1396 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1397 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
1398 }
1399
1400 static void
ure_link_state(struct ure_softc * sc)1401 ure_link_state(struct ure_softc *sc)
1402 {
1403 if_t ifp = uether_getifp(&sc->sc_ue);
1404
1405 if (ure_get_link_status(sc)) {
1406 if (if_getlinkstate(ifp) != LINK_STATE_UP) {
1407 if_link_state_change(ifp, LINK_STATE_UP);
1408 /* Enable transmit and receive. */
1409 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1410
1411 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1412 URE_PHYSTATUS_2500MBPS)
1413 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1414 else
1415 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1416 }
1417 } else {
1418 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) {
1419 if_link_state_change(ifp, LINK_STATE_DOWN);
1420 }
1421 }
1422 }
1423
1424 static int
ure_get_link_status(struct ure_softc * sc)1425 ure_get_link_status(struct ure_softc *sc)
1426 {
1427 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1428 URE_PHYSTATUS_LINK) {
1429 sc->sc_flags |= URE_FLAG_LINK;
1430 return (1);
1431 } else {
1432 sc->sc_flags &= ~URE_FLAG_LINK;
1433 return (0);
1434 }
1435 }
1436
1437 static int
ure_ioctl(if_t ifp,u_long cmd,caddr_t data)1438 ure_ioctl(if_t ifp, u_long cmd, caddr_t data)
1439 {
1440 struct usb_ether *ue = if_getsoftc(ifp);
1441 struct ure_softc *sc;
1442 struct ifreq *ifr;
1443 int error, mask, reinit;
1444
1445 sc = uether_getsc(ue);
1446 ifr = (struct ifreq *)data;
1447 error = 0;
1448 reinit = 0;
1449 switch (cmd) {
1450 case SIOCSIFCAP:
1451 URE_LOCK(sc);
1452 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1453 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1454 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1455 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1456 reinit++;
1457 }
1458 if ((mask & IFCAP_TXCSUM) != 0 &&
1459 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1460 if_togglecapenable(ifp, IFCAP_TXCSUM);
1461 }
1462 if ((mask & IFCAP_RXCSUM) != 0 &&
1463 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1464 if_togglecapenable(ifp, IFCAP_RXCSUM);
1465 }
1466 if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&
1467 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {
1468 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
1469 }
1470 if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&
1471 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {
1472 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
1473 }
1474 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1475 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1476 else
1477 reinit = 0;
1478 URE_UNLOCK(sc);
1479 if (reinit > 0)
1480 uether_init(ue);
1481 break;
1482
1483 case SIOCSIFMTU:
1484 /*
1485 * in testing large MTUs "crashes" the device, it
1486 * leaves the device w/ a broken state where link
1487 * is in a bad state.
1488 */
1489 if (ifr->ifr_mtu < ETHERMIN ||
1490 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN -
1491 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) {
1492 error = EINVAL;
1493 break;
1494 }
1495 URE_LOCK(sc);
1496 if (if_getmtu(ifp) != ifr->ifr_mtu)
1497 if_setmtu(ifp, ifr->ifr_mtu);
1498 URE_UNLOCK(sc);
1499 break;
1500
1501 case SIOCGIFMEDIA:
1502 case SIOCSIFMEDIA:
1503 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1504 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
1505 else
1506 error = uether_ioctl(ifp, cmd, data);
1507 break;
1508
1509 default:
1510 error = uether_ioctl(ifp, cmd, data);
1511 break;
1512 }
1513
1514 return (error);
1515 }
1516
1517 static void
ure_rtl8152_init(struct ure_softc * sc)1518 ure_rtl8152_init(struct ure_softc *sc)
1519 {
1520 uint32_t pwrctrl;
1521
1522 ure_enable_aldps(sc, false);
1523
1524 if (sc->sc_chip & URE_CHIP_VER_4C00) {
1525 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1526 }
1527
1528 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT);
1529
1530 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE);
1531
1532 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
1533
1534 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
1535 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1536 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
1537 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
1538 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
1539 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
1540 URE_SPDWN_LINKCHG_MSK);
1541
1542 /* Enable Rx aggregation. */
1543 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1544
1545 ure_enable_aldps(sc, false);
1546
1547 ure_rtl8152_nic_reset(sc);
1548
1549 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
1550 URE_TX_AGG_MAX_THRESHOLD);
1551 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
1552 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
1553 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
1554 }
1555
1556 static void
ure_rtl8153_init(struct ure_softc * sc)1557 ure_rtl8153_init(struct ure_softc *sc)
1558 {
1559 uint16_t val;
1560 uint8_t u1u2[8];
1561 int i;
1562
1563 ure_enable_aldps(sc, false);
1564
1565 memset(u1u2, 0x00, sizeof(u1u2));
1566 ure_write_mem(sc, URE_USB_TOLERANCE,
1567 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1568
1569 for (i = 0; i < URE_TIMEOUT; i++) {
1570 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1571 URE_AUTOLOAD_DONE)
1572 break;
1573 uether_pause(&sc->sc_ue, hz / 100);
1574 }
1575 if (i == URE_TIMEOUT)
1576 device_printf(sc->sc_ue.ue_dev,
1577 "timeout waiting for chip autoload\n");
1578
1579 for (i = 0; i < URE_TIMEOUT; i++) {
1580 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1581 URE_PHY_STAT_MASK;
1582 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1583 break;
1584 uether_pause(&sc->sc_ue, hz / 100);
1585 }
1586 if (i == URE_TIMEOUT)
1587 device_printf(sc->sc_ue.ue_dev,
1588 "timeout waiting for phy to stabilize\n");
1589
1590 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1591
1592 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1593 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1594 val &= ~URE_PWD_DN_SCALE_MASK;
1595 val |= URE_PWD_DN_SCALE(96);
1596 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1597
1598 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1599 } else if (sc->sc_chip & URE_CHIP_VER_5C20)
1600 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS);
1601
1602 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1603 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1604 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1605 0)
1606 val &= ~URE_DYNAMIC_BURST;
1607 else
1608 val |= URE_DYNAMIC_BURST;
1609 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1610 }
1611
1612 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
1613
1614 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
1615
1616 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1617
1618 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1619 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1620 val = URE_LPM_TIMER_500MS;
1621 else
1622 val = URE_LPM_TIMER_500US;
1623 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1624 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1625
1626 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1627 val &= ~URE_SEN_VAL_MASK;
1628 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1629 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1630
1631 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1632
1633 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN);
1634
1635 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1636
1637 memset(u1u2, 0xff, sizeof(u1u2));
1638 ure_write_mem(sc, URE_USB_TOLERANCE,
1639 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1640
1641 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1642 URE_ALDPS_SPDWN_RATIO);
1643 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1644 URE_EEE_SPDWN_RATIO);
1645 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1646 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1647 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1648 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1649 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1650 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1651 URE_EEE_SPDWN_EN);
1652
1653 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1654 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1655 val |= URE_U2P3_ENABLE;
1656 else
1657 val &= ~URE_U2P3_ENABLE;
1658 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1659
1660 memset(u1u2, 0x00, sizeof(u1u2));
1661 ure_write_mem(sc, URE_USB_TOLERANCE,
1662 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1663
1664 ure_enable_aldps(sc, false);
1665
1666 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1667 URE_CHIP_VER_5C20)) {
1668 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1669 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1670 }
1671 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1672 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1673 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1674 ~URE_CTAP_SHORT_EN);
1675 }
1676 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1677 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1678 URE_EEE_CLKDIV_EN);
1679 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1680 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1681 URE_EN_10M_BGOFF);
1682 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1683 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1684 URE_EN_10M_PLLOFF);
1685 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);
1686 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH);
1687
1688 /* Enable LPF corner auto tune. */
1689 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);
1690
1691 /* Adjust 10M amplitude. */
1692 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);
1693 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);
1694
1695 ure_rtl8152_nic_reset(sc);
1696
1697 /* Enable Rx aggregation. */
1698 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1699
1700 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1701 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1702 val |= URE_U2P3_ENABLE;
1703 else
1704 val &= ~URE_U2P3_ENABLE;
1705 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1706
1707 memset(u1u2, 0xff, sizeof(u1u2));
1708 ure_write_mem(sc, URE_USB_TOLERANCE,
1709 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1710 }
1711
1712 static void
ure_rtl8153b_init(struct ure_softc * sc)1713 ure_rtl8153b_init(struct ure_softc *sc)
1714 {
1715 uint16_t val;
1716 int i;
1717
1718 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1719 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);
1720 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);
1721 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);
1722 }
1723
1724 if (sc->sc_flags & URE_FLAG_8156B) {
1725 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);
1726 }
1727
1728 ure_enable_aldps(sc, false);
1729
1730 /* Disable U1U2 */
1731 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1732
1733 /* Wait loading flash */
1734 if (sc->sc_chip == URE_CHIP_VER_7410) {
1735 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&
1736 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {
1737 for (i=0; i < 100; i++) {
1738 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)
1739 break;
1740 uether_pause(&sc->sc_ue, hz / 1000);
1741 }
1742 }
1743 }
1744
1745 for (i = 0; i < URE_TIMEOUT; i++) {
1746 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1747 URE_AUTOLOAD_DONE)
1748 break;
1749 uether_pause(&sc->sc_ue, hz / 100);
1750 }
1751 if (i == URE_TIMEOUT)
1752 device_printf(sc->sc_ue.ue_dev,
1753 "timeout waiting for chip autoload\n");
1754
1755 val = ure_phy_status(sc, 0);
1756 if ((val == URE_PHY_STAT_EXT_INIT) &
1757 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) {
1758 ure_ocp_reg_write(sc, 0xa468,
1759 ure_ocp_reg_read(sc, 0xa468) & ~0x0a);
1760 if (sc->sc_flags & URE_FLAG_8156B)
1761 ure_ocp_reg_write(sc, 0xa466,
1762 ure_ocp_reg_read(sc, 0xa466) & ~0x01);
1763 }
1764
1765 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR);
1766 if (val & BMCR_PDOWN) {
1767 val &= ~BMCR_PDOWN;
1768 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val);
1769 }
1770
1771 ure_phy_status(sc, URE_PHY_STAT_LAN_ON);
1772
1773 /* Disable U2P3 */
1774 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1775
1776 /* MSC timer, 32760 ms. */
1777 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);
1778
1779 /* U1/U2/L1 idle timer, 500 us. */
1780 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1781
1782 /* Disable power cut */
1783 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1784 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1785
1786 /* Disable ups */
1787 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE);
1788 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);
1789
1790 /* Disable queue wake */
1791 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3);
1792 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT);
1793 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG);
1794
1795 /* Disable runtime suspend */
1796 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1797 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN);
1798 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1799
1800 /* Enable U1U2 */
1801 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1802 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1803
1804 if (sc->sc_flags & URE_FLAG_8156B) {
1805 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);
1806 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);
1807
1808 /* enable fc timer and set timer to 600 ms. */
1809 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8));
1810
1811 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {
1812 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1813 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;
1814 val &= ~0x08;
1815 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val);
1816 }
1817
1818 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1819 }
1820
1821 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1822 if (ure_get_link_status(sc))
1823 val |= URE_CUR_LINK_OK;
1824 else
1825 val &= ~URE_CUR_LINK_OK;
1826 val |= URE_POLL_LINK_CHG;
1827 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val);
1828
1829 /* MAC clock speed down */
1830 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1831 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);
1832 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA);
1833 val &= ~0xff;
1834 val |= URE_MAC_CLK_SPDWN_EN | 0x03;
1835 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val);
1836 } else {
1837 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN);
1838 }
1839 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1840
1841 /* Enable Rx aggregation. */
1842 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1843
1844 if (sc->sc_flags & URE_FLAG_8156)
1845 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);
1846
1847 /* Reset tally */
1848 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET);
1849 }
1850
1851 static void
ure_rtl8153b_nic_reset(struct ure_softc * sc)1852 ure_rtl8153b_nic_reset(struct ure_softc *sc)
1853 {
1854 if_t ifp = uether_getifp(&sc->sc_ue);
1855 uint16_t val;
1856 int i;
1857
1858 /* Disable U1U2 */
1859 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1860
1861 /* Disable U2P3 */
1862 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1863
1864 ure_enable_aldps(sc, false);
1865
1866 /* Enable rxdy_gated */
1867 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1868
1869 /* Disable teredo */
1870 ure_disable_teredo(sc);
1871
1872 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1873 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1874
1875 ure_reset(sc);
1876
1877 /* Reset BMU */
1878 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1879 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1880
1881 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1882 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1883 if (sc->sc_flags & URE_FLAG_8153B) {
1884 for (i = 0; i < URE_TIMEOUT; i++) {
1885 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1886 URE_LINK_LIST_READY)
1887 break;
1888 uether_pause(&sc->sc_ue, hz / 100);
1889 }
1890 if (i == URE_TIMEOUT)
1891 device_printf(sc->sc_ue.ue_dev,
1892 "timeout waiting for OOB control\n");
1893
1894 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
1895 for (i = 0; i < URE_TIMEOUT; i++) {
1896 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1897 URE_LINK_LIST_READY)
1898 break;
1899 uether_pause(&sc->sc_ue, hz / 100);
1900 }
1901 if (i == URE_TIMEOUT)
1902 device_printf(sc->sc_ue.ue_dev,
1903 "timeout waiting for OOB control\n");
1904 }
1905
1906 /* Configure rxvlan */
1907 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);
1908 val &= ~0x00c0;
1909 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)
1910 val |= 0x00c0;
1911 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);
1912
1913 val = if_getmtu(ifp);
1914 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val));
1915 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO);
1916
1917 if (sc->sc_flags & URE_FLAG_8153B) {
1918 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
1919 ure_reset(sc);
1920 }
1921
1922 /* Configure fc parameter */
1923 if (sc->sc_flags & URE_FLAG_8156) {
1924 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);
1925 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);
1926 } else if (sc->sc_flags & URE_FLAG_8156B) {
1927 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);
1928 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);
1929 }
1930
1931 /* Configure Rx FIFO threshold. */
1932 if (sc->sc_flags & URE_FLAG_8153B) {
1933 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL);
1934 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL);
1935 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL);
1936 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B);
1937 } else {
1938 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,
1939 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);
1940 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);
1941 }
1942
1943 /* Configure Tx FIFO threshold. */
1944 if (sc->sc_flags & URE_FLAG_8153B) {
1945 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
1946 } else if (sc->sc_flags & URE_FLAG_8156) {
1947 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
1948 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);
1949 } else if (sc->sc_flags & URE_FLAG_8156B) {
1950 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);
1951 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,
1952 (URE_FRAMELEN(val) + 0x100) / 16 );
1953 }
1954
1955 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1956
1957 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1958 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);
1959
1960 ure_enable_aldps(sc, true);
1961
1962 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1963 /* Enable U2P3 */
1964 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1965 }
1966
1967 /* Enable U1U2 */
1968 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1969 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1970 }
1971
1972 static void
ure_stop(struct usb_ether * ue)1973 ure_stop(struct usb_ether *ue)
1974 {
1975 struct ure_softc *sc = uether_getsc(ue);
1976 if_t ifp = uether_getifp(ue);
1977
1978 URE_LOCK_ASSERT(sc, MA_OWNED);
1979
1980 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1981 sc->sc_flags &= ~URE_FLAG_LINK;
1982 sc->sc_rxstarted = 0;
1983
1984 /*
1985 * stop all the transfers, if not already stopped:
1986 */
1987 for (int i = 0; i < URE_MAX_RX; i++)
1988 usbd_transfer_stop(sc->sc_rx_xfer[i]);
1989 for (int i = 0; i < URE_MAX_TX; i++)
1990 usbd_transfer_stop(sc->sc_tx_xfer[i]);
1991 }
1992
1993 static void
ure_disable_teredo(struct ure_softc * sc)1994 ure_disable_teredo(struct ure_softc *sc)
1995 {
1996
1997 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1998 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);
1999 else {
2000 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
2001 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
2002 }
2003 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE);
2004 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
2005 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
2006 }
2007
2008 static void
ure_enable_aldps(struct ure_softc * sc,bool enable)2009 ure_enable_aldps(struct ure_softc *sc, bool enable)
2010 {
2011 int i;
2012
2013 if (enable) {
2014 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
2015 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
2016 } else {
2017 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
2018 URE_DIS_SDSAVE);
2019 for (i = 0; i < 20; i++) {
2020 uether_pause(&sc->sc_ue, hz / 1000);
2021 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)
2022 break;
2023 }
2024 }
2025 }
2026
2027 static uint16_t
ure_phy_status(struct ure_softc * sc,uint16_t desired)2028 ure_phy_status(struct ure_softc *sc, uint16_t desired)
2029 {
2030 uint16_t val;
2031 int i;
2032
2033 for (i = 0; i < URE_TIMEOUT; i++) {
2034 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
2035 URE_PHY_STAT_MASK;
2036 if (desired) {
2037 if (val == desired)
2038 break;
2039 } else {
2040 if (val == URE_PHY_STAT_LAN_ON ||
2041 val == URE_PHY_STAT_PWRDN ||
2042 val == URE_PHY_STAT_EXT_INIT)
2043 break;
2044 }
2045 uether_pause(&sc->sc_ue, hz / 100);
2046 }
2047 if (i == URE_TIMEOUT)
2048 device_printf(sc->sc_ue.ue_dev,
2049 "timeout waiting for phy to stabilize\n");
2050
2051 return (val);
2052 }
2053
2054 static void
ure_rtl8152_nic_reset(struct ure_softc * sc)2055 ure_rtl8152_nic_reset(struct ure_softc *sc)
2056 {
2057 uint32_t rx_fifo1, rx_fifo2;
2058 int i;
2059
2060 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
2061
2062 ure_disable_teredo(sc);
2063
2064 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
2065 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
2066
2067 ure_reset(sc);
2068
2069 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
2070
2071 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
2072
2073 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
2074 for (i = 0; i < URE_TIMEOUT; i++) {
2075 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2076 URE_LINK_LIST_READY)
2077 break;
2078 uether_pause(&sc->sc_ue, hz / 100);
2079 }
2080 if (i == URE_TIMEOUT)
2081 device_printf(sc->sc_ue.ue_dev,
2082 "timeout waiting for OOB control\n");
2083 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
2084 for (i = 0; i < URE_TIMEOUT; i++) {
2085 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2086 URE_LINK_LIST_READY)
2087 break;
2088 uether_pause(&sc->sc_ue, hz / 100);
2089 }
2090 if (i == URE_TIMEOUT)
2091 device_printf(sc->sc_ue.ue_dev,
2092 "timeout waiting for OOB control\n");
2093
2094 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN);
2095
2096 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
2097
2098 /* Configure Rx FIFO threshold. */
2099 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
2100 URE_RXFIFO_THR1_NORMAL);
2101 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
2102 rx_fifo1 = URE_RXFIFO_THR2_FULL;
2103 rx_fifo2 = URE_RXFIFO_THR3_FULL;
2104 } else {
2105 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
2106 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
2107 }
2108 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
2109 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
2110
2111 /* Configure Tx FIFO threshold. */
2112 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
2113 URE_TXFIFO_THR_NORMAL);
2114 }
2115
2116 /*
2117 * Update mbuf for rx checksum from hardware
2118 */
2119 static void
ure_rxcsum(int capenb,struct ure_rxpkt * rp,struct mbuf * m)2120 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m)
2121 {
2122 int flags;
2123 uint32_t csum, misc;
2124 int tcp, udp;
2125
2126 m->m_pkthdr.csum_flags = 0;
2127
2128 if (!(capenb & IFCAP_RXCSUM))
2129 return;
2130
2131 csum = le32toh(rp->ure_csum);
2132 misc = le32toh(rp->ure_misc);
2133
2134 tcp = udp = 0;
2135
2136 flags = 0;
2137 if (csum & URE_RXPKT_IPV4_CS)
2138 flags |= CSUM_IP_CHECKED;
2139 else if (csum & URE_RXPKT_IPV6_CS)
2140 flags = 0;
2141
2142 tcp = rp->ure_csum & URE_RXPKT_TCP_CS;
2143 udp = rp->ure_csum & URE_RXPKT_UDP_CS;
2144
2145 if (__predict_true((flags & CSUM_IP_CHECKED) &&
2146 !(misc & URE_RXPKT_IP_F))) {
2147 flags |= CSUM_IP_VALID;
2148 }
2149 if (__predict_true(
2150 (tcp && !(misc & URE_RXPKT_TCP_F)) ||
2151 (udp && !(misc & URE_RXPKT_UDP_F)))) {
2152 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2153 m->m_pkthdr.csum_data = 0xFFFF;
2154 }
2155
2156 m->m_pkthdr.csum_flags = flags;
2157 }
2158
2159 /*
2160 * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2161 * We currently restrict MTU such that it can't happen, and even if we
2162 * did have a large enough MTU, only a very specially crafted IPv6 packet
2163 * with MANY headers could possibly come close.
2164 *
2165 * Returns 0 for success, and 1 if the packet cannot be checksummed and
2166 * should be dropped.
2167 */
2168 static int
ure_txcsum(struct mbuf * m,int caps,uint32_t * regout)2169 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout)
2170 {
2171 struct ip ip;
2172 struct ether_header *eh;
2173 int flags;
2174 uint32_t data;
2175 uint32_t reg;
2176 int l3off, l4off;
2177 uint16_t type;
2178
2179 *regout = 0;
2180 flags = m->m_pkthdr.csum_flags;
2181 if (flags == 0)
2182 return (0);
2183
2184 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
2185 eh = mtod(m, struct ether_header *);
2186 type = eh->ether_type;
2187 } else
2188 m_copydata(m, offsetof(struct ether_header, ether_type),
2189 sizeof(type), (caddr_t)&type);
2190
2191 switch (type = htons(type)) {
2192 case ETHERTYPE_IP:
2193 case ETHERTYPE_IPV6:
2194 l3off = ETHER_HDR_LEN;
2195 break;
2196 case ETHERTYPE_VLAN:
2197 /* XXX - what about QinQ? */
2198 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2199 break;
2200 default:
2201 return (0);
2202 }
2203
2204 reg = 0;
2205
2206 if (flags & CSUM_IP)
2207 reg |= URE_TXPKT_IPV4_CS;
2208
2209 data = m->m_pkthdr.csum_data;
2210 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) {
2211 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip);
2212 l4off = l3off + (ip.ip_hl << 2) + data;
2213 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2214 return (1);
2215
2216 reg |= URE_TXPKT_IPV4_CS;
2217 if (flags & CSUM_IP_TCP)
2218 reg |= URE_TXPKT_TCP_CS;
2219 else if (flags & CSUM_IP_UDP)
2220 reg |= URE_TXPKT_UDP_CS;
2221 reg |= l4off << URE_L4_OFFSET_SHIFT;
2222 }
2223 #ifdef INET6
2224 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
2225 l4off = l3off + data;
2226 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2227 return (1);
2228
2229 reg |= URE_TXPKT_IPV6_CS;
2230 if (flags & CSUM_IP6_TCP)
2231 reg |= URE_TXPKT_TCP_CS;
2232 else if (flags & CSUM_IP6_UDP)
2233 reg |= URE_TXPKT_UDP_CS;
2234 reg |= l4off << URE_L4_OFFSET_SHIFT;
2235 }
2236 #endif
2237 *regout = reg;
2238 return 0;
2239 }
2240