1 //===-- ABIX86.cpp --------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "ABIMacOSX_i386.h"
10 #include "ABISysV_i386.h"
11 #include "ABISysV_x86_64.h"
12 #include "ABIWindows_x86_64.h"
13 #include "ABIX86.h"
14 #include "lldb/Core/PluginManager.h"
15 #include "lldb/Target/Process.h"
16
17 using namespace lldb;
18 using namespace lldb_private;
19
LLDB_PLUGIN_DEFINE(ABIX86)20 LLDB_PLUGIN_DEFINE(ABIX86)
21
22 void ABIX86::Initialize() {
23 ABIMacOSX_i386::Initialize();
24 ABISysV_i386::Initialize();
25 ABISysV_x86_64::Initialize();
26 ABIWindows_x86_64::Initialize();
27 }
28
Terminate()29 void ABIX86::Terminate() {
30 ABIMacOSX_i386::Terminate();
31 ABISysV_i386::Terminate();
32 ABISysV_x86_64::Terminate();
33 ABIWindows_x86_64::Terminate();
34 }
35
36 namespace {
37 enum RegKind {
38 GPR32,
39 GPR16,
40 GPR8h,
41 GPR8,
42 MM,
43 YMM_YMMh,
44 YMM_XMM,
45
46 RegKindCount
47 };
48 }
49
50 struct RegData {
51 RegKind subreg_kind;
52 llvm::StringRef subreg_name;
53 llvm::Optional<uint32_t> base_index;
54 };
55
56 static void
addPartialRegisters(std::vector<DynamicRegisterInfo::Register> & regs,llvm::ArrayRef<RegData * > subregs,uint32_t base_size,lldb::Encoding encoding,lldb::Format format,uint32_t subreg_size,uint32_t subreg_offset=0)57 addPartialRegisters(std::vector<DynamicRegisterInfo::Register> ®s,
58 llvm::ArrayRef<RegData *> subregs, uint32_t base_size,
59 lldb::Encoding encoding, lldb::Format format,
60 uint32_t subreg_size, uint32_t subreg_offset = 0) {
61 for (const RegData *subreg : subregs) {
62 assert(subreg);
63 uint32_t base_index = *subreg->base_index;
64 DynamicRegisterInfo::Register &full_reg = regs[base_index];
65 if (full_reg.byte_size != base_size)
66 continue;
67
68 lldb_private::DynamicRegisterInfo::Register new_reg{
69 lldb_private::ConstString(subreg->subreg_name),
70 lldb_private::ConstString(),
71 lldb_private::ConstString("supplementary registers"),
72 subreg_size,
73 LLDB_INVALID_INDEX32,
74 encoding,
75 format,
76 LLDB_INVALID_REGNUM,
77 LLDB_INVALID_REGNUM,
78 LLDB_INVALID_REGNUM,
79 LLDB_INVALID_REGNUM,
80 {base_index},
81 {},
82 subreg_offset};
83
84 addSupplementaryRegister(regs, new_reg);
85 }
86 }
87
88 static void
addCombinedRegisters(std::vector<DynamicRegisterInfo::Register> & regs,llvm::ArrayRef<RegData * > subregs1,llvm::ArrayRef<RegData * > subregs2,uint32_t base_size,lldb::Encoding encoding,lldb::Format format)89 addCombinedRegisters(std::vector<DynamicRegisterInfo::Register> ®s,
90 llvm::ArrayRef<RegData *> subregs1,
91 llvm::ArrayRef<RegData *> subregs2, uint32_t base_size,
92 lldb::Encoding encoding, lldb::Format format) {
93 for (auto it : llvm::zip(subregs1, subregs2)) {
94 RegData *regdata1, *regdata2;
95 std::tie(regdata1, regdata2) = it;
96 assert(regdata1);
97 assert(regdata2);
98
99 // verify that we've got matching target registers
100 if (regdata1->subreg_name != regdata2->subreg_name)
101 continue;
102
103 uint32_t base_index1 = regdata1->base_index.value();
104 uint32_t base_index2 = regdata2->base_index.value();
105 if (regs[base_index1].byte_size != base_size ||
106 regs[base_index2].byte_size != base_size)
107 continue;
108
109 lldb_private::DynamicRegisterInfo::Register new_reg{
110 lldb_private::ConstString(regdata1->subreg_name),
111 lldb_private::ConstString(),
112 lldb_private::ConstString("supplementary registers"),
113 base_size * 2,
114 LLDB_INVALID_INDEX32,
115 encoding,
116 format,
117 LLDB_INVALID_REGNUM,
118 LLDB_INVALID_REGNUM,
119 LLDB_INVALID_REGNUM,
120 LLDB_INVALID_REGNUM,
121 {base_index1, base_index2},
122 {}};
123
124 addSupplementaryRegister(regs, new_reg);
125 }
126 }
127
128 typedef llvm::SmallDenseMap<llvm::StringRef, llvm::SmallVector<RegData, 4>, 64>
129 BaseRegToRegsMap;
130
131 #define GPRh(l) \
132 { \
133 is64bit \
134 ? BaseRegToRegsMap::value_type("r" l "x", \
135 {{GPR32, "e" l "x", llvm::None}, \
136 {GPR16, l "x", llvm::None}, \
137 {GPR8h, l "h", llvm::None}, \
138 {GPR8, l "l", llvm::None}}) \
139 : BaseRegToRegsMap::value_type("e" l "x", {{GPR16, l "x", llvm::None}, \
140 {GPR8h, l "h", llvm::None}, \
141 {GPR8, l "l", llvm::None}}) \
142 }
143
144 #define GPR(r16) \
145 { \
146 is64bit \
147 ? BaseRegToRegsMap::value_type("r" r16, {{GPR32, "e" r16, llvm::None}, \
148 {GPR16, r16, llvm::None}, \
149 {GPR8, r16 "l", llvm::None}}) \
150 : BaseRegToRegsMap::value_type("e" r16, {{GPR16, r16, llvm::None}, \
151 {GPR8, r16 "l", llvm::None}}) \
152 }
153
154 #define GPR64(n) \
155 { \
156 BaseRegToRegsMap::value_type("r" #n, {{GPR32, "r" #n "d", llvm::None}, \
157 {GPR16, "r" #n "w", llvm::None}, \
158 {GPR8, "r" #n "l", llvm::None}}) \
159 }
160
161 #define STMM(n) \
162 { BaseRegToRegsMap::value_type("st" #n, {{MM, "mm" #n, llvm::None}}) }
163
164 #define YMM(n) \
165 {BaseRegToRegsMap::value_type("ymm" #n "h", \
166 {{YMM_YMMh, "ymm" #n, llvm::None}})}, \
167 { \
168 BaseRegToRegsMap::value_type("xmm" #n, {{YMM_XMM, "ymm" #n, llvm::None}}) \
169 }
170
makeBaseRegMap(bool is64bit)171 BaseRegToRegsMap makeBaseRegMap(bool is64bit) {
172 BaseRegToRegsMap out{
173 {// GPRs common to amd64 & i386
174 GPRh("a"), GPRh("b"), GPRh("c"), GPRh("d"), GPR("si"), GPR("di"),
175 GPR("bp"), GPR("sp"),
176
177 // ST/MM registers
178 STMM(0), STMM(1), STMM(2), STMM(3), STMM(4), STMM(5), STMM(6), STMM(7),
179
180 // lower YMM registers (common to amd64 & i386)
181 YMM(0), YMM(1), YMM(2), YMM(3), YMM(4), YMM(5), YMM(6), YMM(7)}};
182
183 if (is64bit) {
184 BaseRegToRegsMap amd64_regs{{// GPRs specific to amd64
185 GPR64(8), GPR64(9), GPR64(10), GPR64(11),
186 GPR64(12), GPR64(13), GPR64(14), GPR64(15),
187
188 // higher YMM registers (specific to amd64)
189 YMM(8), YMM(9), YMM(10), YMM(11), YMM(12),
190 YMM(13), YMM(14), YMM(15)}};
191 out.insert(amd64_regs.begin(), amd64_regs.end());
192 }
193
194 return out;
195 }
196
AugmentRegisterInfo(std::vector<DynamicRegisterInfo::Register> & regs)197 void ABIX86::AugmentRegisterInfo(
198 std::vector<DynamicRegisterInfo::Register> ®s) {
199 MCBasedABI::AugmentRegisterInfo(regs);
200
201 ProcessSP process_sp = GetProcessSP();
202 if (!process_sp)
203 return;
204
205 uint32_t gpr_base_size =
206 process_sp->GetTarget().GetArchitecture().GetAddressByteSize();
207
208 // primary map from a base register to its subregisters
209 BaseRegToRegsMap base_reg_map = makeBaseRegMap(gpr_base_size == 8);
210 // set used for fast matching of register names to subregisters
211 llvm::SmallDenseSet<llvm::StringRef, 64> subreg_name_set;
212 // convenience array providing access to all subregisters of given kind,
213 // sorted by base register index
214 std::array<llvm::SmallVector<RegData *, 16>, RegKindCount> subreg_by_kind;
215
216 // prepare the set of all known subregisters
217 for (const auto &x : base_reg_map) {
218 for (const auto &subreg : x.second)
219 subreg_name_set.insert(subreg.subreg_name);
220 }
221
222 // iterate over all registers
223 for (const auto &x : llvm::enumerate(regs)) {
224 llvm::StringRef reg_name = x.value().name.GetStringRef();
225 // abort if at least one sub-register is already present
226 if (llvm::is_contained(subreg_name_set, reg_name))
227 return;
228
229 auto found = base_reg_map.find(reg_name);
230 if (found == base_reg_map.end())
231 continue;
232
233 for (auto &subreg : found->second) {
234 // fill in base register indices
235 subreg.base_index = x.index();
236 // fill subreg_by_kind map-array
237 subreg_by_kind[static_cast<size_t>(subreg.subreg_kind)].push_back(
238 &subreg);
239 }
240 }
241
242 // now add registers by kind
243 addPartialRegisters(regs, subreg_by_kind[GPR32], gpr_base_size, eEncodingUint,
244 eFormatHex, 4);
245 addPartialRegisters(regs, subreg_by_kind[GPR16], gpr_base_size, eEncodingUint,
246 eFormatHex, 2);
247 addPartialRegisters(regs, subreg_by_kind[GPR8h], gpr_base_size, eEncodingUint,
248 eFormatHex, 1, 1);
249 addPartialRegisters(regs, subreg_by_kind[GPR8], gpr_base_size, eEncodingUint,
250 eFormatHex, 1);
251
252 addPartialRegisters(regs, subreg_by_kind[MM], 10, eEncodingUint, eFormatHex,
253 8);
254
255 addCombinedRegisters(regs, subreg_by_kind[YMM_XMM], subreg_by_kind[YMM_YMMh],
256 16, eEncodingVector, eFormatVectorOfUInt8);
257 }
258