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39
40
41 /**
42 * cvmx-pcmx-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon pcmx.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_PCMX_DEFS_H__
53 #define __CVMX_PCMX_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_DMA_CFG(unsigned long offset)56 static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
57 {
58 if (!(
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
64 cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
65 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
66 }
67 #else
68 #define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384)
69 #endif
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_INT_ENA(unsigned long offset)71 static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
72 {
73 if (!(
74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
78 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
79 cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
80 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
81 }
82 #else
83 #define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384)
84 #endif
85 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_INT_SUM(unsigned long offset)86 static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
87 {
88 if (!(
89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
93 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
94 cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
95 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
96 }
97 #else
98 #define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384)
99 #endif
100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXADDR(unsigned long offset)101 static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
102 {
103 if (!(
104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
109 cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
110 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
111 }
112 #else
113 #define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384)
114 #endif
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXCNT(unsigned long offset)116 static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
117 {
118 if (!(
119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
123 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
124 cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
125 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
126 }
127 #else
128 #define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384)
129 #endif
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK0(unsigned long offset)131 static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
132 {
133 if (!(
134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
137 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
138 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
139 cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
140 return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384;
141 }
142 #else
143 #define CVMX_PCMX_RXMSK0(offset) (CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384)
144 #endif
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK1(unsigned long offset)146 static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
147 {
148 if (!(
149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
154 cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
155 return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384;
156 }
157 #else
158 #define CVMX_PCMX_RXMSK1(offset) (CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384)
159 #endif
160 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK2(unsigned long offset)161 static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
162 {
163 if (!(
164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
168 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
169 cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
170 return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384;
171 }
172 #else
173 #define CVMX_PCMX_RXMSK2(offset) (CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384)
174 #endif
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK3(unsigned long offset)176 static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
177 {
178 if (!(
179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
183 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
184 cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
185 return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384;
186 }
187 #else
188 #define CVMX_PCMX_RXMSK3(offset) (CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384)
189 #endif
190 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK4(unsigned long offset)191 static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
192 {
193 if (!(
194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
198 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
199 cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
200 return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384;
201 }
202 #else
203 #define CVMX_PCMX_RXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384)
204 #endif
205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK5(unsigned long offset)206 static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
207 {
208 if (!(
209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
213 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
214 cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
215 return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384;
216 }
217 #else
218 #define CVMX_PCMX_RXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384)
219 #endif
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK6(unsigned long offset)221 static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
222 {
223 if (!(
224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
227 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
228 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
229 cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
230 return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384;
231 }
232 #else
233 #define CVMX_PCMX_RXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384)
234 #endif
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXMSK7(unsigned long offset)236 static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
237 {
238 if (!(
239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
243 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
244 cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
245 return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384;
246 }
247 #else
248 #define CVMX_PCMX_RXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384)
249 #endif
250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_RXSTART(unsigned long offset)251 static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
252 {
253 if (!(
254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
258 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
259 cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
260 return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384;
261 }
262 #else
263 #define CVMX_PCMX_RXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384)
264 #endif
265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TDM_CFG(unsigned long offset)266 static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
267 {
268 if (!(
269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
273 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
274 cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
275 return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384;
276 }
277 #else
278 #define CVMX_PCMX_TDM_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384)
279 #endif
280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TDM_DBG(unsigned long offset)281 static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
282 {
283 if (!(
284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
288 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
289 cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
290 return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384;
291 }
292 #else
293 #define CVMX_PCMX_TDM_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384)
294 #endif
295 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXADDR(unsigned long offset)296 static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
297 {
298 if (!(
299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
302 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
303 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
304 cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
305 return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384;
306 }
307 #else
308 #define CVMX_PCMX_TXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384)
309 #endif
310 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXCNT(unsigned long offset)311 static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
312 {
313 if (!(
314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
317 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
318 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
319 cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
320 return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384;
321 }
322 #else
323 #define CVMX_PCMX_TXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384)
324 #endif
325 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK0(unsigned long offset)326 static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
327 {
328 if (!(
329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
333 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
334 cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
335 return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384;
336 }
337 #else
338 #define CVMX_PCMX_TXMSK0(offset) (CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384)
339 #endif
340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK1(unsigned long offset)341 static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
342 {
343 if (!(
344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
348 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
349 cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
350 return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384;
351 }
352 #else
353 #define CVMX_PCMX_TXMSK1(offset) (CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384)
354 #endif
355 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK2(unsigned long offset)356 static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
357 {
358 if (!(
359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
362 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
363 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
364 cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
365 return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384;
366 }
367 #else
368 #define CVMX_PCMX_TXMSK2(offset) (CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384)
369 #endif
370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK3(unsigned long offset)371 static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
372 {
373 if (!(
374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
378 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
379 cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
380 return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384;
381 }
382 #else
383 #define CVMX_PCMX_TXMSK3(offset) (CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384)
384 #endif
385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK4(unsigned long offset)386 static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
387 {
388 if (!(
389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
392 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
393 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
394 cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
395 return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384;
396 }
397 #else
398 #define CVMX_PCMX_TXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384)
399 #endif
400 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK5(unsigned long offset)401 static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
402 {
403 if (!(
404 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
408 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
409 cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
410 return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384;
411 }
412 #else
413 #define CVMX_PCMX_TXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384)
414 #endif
415 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK6(unsigned long offset)416 static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
417 {
418 if (!(
419 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
420 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
421 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
422 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
423 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
424 cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
425 return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384;
426 }
427 #else
428 #define CVMX_PCMX_TXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384)
429 #endif
430 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXMSK7(unsigned long offset)431 static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
432 {
433 if (!(
434 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
435 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
436 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
437 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
438 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
439 cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
440 return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384;
441 }
442 #else
443 #define CVMX_PCMX_TXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384)
444 #endif
445 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCMX_TXSTART(unsigned long offset)446 static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
447 {
448 if (!(
449 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
450 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
451 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
452 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
453 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
454 cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
455 return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384;
456 }
457 #else
458 #define CVMX_PCMX_TXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384)
459 #endif
460
461 /**
462 * cvmx_pcm#_dma_cfg
463 */
464 union cvmx_pcmx_dma_cfg {
465 uint64_t u64;
466 struct cvmx_pcmx_dma_cfg_s {
467 #ifdef __BIG_ENDIAN_BITFIELD
468 uint64_t rdpend : 1; /**< If 0, no L2C read responses pending | NS
469 1, L2C read responses are outstanding
470 NOTE: When restarting after stopping a running TDM
471 engine, software must wait for RDPEND to read 0
472 before writing PCMn_TDM_CFG[ENABLE] to a 1 */
473 uint64_t reserved_54_62 : 9;
474 uint64_t rxslots : 10; /**< Number of 8-bit slots to receive per frame | NS
475 (number of slots in a receive superframe) */
476 uint64_t reserved_42_43 : 2;
477 uint64_t txslots : 10; /**< Number of 8-bit slots to transmit per frame | NS
478 (number of slots in a transmit superframe) */
479 uint64_t reserved_30_31 : 2;
480 uint64_t rxst : 10; /**< Number of frame writes for interrupt | NS */
481 uint64_t reserved_19_19 : 1;
482 uint64_t useldt : 1; /**< If 0, use LDI command to read from L2C | NS
483 1, use LDT command to read from L2C */
484 uint64_t txrd : 10; /**< Number of frame reads for interrupt | NS */
485 uint64_t fetchsiz : 4; /**< FETCHSIZ+1 timeslots are read when threshold is | NS
486 reached. */
487 uint64_t thresh : 4; /**< If number of bytes remaining in the DMA fifo is <=| NS
488 THRESH, initiate a fetch of timeslot data from the
489 transmit memory region.
490 NOTE: there are only 16B of buffer for each engine
491 so the seetings for FETCHSIZ and THRESH must be
492 such that the buffer will not be overrun:
493
494 THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */
495 #else
496 uint64_t thresh : 4;
497 uint64_t fetchsiz : 4;
498 uint64_t txrd : 10;
499 uint64_t useldt : 1;
500 uint64_t reserved_19_19 : 1;
501 uint64_t rxst : 10;
502 uint64_t reserved_30_31 : 2;
503 uint64_t txslots : 10;
504 uint64_t reserved_42_43 : 2;
505 uint64_t rxslots : 10;
506 uint64_t reserved_54_62 : 9;
507 uint64_t rdpend : 1;
508 #endif
509 } s;
510 struct cvmx_pcmx_dma_cfg_s cn30xx;
511 struct cvmx_pcmx_dma_cfg_s cn31xx;
512 struct cvmx_pcmx_dma_cfg_s cn50xx;
513 struct cvmx_pcmx_dma_cfg_s cn61xx;
514 struct cvmx_pcmx_dma_cfg_s cnf71xx;
515 };
516 typedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t;
517
518 /**
519 * cvmx_pcm#_int_ena
520 */
521 union cvmx_pcmx_int_ena {
522 uint64_t u64;
523 struct cvmx_pcmx_int_ena_s {
524 #ifdef __BIG_ENDIAN_BITFIELD
525 uint64_t reserved_8_63 : 56;
526 uint64_t rxovf : 1; /**< Enable interrupt if RX byte overflows | NS */
527 uint64_t txempty : 1; /**< Enable interrupt on TX byte empty | NS */
528 uint64_t txrd : 1; /**< Enable DMA engine frame read interrupts | NS */
529 uint64_t txwrap : 1; /**< Enable TX region wrap interrupts | NS */
530 uint64_t rxst : 1; /**< Enable DMA engine frame store interrupts | NS */
531 uint64_t rxwrap : 1; /**< Enable RX region wrap interrupts | NS */
532 uint64_t fsyncextra : 1; /**< Enable FSYNC extra interrupts | NS
533 NOTE: FSYNCEXTRA errors are defined as an FSYNC
534 found in the "wrong" spot of a frame given the
535 programming of PCMn_CLK_CFG[NUMSLOTS] and
536 PCMn_CLK_CFG[EXTRABIT]. */
537 uint64_t fsyncmissed : 1; /**< Enable FSYNC missed interrupts | NS
538 NOTE: FSYNCMISSED errors are defined as an FSYNC
539 missing from the correct spot in a frame given
540 the programming of PCMn_CLK_CFG[NUMSLOTS] and
541 PCMn_CLK_CFG[EXTRABIT]. */
542 #else
543 uint64_t fsyncmissed : 1;
544 uint64_t fsyncextra : 1;
545 uint64_t rxwrap : 1;
546 uint64_t rxst : 1;
547 uint64_t txwrap : 1;
548 uint64_t txrd : 1;
549 uint64_t txempty : 1;
550 uint64_t rxovf : 1;
551 uint64_t reserved_8_63 : 56;
552 #endif
553 } s;
554 struct cvmx_pcmx_int_ena_s cn30xx;
555 struct cvmx_pcmx_int_ena_s cn31xx;
556 struct cvmx_pcmx_int_ena_s cn50xx;
557 struct cvmx_pcmx_int_ena_s cn61xx;
558 struct cvmx_pcmx_int_ena_s cnf71xx;
559 };
560 typedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t;
561
562 /**
563 * cvmx_pcm#_int_sum
564 */
565 union cvmx_pcmx_int_sum {
566 uint64_t u64;
567 struct cvmx_pcmx_int_sum_s {
568 #ifdef __BIG_ENDIAN_BITFIELD
569 uint64_t reserved_8_63 : 56;
570 uint64_t rxovf : 1; /**< RX byte overflowed | NS */
571 uint64_t txempty : 1; /**< TX byte was empty when sampled | NS */
572 uint64_t txrd : 1; /**< DMA engine frame read interrupt occurred | NS */
573 uint64_t txwrap : 1; /**< TX region wrap interrupt occurred | NS */
574 uint64_t rxst : 1; /**< DMA engine frame store interrupt occurred | NS */
575 uint64_t rxwrap : 1; /**< RX region wrap interrupt occurred | NS */
576 uint64_t fsyncextra : 1; /**< FSYNC extra interrupt occurred | NS */
577 uint64_t fsyncmissed : 1; /**< FSYNC missed interrupt occurred | NS */
578 #else
579 uint64_t fsyncmissed : 1;
580 uint64_t fsyncextra : 1;
581 uint64_t rxwrap : 1;
582 uint64_t rxst : 1;
583 uint64_t txwrap : 1;
584 uint64_t txrd : 1;
585 uint64_t txempty : 1;
586 uint64_t rxovf : 1;
587 uint64_t reserved_8_63 : 56;
588 #endif
589 } s;
590 struct cvmx_pcmx_int_sum_s cn30xx;
591 struct cvmx_pcmx_int_sum_s cn31xx;
592 struct cvmx_pcmx_int_sum_s cn50xx;
593 struct cvmx_pcmx_int_sum_s cn61xx;
594 struct cvmx_pcmx_int_sum_s cnf71xx;
595 };
596 typedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t;
597
598 /**
599 * cvmx_pcm#_rxaddr
600 */
601 union cvmx_pcmx_rxaddr {
602 uint64_t u64;
603 struct cvmx_pcmx_rxaddr_s {
604 #ifdef __BIG_ENDIAN_BITFIELD
605 uint64_t reserved_36_63 : 28;
606 uint64_t addr : 36; /**< Address of the next write to the receive memory | NS
607 region */
608 #else
609 uint64_t addr : 36;
610 uint64_t reserved_36_63 : 28;
611 #endif
612 } s;
613 struct cvmx_pcmx_rxaddr_s cn30xx;
614 struct cvmx_pcmx_rxaddr_s cn31xx;
615 struct cvmx_pcmx_rxaddr_s cn50xx;
616 struct cvmx_pcmx_rxaddr_s cn61xx;
617 struct cvmx_pcmx_rxaddr_s cnf71xx;
618 };
619 typedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t;
620
621 /**
622 * cvmx_pcm#_rxcnt
623 */
624 union cvmx_pcmx_rxcnt {
625 uint64_t u64;
626 struct cvmx_pcmx_rxcnt_s {
627 #ifdef __BIG_ENDIAN_BITFIELD
628 uint64_t reserved_16_63 : 48;
629 uint64_t cnt : 16; /**< Number of superframes in receive memory region | NS */
630 #else
631 uint64_t cnt : 16;
632 uint64_t reserved_16_63 : 48;
633 #endif
634 } s;
635 struct cvmx_pcmx_rxcnt_s cn30xx;
636 struct cvmx_pcmx_rxcnt_s cn31xx;
637 struct cvmx_pcmx_rxcnt_s cn50xx;
638 struct cvmx_pcmx_rxcnt_s cn61xx;
639 struct cvmx_pcmx_rxcnt_s cnf71xx;
640 };
641 typedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t;
642
643 /**
644 * cvmx_pcm#_rxmsk0
645 */
646 union cvmx_pcmx_rxmsk0 {
647 uint64_t u64;
648 struct cvmx_pcmx_rxmsk0_s {
649 #ifdef __BIG_ENDIAN_BITFIELD
650 uint64_t mask : 64; /**< Receive mask bits for slots 63 to 0 | NS
651 (1 means transmit, 0 means don't transmit) */
652 #else
653 uint64_t mask : 64;
654 #endif
655 } s;
656 struct cvmx_pcmx_rxmsk0_s cn30xx;
657 struct cvmx_pcmx_rxmsk0_s cn31xx;
658 struct cvmx_pcmx_rxmsk0_s cn50xx;
659 struct cvmx_pcmx_rxmsk0_s cn61xx;
660 struct cvmx_pcmx_rxmsk0_s cnf71xx;
661 };
662 typedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t;
663
664 /**
665 * cvmx_pcm#_rxmsk1
666 */
667 union cvmx_pcmx_rxmsk1 {
668 uint64_t u64;
669 struct cvmx_pcmx_rxmsk1_s {
670 #ifdef __BIG_ENDIAN_BITFIELD
671 uint64_t mask : 64; /**< Receive mask bits for slots 127 to 64 | NS
672 (1 means transmit, 0 means don't transmit) */
673 #else
674 uint64_t mask : 64;
675 #endif
676 } s;
677 struct cvmx_pcmx_rxmsk1_s cn30xx;
678 struct cvmx_pcmx_rxmsk1_s cn31xx;
679 struct cvmx_pcmx_rxmsk1_s cn50xx;
680 struct cvmx_pcmx_rxmsk1_s cn61xx;
681 struct cvmx_pcmx_rxmsk1_s cnf71xx;
682 };
683 typedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t;
684
685 /**
686 * cvmx_pcm#_rxmsk2
687 */
688 union cvmx_pcmx_rxmsk2 {
689 uint64_t u64;
690 struct cvmx_pcmx_rxmsk2_s {
691 #ifdef __BIG_ENDIAN_BITFIELD
692 uint64_t mask : 64; /**< Receive mask bits for slots 191 to 128 | NS
693 (1 means transmit, 0 means don't transmit) */
694 #else
695 uint64_t mask : 64;
696 #endif
697 } s;
698 struct cvmx_pcmx_rxmsk2_s cn30xx;
699 struct cvmx_pcmx_rxmsk2_s cn31xx;
700 struct cvmx_pcmx_rxmsk2_s cn50xx;
701 struct cvmx_pcmx_rxmsk2_s cn61xx;
702 struct cvmx_pcmx_rxmsk2_s cnf71xx;
703 };
704 typedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t;
705
706 /**
707 * cvmx_pcm#_rxmsk3
708 */
709 union cvmx_pcmx_rxmsk3 {
710 uint64_t u64;
711 struct cvmx_pcmx_rxmsk3_s {
712 #ifdef __BIG_ENDIAN_BITFIELD
713 uint64_t mask : 64; /**< Receive mask bits for slots 255 to 192 | NS
714 (1 means transmit, 0 means don't transmit) */
715 #else
716 uint64_t mask : 64;
717 #endif
718 } s;
719 struct cvmx_pcmx_rxmsk3_s cn30xx;
720 struct cvmx_pcmx_rxmsk3_s cn31xx;
721 struct cvmx_pcmx_rxmsk3_s cn50xx;
722 struct cvmx_pcmx_rxmsk3_s cn61xx;
723 struct cvmx_pcmx_rxmsk3_s cnf71xx;
724 };
725 typedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t;
726
727 /**
728 * cvmx_pcm#_rxmsk4
729 */
730 union cvmx_pcmx_rxmsk4 {
731 uint64_t u64;
732 struct cvmx_pcmx_rxmsk4_s {
733 #ifdef __BIG_ENDIAN_BITFIELD
734 uint64_t mask : 64; /**< Receive mask bits for slots 319 to 256 | NS
735 (1 means transmit, 0 means don't transmit) */
736 #else
737 uint64_t mask : 64;
738 #endif
739 } s;
740 struct cvmx_pcmx_rxmsk4_s cn30xx;
741 struct cvmx_pcmx_rxmsk4_s cn31xx;
742 struct cvmx_pcmx_rxmsk4_s cn50xx;
743 struct cvmx_pcmx_rxmsk4_s cn61xx;
744 struct cvmx_pcmx_rxmsk4_s cnf71xx;
745 };
746 typedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t;
747
748 /**
749 * cvmx_pcm#_rxmsk5
750 */
751 union cvmx_pcmx_rxmsk5 {
752 uint64_t u64;
753 struct cvmx_pcmx_rxmsk5_s {
754 #ifdef __BIG_ENDIAN_BITFIELD
755 uint64_t mask : 64; /**< Receive mask bits for slots 383 to 320 | NS
756 (1 means transmit, 0 means don't transmit) */
757 #else
758 uint64_t mask : 64;
759 #endif
760 } s;
761 struct cvmx_pcmx_rxmsk5_s cn30xx;
762 struct cvmx_pcmx_rxmsk5_s cn31xx;
763 struct cvmx_pcmx_rxmsk5_s cn50xx;
764 struct cvmx_pcmx_rxmsk5_s cn61xx;
765 struct cvmx_pcmx_rxmsk5_s cnf71xx;
766 };
767 typedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t;
768
769 /**
770 * cvmx_pcm#_rxmsk6
771 */
772 union cvmx_pcmx_rxmsk6 {
773 uint64_t u64;
774 struct cvmx_pcmx_rxmsk6_s {
775 #ifdef __BIG_ENDIAN_BITFIELD
776 uint64_t mask : 64; /**< Receive mask bits for slots 447 to 384 | NS
777 (1 means transmit, 0 means don't transmit) */
778 #else
779 uint64_t mask : 64;
780 #endif
781 } s;
782 struct cvmx_pcmx_rxmsk6_s cn30xx;
783 struct cvmx_pcmx_rxmsk6_s cn31xx;
784 struct cvmx_pcmx_rxmsk6_s cn50xx;
785 struct cvmx_pcmx_rxmsk6_s cn61xx;
786 struct cvmx_pcmx_rxmsk6_s cnf71xx;
787 };
788 typedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t;
789
790 /**
791 * cvmx_pcm#_rxmsk7
792 */
793 union cvmx_pcmx_rxmsk7 {
794 uint64_t u64;
795 struct cvmx_pcmx_rxmsk7_s {
796 #ifdef __BIG_ENDIAN_BITFIELD
797 uint64_t mask : 64; /**< Receive mask bits for slots 511 to 448 | NS
798 (1 means transmit, 0 means don't transmit) */
799 #else
800 uint64_t mask : 64;
801 #endif
802 } s;
803 struct cvmx_pcmx_rxmsk7_s cn30xx;
804 struct cvmx_pcmx_rxmsk7_s cn31xx;
805 struct cvmx_pcmx_rxmsk7_s cn50xx;
806 struct cvmx_pcmx_rxmsk7_s cn61xx;
807 struct cvmx_pcmx_rxmsk7_s cnf71xx;
808 };
809 typedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t;
810
811 /**
812 * cvmx_pcm#_rxstart
813 */
814 union cvmx_pcmx_rxstart {
815 uint64_t u64;
816 struct cvmx_pcmx_rxstart_s {
817 #ifdef __BIG_ENDIAN_BITFIELD
818 uint64_t reserved_36_63 : 28;
819 uint64_t addr : 33; /**< Starting address for the receive memory region | NS */
820 uint64_t reserved_0_2 : 3;
821 #else
822 uint64_t reserved_0_2 : 3;
823 uint64_t addr : 33;
824 uint64_t reserved_36_63 : 28;
825 #endif
826 } s;
827 struct cvmx_pcmx_rxstart_s cn30xx;
828 struct cvmx_pcmx_rxstart_s cn31xx;
829 struct cvmx_pcmx_rxstart_s cn50xx;
830 struct cvmx_pcmx_rxstart_s cn61xx;
831 struct cvmx_pcmx_rxstart_s cnf71xx;
832 };
833 typedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t;
834
835 /**
836 * cvmx_pcm#_tdm_cfg
837 */
838 union cvmx_pcmx_tdm_cfg {
839 uint64_t u64;
840 struct cvmx_pcmx_tdm_cfg_s {
841 #ifdef __BIG_ENDIAN_BITFIELD
842 uint64_t drvtim : 16; /**< Number of ECLKs from start of bit time to stop | NS
843 driving last bit of timeslot (if not driving next
844 timeslot) */
845 uint64_t samppt : 16; /**< Number of ECLKs from start of bit time to sample | NS
846 data bit. */
847 uint64_t reserved_3_31 : 29;
848 uint64_t lsbfirst : 1; /**< If 0, shift/receive MSB first | NS
849 1, shift/receive LSB first */
850 uint64_t useclk1 : 1; /**< If 0, this PCM is based on BCLK/FSYNC0 | NS
851 1, this PCM is based on BCLK/FSYNC1 */
852 uint64_t enable : 1; /**< If 1, PCM is enabled, otherwise pins are GPIOs | NS
853 NOTE: when TDM is disabled by detection of an
854 FSYNC error all transmission and reception is
855 halted. In addition, PCMn_TX/RXADDR are updated
856 to point to the position at which the error was
857 detected. */
858 #else
859 uint64_t enable : 1;
860 uint64_t useclk1 : 1;
861 uint64_t lsbfirst : 1;
862 uint64_t reserved_3_31 : 29;
863 uint64_t samppt : 16;
864 uint64_t drvtim : 16;
865 #endif
866 } s;
867 struct cvmx_pcmx_tdm_cfg_s cn30xx;
868 struct cvmx_pcmx_tdm_cfg_s cn31xx;
869 struct cvmx_pcmx_tdm_cfg_s cn50xx;
870 struct cvmx_pcmx_tdm_cfg_s cn61xx;
871 struct cvmx_pcmx_tdm_cfg_s cnf71xx;
872 };
873 typedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t;
874
875 /**
876 * cvmx_pcm#_tdm_dbg
877 */
878 union cvmx_pcmx_tdm_dbg {
879 uint64_t u64;
880 struct cvmx_pcmx_tdm_dbg_s {
881 #ifdef __BIG_ENDIAN_BITFIELD
882 uint64_t debuginfo : 64; /**< Miscellaneous debug information | NS */
883 #else
884 uint64_t debuginfo : 64;
885 #endif
886 } s;
887 struct cvmx_pcmx_tdm_dbg_s cn30xx;
888 struct cvmx_pcmx_tdm_dbg_s cn31xx;
889 struct cvmx_pcmx_tdm_dbg_s cn50xx;
890 struct cvmx_pcmx_tdm_dbg_s cn61xx;
891 struct cvmx_pcmx_tdm_dbg_s cnf71xx;
892 };
893 typedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t;
894
895 /**
896 * cvmx_pcm#_txaddr
897 */
898 union cvmx_pcmx_txaddr {
899 uint64_t u64;
900 struct cvmx_pcmx_txaddr_s {
901 #ifdef __BIG_ENDIAN_BITFIELD
902 uint64_t reserved_36_63 : 28;
903 uint64_t addr : 33; /**< Address of the next read from the transmit memory | NS
904 region */
905 uint64_t fram : 3; /**< Frame offset | NS
906 NOTE: this is used to extract the correct byte from
907 each 64b word read from the transmit memory region */
908 #else
909 uint64_t fram : 3;
910 uint64_t addr : 33;
911 uint64_t reserved_36_63 : 28;
912 #endif
913 } s;
914 struct cvmx_pcmx_txaddr_s cn30xx;
915 struct cvmx_pcmx_txaddr_s cn31xx;
916 struct cvmx_pcmx_txaddr_s cn50xx;
917 struct cvmx_pcmx_txaddr_s cn61xx;
918 struct cvmx_pcmx_txaddr_s cnf71xx;
919 };
920 typedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t;
921
922 /**
923 * cvmx_pcm#_txcnt
924 */
925 union cvmx_pcmx_txcnt {
926 uint64_t u64;
927 struct cvmx_pcmx_txcnt_s {
928 #ifdef __BIG_ENDIAN_BITFIELD
929 uint64_t reserved_16_63 : 48;
930 uint64_t cnt : 16; /**< Number of superframes in transmit memory region | NS */
931 #else
932 uint64_t cnt : 16;
933 uint64_t reserved_16_63 : 48;
934 #endif
935 } s;
936 struct cvmx_pcmx_txcnt_s cn30xx;
937 struct cvmx_pcmx_txcnt_s cn31xx;
938 struct cvmx_pcmx_txcnt_s cn50xx;
939 struct cvmx_pcmx_txcnt_s cn61xx;
940 struct cvmx_pcmx_txcnt_s cnf71xx;
941 };
942 typedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t;
943
944 /**
945 * cvmx_pcm#_txmsk0
946 */
947 union cvmx_pcmx_txmsk0 {
948 uint64_t u64;
949 struct cvmx_pcmx_txmsk0_s {
950 #ifdef __BIG_ENDIAN_BITFIELD
951 uint64_t mask : 64; /**< Transmit mask bits for slots 63 to 0 | NS
952 (1 means transmit, 0 means don't transmit) */
953 #else
954 uint64_t mask : 64;
955 #endif
956 } s;
957 struct cvmx_pcmx_txmsk0_s cn30xx;
958 struct cvmx_pcmx_txmsk0_s cn31xx;
959 struct cvmx_pcmx_txmsk0_s cn50xx;
960 struct cvmx_pcmx_txmsk0_s cn61xx;
961 struct cvmx_pcmx_txmsk0_s cnf71xx;
962 };
963 typedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t;
964
965 /**
966 * cvmx_pcm#_txmsk1
967 */
968 union cvmx_pcmx_txmsk1 {
969 uint64_t u64;
970 struct cvmx_pcmx_txmsk1_s {
971 #ifdef __BIG_ENDIAN_BITFIELD
972 uint64_t mask : 64; /**< Transmit mask bits for slots 127 to 64 | NS
973 (1 means transmit, 0 means don't transmit) */
974 #else
975 uint64_t mask : 64;
976 #endif
977 } s;
978 struct cvmx_pcmx_txmsk1_s cn30xx;
979 struct cvmx_pcmx_txmsk1_s cn31xx;
980 struct cvmx_pcmx_txmsk1_s cn50xx;
981 struct cvmx_pcmx_txmsk1_s cn61xx;
982 struct cvmx_pcmx_txmsk1_s cnf71xx;
983 };
984 typedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t;
985
986 /**
987 * cvmx_pcm#_txmsk2
988 */
989 union cvmx_pcmx_txmsk2 {
990 uint64_t u64;
991 struct cvmx_pcmx_txmsk2_s {
992 #ifdef __BIG_ENDIAN_BITFIELD
993 uint64_t mask : 64; /**< Transmit mask bits for slots 191 to 128 | NS
994 (1 means transmit, 0 means don't transmit) */
995 #else
996 uint64_t mask : 64;
997 #endif
998 } s;
999 struct cvmx_pcmx_txmsk2_s cn30xx;
1000 struct cvmx_pcmx_txmsk2_s cn31xx;
1001 struct cvmx_pcmx_txmsk2_s cn50xx;
1002 struct cvmx_pcmx_txmsk2_s cn61xx;
1003 struct cvmx_pcmx_txmsk2_s cnf71xx;
1004 };
1005 typedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t;
1006
1007 /**
1008 * cvmx_pcm#_txmsk3
1009 */
1010 union cvmx_pcmx_txmsk3 {
1011 uint64_t u64;
1012 struct cvmx_pcmx_txmsk3_s {
1013 #ifdef __BIG_ENDIAN_BITFIELD
1014 uint64_t mask : 64; /**< Transmit mask bits for slots 255 to 192 | NS
1015 (1 means transmit, 0 means don't transmit) */
1016 #else
1017 uint64_t mask : 64;
1018 #endif
1019 } s;
1020 struct cvmx_pcmx_txmsk3_s cn30xx;
1021 struct cvmx_pcmx_txmsk3_s cn31xx;
1022 struct cvmx_pcmx_txmsk3_s cn50xx;
1023 struct cvmx_pcmx_txmsk3_s cn61xx;
1024 struct cvmx_pcmx_txmsk3_s cnf71xx;
1025 };
1026 typedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t;
1027
1028 /**
1029 * cvmx_pcm#_txmsk4
1030 */
1031 union cvmx_pcmx_txmsk4 {
1032 uint64_t u64;
1033 struct cvmx_pcmx_txmsk4_s {
1034 #ifdef __BIG_ENDIAN_BITFIELD
1035 uint64_t mask : 64; /**< Transmit mask bits for slots 319 to 256 | NS
1036 (1 means transmit, 0 means don't transmit) */
1037 #else
1038 uint64_t mask : 64;
1039 #endif
1040 } s;
1041 struct cvmx_pcmx_txmsk4_s cn30xx;
1042 struct cvmx_pcmx_txmsk4_s cn31xx;
1043 struct cvmx_pcmx_txmsk4_s cn50xx;
1044 struct cvmx_pcmx_txmsk4_s cn61xx;
1045 struct cvmx_pcmx_txmsk4_s cnf71xx;
1046 };
1047 typedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t;
1048
1049 /**
1050 * cvmx_pcm#_txmsk5
1051 */
1052 union cvmx_pcmx_txmsk5 {
1053 uint64_t u64;
1054 struct cvmx_pcmx_txmsk5_s {
1055 #ifdef __BIG_ENDIAN_BITFIELD
1056 uint64_t mask : 64; /**< Transmit mask bits for slots 383 to 320 | NS
1057 (1 means transmit, 0 means don't transmit) */
1058 #else
1059 uint64_t mask : 64;
1060 #endif
1061 } s;
1062 struct cvmx_pcmx_txmsk5_s cn30xx;
1063 struct cvmx_pcmx_txmsk5_s cn31xx;
1064 struct cvmx_pcmx_txmsk5_s cn50xx;
1065 struct cvmx_pcmx_txmsk5_s cn61xx;
1066 struct cvmx_pcmx_txmsk5_s cnf71xx;
1067 };
1068 typedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t;
1069
1070 /**
1071 * cvmx_pcm#_txmsk6
1072 */
1073 union cvmx_pcmx_txmsk6 {
1074 uint64_t u64;
1075 struct cvmx_pcmx_txmsk6_s {
1076 #ifdef __BIG_ENDIAN_BITFIELD
1077 uint64_t mask : 64; /**< Transmit mask bits for slots 447 to 384 | NS
1078 (1 means transmit, 0 means don't transmit) */
1079 #else
1080 uint64_t mask : 64;
1081 #endif
1082 } s;
1083 struct cvmx_pcmx_txmsk6_s cn30xx;
1084 struct cvmx_pcmx_txmsk6_s cn31xx;
1085 struct cvmx_pcmx_txmsk6_s cn50xx;
1086 struct cvmx_pcmx_txmsk6_s cn61xx;
1087 struct cvmx_pcmx_txmsk6_s cnf71xx;
1088 };
1089 typedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t;
1090
1091 /**
1092 * cvmx_pcm#_txmsk7
1093 */
1094 union cvmx_pcmx_txmsk7 {
1095 uint64_t u64;
1096 struct cvmx_pcmx_txmsk7_s {
1097 #ifdef __BIG_ENDIAN_BITFIELD
1098 uint64_t mask : 64; /**< Transmit mask bits for slots 511 to 448 | NS
1099 (1 means transmit, 0 means don't transmit) */
1100 #else
1101 uint64_t mask : 64;
1102 #endif
1103 } s;
1104 struct cvmx_pcmx_txmsk7_s cn30xx;
1105 struct cvmx_pcmx_txmsk7_s cn31xx;
1106 struct cvmx_pcmx_txmsk7_s cn50xx;
1107 struct cvmx_pcmx_txmsk7_s cn61xx;
1108 struct cvmx_pcmx_txmsk7_s cnf71xx;
1109 };
1110 typedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t;
1111
1112 /**
1113 * cvmx_pcm#_txstart
1114 */
1115 union cvmx_pcmx_txstart {
1116 uint64_t u64;
1117 struct cvmx_pcmx_txstart_s {
1118 #ifdef __BIG_ENDIAN_BITFIELD
1119 uint64_t reserved_36_63 : 28;
1120 uint64_t addr : 33; /**< Starting address for the transmit memory region | NS */
1121 uint64_t reserved_0_2 : 3;
1122 #else
1123 uint64_t reserved_0_2 : 3;
1124 uint64_t addr : 33;
1125 uint64_t reserved_36_63 : 28;
1126 #endif
1127 } s;
1128 struct cvmx_pcmx_txstart_s cn30xx;
1129 struct cvmx_pcmx_txstart_s cn31xx;
1130 struct cvmx_pcmx_txstart_s cn50xx;
1131 struct cvmx_pcmx_txstart_s cn61xx;
1132 struct cvmx_pcmx_txstart_s cnf71xx;
1133 };
1134 typedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t;
1135
1136 #endif
1137