1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2013 - 2015 Intel Corporation 3 */ 4 5 #ifndef _FM10K_TYPE_H_ 6 #define _FM10K_TYPE_H_ 7 8 /* forward declaration */ 9 struct fm10k_hw; 10 11 #include "fm10k_osdep.h" 12 #include "fm10k_mbx.h" 13 14 #define FM10K_INTEL_VENDOR_ID 0x8086 15 #define FM10K_DEV_ID_PF 0x15A4 16 #define FM10K_DEV_ID_VF 0x15A5 17 #ifdef BOULDER_RAPIDS_HW 18 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0 19 #endif /* BOULDER_RAPIDS_HW */ 20 #ifdef ATWOOD_CHANNEL_HW 21 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5 22 #endif /* ATWOOD_CHANNEL_HW */ 23 24 #ifndef LINUX_MACROS 25 #ifndef BIT 26 #define BIT(a) (1UL << (a)) 27 #endif 28 #endif /* LINUX_MACROS */ 29 30 #define FM10K_MAX_QUEUES 256 31 #define FM10K_MAX_QUEUES_PF 128 32 #define FM10K_MAX_QUEUES_POOL 16 33 34 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull 35 #define FM10K_STAT_VALID 0x80000000 36 37 /* PCI Bus Info */ 38 #define FM10K_PCIE_LINK_CAP 0x7C 39 #define FM10K_PCIE_LINK_STATUS 0x82 40 #define FM10K_PCIE_LINK_WIDTH 0x3F0 41 #define FM10K_PCIE_LINK_WIDTH_1 0x10 42 #define FM10K_PCIE_LINK_WIDTH_2 0x20 43 #define FM10K_PCIE_LINK_WIDTH_4 0x40 44 #define FM10K_PCIE_LINK_WIDTH_8 0x80 45 #define FM10K_PCIE_LINK_SPEED 0xF 46 #define FM10K_PCIE_LINK_SPEED_2500 0x1 47 #define FM10K_PCIE_LINK_SPEED_5000 0x2 48 #define FM10K_PCIE_LINK_SPEED_8000 0x3 49 50 /* PCIe payload size */ 51 #define FM10K_PCIE_DEV_CAP 0x74 52 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07 53 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00 54 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01 55 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02 56 #define FM10K_PCIE_DEV_CTRL 0x78 57 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0 58 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00 59 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20 60 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40 61 62 /* PCIe MSI-X Capability info */ 63 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2 64 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF 65 #define FM10K_MAX_MSIX_VECTORS 256 66 #define FM10K_MAX_VECTORS_PF 256 67 #define FM10K_MAX_VECTORS_POOL 32 68 69 /* PCIe SR-IOV Info */ 70 #define FM10K_PCIE_SRIOV_CTRL 0x190 71 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10 72 73 #define FM10K_SUCCESS 0 74 #define FM10K_ERR_DEVICE_NOT_SUPPORTED -1 75 #define FM10K_ERR_PARAM -2 76 #define FM10K_ERR_NO_RESOURCES -3 77 #define FM10K_ERR_REQUESTS_PENDING -4 78 #define FM10K_ERR_RESET_REQUESTED -5 79 #define FM10K_ERR_DMA_PENDING -6 80 #define FM10K_ERR_RESET_FAILED -7 81 #define FM10K_ERR_INVALID_MAC_ADDR -8 82 #define FM10K_ERR_INVALID_VALUE -9 83 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF 84 85 #define UNREFERENCED_XPARAMETER 86 #define UNREFERENCED_1PARAMETER(_p) (_p) 87 #define UNREFERENCED_2PARAMETER(_p, _q) do { (_p); (_q); } while (0) 88 #define UNREFERENCED_3PARAMETER(_p, _q, _r) do { (_p); (_q); (_r); } while (0) 89 90 /* Start of PF registers */ 91 #define FM10K_CTRL 0x0000 92 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004 93 94 #define FM10K_CTRL_EXT 0x0001 95 #define FM10K_GCR 0x0003 96 #define FM10K_GCR_EXT 0x0005 97 98 /* Interrupt control registers */ 99 #define FM10K_EICR 0x0006 100 #define FM10K_EICR_PCA_FAULT 0x00000001 101 #define FM10K_EICR_THI_FAULT 0x00000004 102 #define FM10K_EICR_FUM_FAULT 0x00000020 103 #define FM10K_EICR_FAULT_MASK 0x0000003F 104 #define FM10K_EICR_MAILBOX 0x00000040 105 #define FM10K_EICR_SWITCHREADY 0x00000080 106 #define FM10K_EICR_SWITCHNOTREADY 0x00000100 107 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200 108 #define FM10K_EICR_SRAMERROR 0x00000400 109 #define FM10K_EICR_VFLR 0x00000800 110 #define FM10K_EICR_MAXHOLDTIME 0x00001000 111 #define FM10K_EIMR 0x0007 112 #define FM10K_EIMR_PCA_FAULT 0x00000001 113 #define FM10K_EIMR_THI_FAULT 0x00000010 114 #define FM10K_EIMR_FUM_FAULT 0x00000400 115 #define FM10K_EIMR_MAILBOX 0x00001000 116 #define FM10K_EIMR_SWITCHREADY 0x00004000 117 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000 118 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000 119 #define FM10K_EIMR_SRAMERROR 0x00100000 120 #define FM10K_EIMR_VFLR 0x00400000 121 #define FM10K_EIMR_MAXHOLDTIME 0x01000000 122 #define FM10K_EIMR_ALL 0x55555555 123 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0) 124 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1) 125 #define FM10K_FAULT_ADDR_LO 0x0 126 #define FM10K_FAULT_ADDR_HI 0x1 127 #define FM10K_FAULT_SPECINFO 0x2 128 #define FM10K_FAULT_FUNC 0x3 129 #define FM10K_FAULT_SIZE 0x4 130 #define FM10K_FAULT_FUNC_VALID 0x00008000 131 #define FM10K_FAULT_FUNC_PF 0x00004000 132 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00 133 #define FM10K_FAULT_FUNC_VF_SHIFT 8 134 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF 135 136 #define FM10K_PCA_FAULT 0x0008 137 #define FM10K_THI_FAULT 0x0010 138 #define FM10K_FUM_FAULT 0x001C 139 140 /* Rx queue timeout indicator */ 141 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020) 142 143 /* Switch Manager info */ 144 #define FM10K_SM_AREA(_n) ((_n) + 0x0028) 145 146 /* GLORT mapping registers */ 147 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030) 148 #define FM10K_DGLORT_COUNT 8 149 #define FM10K_DGLORTMAP_MASK_SHIFT 16 150 #define FM10K_DGLORTMAP_ANY 0x00000000 151 #define FM10K_DGLORTMAP_NONE 0x0000FFFF 152 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000 153 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038) 154 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4 155 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7 156 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14 157 #define FM10K_DGLORTDEC_QBASE_SHIFT 16 158 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24 159 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000 160 #define FM10K_TUNNEL_CFG 0x0040 161 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16 162 #define FM10K_TUNNEL_CFG_GENEVE 0x0041 163 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050) 164 #define FM10K_SWPRI_MAX 16 165 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800) 166 #define FM10K_RSSRK_SIZE 10 167 #define FM10K_RSSRK_ENTRIES_PER_REG 4 168 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000) 169 #define FM10K_RETA_SIZE 32 170 #define FM10K_RETA_ENTRIES_PER_REG 4 171 #define FM10K_MAX_RSS_INDICES 128 172 173 /* Rate limiting registers */ 174 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000) 175 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF 176 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040) 177 #define FM10K_TC_MAXCREDIT_64K 0x00010000 178 #define FM10K_TC_RATE(_n) ((_n) + 0x2080) 179 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF 180 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000 181 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000 182 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000 183 184 /* DMA control registers */ 185 #define FM10K_DMA_CTRL 0x20C3 186 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001 187 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008 188 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010 189 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080 190 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100 191 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9 192 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000 193 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000 194 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000 195 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000 196 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000 197 #define FM10K_DMA_CTRL_32_DESC 0x00000000 198 199 #define FM10K_DMA_CTRL2 0x20C4 200 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000 201 202 /* TSO flags configuration 203 * First packet contains all flags except for fin and psh 204 * Middle packet contains only urg and ack 205 * Last packet contains urg, ack, fin, and psh 206 */ 207 #define FM10K_TSO_FLAGS_LOW 0x00300FF6 208 #define FM10K_TSO_FLAGS_HI 0x00000039 209 #define FM10K_DTXTCPFLGL 0x20C5 210 #define FM10K_DTXTCPFLGH 0x20C6 211 212 #define FM10K_TPH_CTRL 0x20C7 213 #define FM10K_MRQC(_n) ((_n) + 0x2100) 214 #define FM10K_MRQC_TCP_IPV4 0x00000001 215 #define FM10K_MRQC_IPV4 0x00000002 216 #define FM10K_MRQC_IPV6 0x00000010 217 #define FM10K_MRQC_TCP_IPV6 0x00000020 218 #define FM10K_MRQC_UDP_IPV4 0x00000040 219 #define FM10K_MRQC_UDP_IPV6 0x00000080 220 221 #define FM10K_TQMAP(_n) ((_n) + 0x2800) 222 #define FM10K_TQMAP_TABLE_SIZE 2048 223 #define FM10K_RQMAP(_n) ((_n) + 0x3000) 224 225 /* Hardware Statistics */ 226 #define FM10K_STATS_TIMEOUT 0x3800 227 #define FM10K_STATS_UR 0x3801 228 #define FM10K_STATS_CA 0x3802 229 #define FM10K_STATS_UM 0x3803 230 #define FM10K_STATS_XEC 0x3804 231 #define FM10K_STATS_VLAN_DROP 0x3805 232 #define FM10K_STATS_LOOPBACK_DROP 0x3806 233 #define FM10K_STATS_NODESC_DROP 0x3807 234 235 /* Timesync registers */ 236 #define FM10K_SYSTIME 0x3814 237 #define FM10K_SYSTIME_CFG 0x3818 238 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F 239 240 /* PCIe state registers */ 241 #define FM10K_PHYADDR 0x381C 242 243 /* Rx ring registers */ 244 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000) 245 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001) 246 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002) 247 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003) 248 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020 249 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200 250 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000 251 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000 252 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004) 253 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005) 254 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006) 255 #define FM10K_RXQCTL_ENABLE 0x00000001 256 #define FM10K_RXQCTL_PF 0x000000FC 257 #define FM10K_RXQCTL_VF_SHIFT 2 258 #define FM10K_RXQCTL_VF 0x00000100 259 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF) 260 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007) 261 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001 262 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200 263 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008) 264 #define FM10K_RXINT_TIMER_SHIFT 8 265 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009) 266 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */ 267 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000 268 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000 269 270 /* Rx Statistics */ 271 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A) 272 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B) 273 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C) 274 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D) 275 276 /* Rx GLORT register */ 277 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E) 278 279 /* Tx ring registers */ 280 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000) 281 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001) 282 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002) 283 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR) 284 * scale which is based on the PCIe speed but the speed information in the PCI 285 * configuration space may not be accurate. The PF already knows the ITR scale 286 * but there is no defined method to pass that information from the PF to the 287 * VF. This is accomplished during VF initialization by temporarily co-opting 288 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for 289 * the VF to retrieve before the VF needs to use the TDLEN register for its 290 * intended purpose, i.e. before the Tx resources are allocated. 291 */ 292 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9 293 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00 294 #define FM10K_TDLEN_ITR_SCALE_GEN1 2 295 #define FM10K_TDLEN_ITR_SCALE_GEN2 1 296 #define FM10K_TDLEN_ITR_SCALE_GEN3 0 297 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003) 298 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020 299 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200 300 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800 301 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000 302 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004) 303 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005) 304 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006) 305 #define FM10K_TXDCTL_ENABLE 0x00004000 306 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16 307 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007) 308 #define FM10K_TXQCTL_PF 0x0000003F 309 #define FM10K_TXQCTL_VF 0x00000040 310 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF) 311 #define FM10K_TXQCTL_PC_SHIFT 7 312 #define FM10K_TXQCTL_PC_MASK 0x00000380 313 #define FM10K_TXQCTL_TC_SHIFT 10 314 #define FM10K_TXQCTL_VID_SHIFT 16 315 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000 316 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000 317 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008) 318 #define FM10K_TXINT_TIMER_SHIFT 8 319 320 /* Tx Statistics */ 321 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009) 322 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A) 323 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B) 324 325 /* Tx Push registers */ 326 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C) 327 #define FM10K_TQDLOC_BASE_32_DESC 0x08 328 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000 329 330 /* Tx GLORT registers */ 331 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D) 332 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E) 333 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001 334 335 /* Interrupt moderation and control registers */ 336 #define FM10K_INT_MAP(_n) ((_n) + 0x10080) 337 #define FM10K_INT_MAP_TIMER0 0x00000000 338 #define FM10K_INT_MAP_TIMER1 0x00000100 339 #define FM10K_INT_MAP_IMMEDIATE 0x00000200 340 #define FM10K_INT_MAP_DISABLE 0x00000300 341 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003) 342 #define FM10K_INT_CTRL 0x12000 343 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400 344 #define FM10K_ITR(_n) ((_n) + 0x12400) 345 #define FM10K_ITR_INTERVAL1_SHIFT 12 346 #define FM10K_ITR_PENDING2 0x10000000 347 #define FM10K_ITR_AUTOMASK 0x20000000 348 #define FM10K_ITR_MASK_SET 0x40000000 349 #define FM10K_ITR_MASK_CLEAR 0x80000000 350 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800) 351 #define FM10K_ITR_REG_COUNT 768 352 #define FM10K_ITR_REG_COUNT_PF 256 353 354 /* Switch manager interrupt registers */ 355 #define FM10K_IP 0x13000 356 #define FM10K_IP_NOTINRESET 0x00000100 357 #define FM10K_SRAM_IP 0x13003 358 359 /* VLAN registers */ 360 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000) 361 #define FM10K_VLAN_TABLE_SIZE 128 362 363 /* VLAN specific message offsets */ 364 #define FM10K_VLAN_TABLE_VID_MAX 4096 365 #define FM10K_VLAN_TABLE_VSI_MAX 64 366 #define FM10K_VLAN_LENGTH_SHIFT 16 367 #define FM10K_VLAN_CLEAR BIT(15) 368 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR 369 #define FM10K_VLAN_ALL \ 370 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT) 371 372 /* VF FLR event notification registers */ 373 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844) 374 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846) 375 376 /* Defines for size of uncacheable and write-combining memories */ 377 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */ 378 #define FM10K_WC_ADDR_START 0x100000 /* start of Tx Desc Cache */ 379 #define FM10K_DBI_ADDR_START 0x200000 /* start of debug registers */ 380 #define FM10K_UC_ADDR_SIZE (FM10K_WC_ADDR_START - FM10K_UC_ADDR_START) 381 #define FM10K_WC_ADDR_SIZE (FM10K_DBI_ADDR_START - FM10K_WC_ADDR_START) 382 383 /* Define timeouts for resets and disables */ 384 #define FM10K_QUEUE_DISABLE_TIMEOUT 100 385 #define FM10K_RESET_TIMEOUT 150 386 387 /* Maximum supported combined inner and outer header length for encapsulation */ 388 #define FM10K_TUNNEL_HEADER_LENGTH 184 389 390 /* VF registers */ 391 #define FM10K_VFCTRL 0x00000 392 #define FM10K_VFCTRL_RST 0x00000008 393 #define FM10K_VFINT_MAP 0x00030 394 #define FM10K_VFSYSTIME 0x00040 395 #define FM10K_VFITR(_n) ((_n) + 0x00060) 396 397 /* Registers contained in BAR 4 for Switch management */ 398 #define FM10K_SW_SYSTIME_ADJUST 0x0224D 399 #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF 400 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000 401 #define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252) 402 403 #ifndef ETH_ALEN 404 #define ETH_ALEN 6 405 #endif /* ETH_ALEN */ 406 407 #ifndef IS_ZERO_ETHER_ADDR 408 /* make certain address is not 0 */ 409 #define IS_ZERO_ETHER_ADDR(addr) \ 410 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5])) 411 #endif 412 413 #ifndef IS_MULTICAST_ETHER_ADDR 414 #define IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1) 415 #endif 416 417 #ifndef IS_VALID_ETHER_ADDR 418 /* make certain address is not multicast or 0 */ 419 #define IS_VALID_ETHER_ADDR(addr) \ 420 (!IS_MULTICAST_ETHER_ADDR(addr) && !IS_ZERO_ETHER_ADDR(addr)) 421 #endif 422 423 enum fm10k_int_source { 424 fm10k_int_mailbox = 0, 425 fm10k_int_pcie_fault = 1, 426 fm10k_int_switch_up_down = 2, 427 fm10k_int_switch_event = 3, 428 fm10k_int_sram = 4, 429 fm10k_int_vflr = 5, 430 fm10k_int_max_hold_time = 6, 431 fm10k_int_sources_max_pf 432 }; 433 434 /* PCIe bus speeds */ 435 enum fm10k_bus_speed { 436 fm10k_bus_speed_unknown = 0, 437 fm10k_bus_speed_2500 = 2500, 438 fm10k_bus_speed_5000 = 5000, 439 fm10k_bus_speed_8000 = 8000, 440 fm10k_bus_speed_reserved 441 }; 442 443 /* PCIe bus widths */ 444 enum fm10k_bus_width { 445 fm10k_bus_width_unknown = 0, 446 fm10k_bus_width_pcie_x1 = 1, 447 fm10k_bus_width_pcie_x2 = 2, 448 fm10k_bus_width_pcie_x4 = 4, 449 fm10k_bus_width_pcie_x8 = 8, 450 fm10k_bus_width_reserved 451 }; 452 453 /* PCIe payload sizes */ 454 enum fm10k_bus_payload { 455 fm10k_bus_payload_unknown = 0, 456 fm10k_bus_payload_128 = 1, 457 fm10k_bus_payload_256 = 2, 458 fm10k_bus_payload_512 = 3, 459 fm10k_bus_payload_reserved 460 }; 461 462 /* Bus parameters */ 463 struct fm10k_bus_info { 464 enum fm10k_bus_speed speed; 465 enum fm10k_bus_width width; 466 enum fm10k_bus_payload payload; 467 }; 468 469 /* Statistics related declarations */ 470 struct fm10k_hw_stat { 471 u64 count; 472 u32 base_l; 473 u32 base_h; 474 }; 475 476 struct fm10k_hw_stats_q { 477 struct fm10k_hw_stat tx_bytes; 478 struct fm10k_hw_stat tx_packets; 479 #define tx_stats_idx tx_packets.base_h 480 struct fm10k_hw_stat rx_bytes; 481 struct fm10k_hw_stat rx_packets; 482 #define rx_stats_idx rx_packets.base_h 483 struct fm10k_hw_stat rx_drops; 484 }; 485 486 struct fm10k_hw_stats { 487 struct fm10k_hw_stat timeout; 488 #define stats_idx timeout.base_h 489 struct fm10k_hw_stat ur; 490 struct fm10k_hw_stat ca; 491 struct fm10k_hw_stat um; 492 struct fm10k_hw_stat xec; 493 struct fm10k_hw_stat vlan_drop; 494 struct fm10k_hw_stat loopback_drop; 495 struct fm10k_hw_stat nodesc_drop; 496 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF]; 497 }; 498 499 /* Establish DGLORT feature priority */ 500 enum fm10k_dglortdec_idx { 501 fm10k_dglort_default = 0, 502 fm10k_dglort_vf_rsvd0 = 1, 503 fm10k_dglort_vf_rss = 2, 504 fm10k_dglort_pf_rsvd0 = 3, 505 fm10k_dglort_pf_queue = 4, 506 fm10k_dglort_pf_vsi = 5, 507 fm10k_dglort_pf_rsvd1 = 6, 508 fm10k_dglort_pf_rss = 7 509 }; 510 511 struct fm10k_dglort_cfg { 512 u16 glort; /* GLORT base */ 513 u16 queue_b; /* Base value for queue */ 514 u8 vsi_b; /* Base value for VSI */ 515 u8 idx; /* index of DGLORTDEC entry */ 516 u8 rss_l; /* RSS indices */ 517 u8 pc_l; /* Priority Class indices */ 518 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */ 519 u8 queue_l; /* Number of bits from GLORT used to determine queue */ 520 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */ 521 u8 inner_rss; /* Boolean value if inner header is used for RSS */ 522 }; 523 524 enum fm10k_pca_fault { 525 PCA_NO_FAULT, 526 PCA_UNMAPPED_ADDR, 527 PCA_BAD_QACCESS_PF, 528 PCA_BAD_QACCESS_VF, 529 PCA_MALICIOUS_REQ, 530 PCA_POISONED_TLP, 531 PCA_TLP_ABORT, 532 __PCA_MAX 533 }; 534 535 enum fm10k_thi_fault { 536 THI_NO_FAULT, 537 THI_MAL_DIS_Q_FAULT, 538 __THI_MAX 539 }; 540 541 enum fm10k_fum_fault { 542 FUM_NO_FAULT, 543 FUM_UNMAPPED_ADDR, 544 FUM_POISONED_TLP, 545 FUM_BAD_VF_QACCESS, 546 FUM_ADD_DECODE_ERR, 547 FUM_RO_ERROR, 548 FUM_QPRC_CRC_ERROR, 549 FUM_CSR_TIMEOUT, 550 FUM_INVALID_TYPE, 551 FUM_INVALID_LENGTH, 552 FUM_INVALID_BE, 553 FUM_INVALID_ALIGN, 554 __FUM_MAX 555 }; 556 557 struct fm10k_fault { 558 u64 address; /* Address at the time fault was detected */ 559 u32 specinfo; /* Extra info on this fault (fault dependent) */ 560 u8 type; /* Fault value dependent on subunit */ 561 u8 func; /* Function number of the fault */ 562 }; 563 564 struct fm10k_mac_ops { 565 /* basic bring-up and tear-down */ 566 s32 (*reset_hw)(struct fm10k_hw *); 567 s32 (*init_hw)(struct fm10k_hw *); 568 s32 (*start_hw)(struct fm10k_hw *); 569 s32 (*stop_hw)(struct fm10k_hw *); 570 s32 (*get_bus_info)(struct fm10k_hw *); 571 s32 (*get_host_state)(struct fm10k_hw *, bool *); 572 s32 (*request_lport_map)(struct fm10k_hw *); 573 #ifndef NO_IS_SLOT_APPROPRIATE_CHECK 574 bool (*is_slot_appropriate)(struct fm10k_hw *); 575 #endif 576 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool); 577 s32 (*read_mac_addr)(struct fm10k_hw *); 578 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *, 579 u16, bool, u8); 580 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool); 581 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8); 582 void (*update_int_moderator)(struct fm10k_hw *); 583 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool); 584 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 585 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 586 s32 (*configure_dglort_map)(struct fm10k_hw *, 587 struct fm10k_dglort_cfg *); 588 void (*set_dma_mask)(struct fm10k_hw *, u64); 589 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *); 590 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb); 591 s32 (*notify_offset)(struct fm10k_hw *, u64 offset); 592 u64 (*read_systime)(struct fm10k_hw *); 593 }; 594 595 enum fm10k_mac_type { 596 fm10k_mac_unknown = 0, 597 fm10k_mac_pf, 598 fm10k_mac_vf, 599 fm10k_num_macs 600 }; 601 602 struct fm10k_mac_info { 603 struct fm10k_mac_ops ops; 604 enum fm10k_mac_type type; 605 u8 addr[ETH_ALEN]; 606 u8 perm_addr[ETH_ALEN]; 607 u16 default_vid; 608 u16 max_msix_vectors; 609 u16 max_queues; 610 bool vlan_override; 611 bool get_host_state; 612 bool tx_ready; 613 u32 dglort_map; 614 u8 itr_scale; 615 u64 reset_while_pending; 616 }; 617 618 struct fm10k_swapi_table_info { 619 u32 used; 620 u32 avail; 621 }; 622 623 struct fm10k_swapi_info { 624 u32 status; 625 struct fm10k_swapi_table_info mac; 626 struct fm10k_swapi_table_info nexthop; 627 struct fm10k_swapi_table_info ffu; 628 }; 629 630 enum fm10k_xcast_modes { 631 FM10K_XCAST_MODE_ALLMULTI = 0, 632 FM10K_XCAST_MODE_MULTI = 1, 633 FM10K_XCAST_MODE_PROMISC = 2, 634 FM10K_XCAST_MODE_NONE = 3, 635 FM10K_XCAST_MODE_DISABLE = 4 636 }; 637 638 enum fm10k_timestamp_modes { 639 FM10K_TIMESTAMP_MODE_NONE = 0, 640 FM10K_TIMESTAMP_MODE_PEP_TO_PEP = 1, 641 FM10K_TIMESTAMP_MODE_PEP_TO_ANY = 2, 642 }; 643 644 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */ 645 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */ 646 647 struct fm10k_vf_info { 648 /* mbx must be first field in struct unless all default IOV message 649 * handlers are redone as the assumption is that vf_info starts 650 * at the same offset as the mailbox 651 */ 652 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */ 653 int rate; /* Tx BW cap as defined by OS */ 654 u16 glort; /* resource tag for this VF */ 655 u16 sw_vid; /* Switch API assigned VLAN */ 656 u16 pf_vid; /* PF assigned Default VLAN */ 657 u8 mac[ETH_ALEN]; /* PF Default MAC address */ 658 u8 vsi; /* VSI identifier */ 659 u8 vf_idx; /* which VF this is */ 660 u8 vf_flags; /* flags indicating what modes 661 * are supported for the port 662 */ 663 #ifndef NO_FM10K_VF_TRUSTED_MODE 664 bool trusted; /* VF trust mode */ 665 #endif 666 }; 667 668 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI)) 669 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI)) 670 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC)) 671 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE)) 672 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF) 673 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4) 674 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode)) 675 #define FM10K_VF_FLAG_SET_MODE_NONE \ 676 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE) 677 #define FM10K_VF_FLAG_MULTI_ENABLED \ 678 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \ 679 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \ 680 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC)) 681 682 struct fm10k_iov_ops { 683 /* IOV related bring-up and tear-down */ 684 s32 (*assign_resources)(struct fm10k_hw *, u16, u16); 685 s32 (*configure_tc)(struct fm10k_hw *, u16, int); 686 s32 (*assign_int_moderator)(struct fm10k_hw *, u16); 687 s32 (*assign_default_mac_vlan)(struct fm10k_hw *, 688 struct fm10k_vf_info *); 689 s32 (*reset_resources)(struct fm10k_hw *, 690 struct fm10k_vf_info *); 691 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8); 692 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *); 693 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16); 694 void (*notify_offset)(struct fm10k_hw *, struct fm10k_vf_info*, u64); 695 }; 696 697 struct fm10k_iov_info { 698 struct fm10k_iov_ops ops; 699 u16 total_vfs; 700 u16 num_vfs; 701 u16 num_pools; 702 }; 703 704 struct fm10k_hw { 705 u32 *hw_addr; 706 u32 *sw_addr; 707 void *back; 708 struct fm10k_mac_info mac; 709 struct fm10k_bus_info bus; 710 struct fm10k_bus_info bus_caps; 711 struct fm10k_iov_info iov; 712 struct fm10k_mbx_info mbx; 713 struct fm10k_swapi_info swapi; 714 u16 device_id; 715 u16 vendor_id; 716 u16 subsystem_device_id; 717 u16 subsystem_vendor_id; 718 u8 revision_id; 719 u32 flags; 720 #define FM10K_HW_FLAG_CLOCK_OWNER BIT(0) 721 }; 722 723 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 724 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8 725 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8 726 727 /* Transmit Descriptor */ 728 struct fm10k_tx_desc { 729 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 730 __le16 buflen; /* Length of data to be DMAed */ 731 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */ 732 __le16 mss; /* MSS for segmentation offload */ 733 u8 hdrlen; /* Header size for segmentation offload */ 734 u8 flags; /* Status and offload request flags */ 735 }; 736 737 /* Transmit Descriptor Cache Structure */ 738 struct fm10k_tx_desc_cache { 739 struct fm10k_tx_desc tx_desc[256]; 740 }; 741 742 #define FM10K_TXD_FLAG_INT 0x01 743 #define FM10K_TXD_FLAG_TIME 0x02 744 #define FM10K_TXD_FLAG_CSUM 0x04 745 #define FM10K_TXD_FLAG_FTAG 0x10 746 #define FM10K_TXD_FLAG_RS 0x20 747 #define FM10K_TXD_FLAG_LAST 0x40 748 #define FM10K_TXD_FLAG_DONE 0x80 749 750 751 /* These macros are meant to enable optimal placement of the RS and INT 752 * bits. It will point us to the last descriptor in the cache for either the 753 * start of the packet, or the end of the packet. If the index is actually 754 * at the start of the FIFO it will point to the offset for the last index 755 * in the FIFO to prevent an unnecessary write. 756 */ 757 #define FM10K_TXD_WB_FIFO_SIZE 4 758 759 /* Receive Descriptor - 32B */ 760 union fm10k_rx_desc { 761 struct { 762 __le64 pkt_addr; /* Packet buffer address */ 763 __le64 hdr_addr; /* Header buffer address */ 764 __le64 reserved; /* Empty space, RSS hash */ 765 __le64 timestamp; 766 } q; /* Read, Writeback, 64b quad-words */ 767 struct { 768 __le32 data; /* RSS and header data */ 769 __le32 rss; /* RSS Hash */ 770 __le32 staterr; 771 __le32 vlan_len; 772 __le32 glort; /* sglort/dglort */ 773 } d; /* Writeback, 32b double-words */ 774 struct { 775 __le16 pkt_info; /* RSS, Pkt type */ 776 __le16 hdr_info; /* Splithdr, hdrlen, xC */ 777 __le16 rss_lower; 778 __le16 rss_upper; 779 __le16 status; /* status/error */ 780 __le16 csum_err; /* checksum or extended error value */ 781 __le16 length; /* Packet length */ 782 __le16 vlan; /* VLAN tag */ 783 __le16 dglort; 784 __le16 sglort; 785 } w; /* Writeback, 16b words */ 786 }; 787 788 #define FM10K_RXD_RSSTYPE_MASK 0x000F 789 enum fm10k_rdesc_rss_type { 790 FM10K_RSSTYPE_NONE = 0x0, 791 FM10K_RSSTYPE_IPV4_TCP = 0x1, 792 FM10K_RSSTYPE_IPV4 = 0x2, 793 FM10K_RSSTYPE_IPV6_TCP = 0x3, 794 /* Reserved 0x4 */ 795 FM10K_RSSTYPE_IPV6 = 0x5, 796 /* Reserved 0x6 */ 797 FM10K_RSSTYPE_IPV4_UDP = 0x7, 798 FM10K_RSSTYPE_IPV6_UDP = 0x8 799 /* Reserved 0x9 - 0xF */ 800 }; 801 802 #define FM10K_RXD_PKTTYPE_MASK 0x03F0 803 #define FM10K_RXD_PKTTYPE_SHIFT 4 804 enum fm10k_rdesc_pkt_type { 805 /* L3 type */ 806 FM10K_PKTTYPE_OTHER = 0x00, 807 FM10K_PKTTYPE_IPV4 = 0x01, 808 FM10K_PKTTYPE_IPV4_EX = 0x02, 809 FM10K_PKTTYPE_IPV6 = 0x03, 810 FM10K_PKTTYPE_IPV6_EX = 0x04, 811 812 /* L4 type */ 813 FM10K_PKTTYPE_TCP = 0x08, 814 FM10K_PKTTYPE_UDP = 0x10, 815 FM10K_PKTTYPE_GRE = 0x18, 816 FM10K_PKTTYPE_VXLAN = 0x20, 817 FM10K_PKTTYPE_NVGRE = 0x28, 818 FM10K_PKTTYPE_GENEVE = 0x30 819 }; 820 821 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006 822 enum fm10k_rxdesc_xc { 823 FM10K_XC_UNICAST = 0x0, 824 FM10K_XC_MULTICAST = 0x4, 825 FM10K_XC_BROADCAST = 0x6 826 }; 827 828 829 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */ 830 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */ 831 #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */ 832 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */ 833 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */ 834 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */ 835 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */ 836 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */ 837 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */ 838 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */ 839 840 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */ 841 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */ 842 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */ 843 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */ 844 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */ 845 846 847 struct fm10k_ftag { 848 __be16 swpri_type_user; 849 __be16 vlan; 850 __be16 sglort; 851 __be16 dglort; 852 }; 853 854 #endif /* _FM10K_TYPE_H */ 855