1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/drm_crtc_helper.h>
32 #include <dev/drm2/radeon/radeon_drm.h>
33 #include <dev/drm2/drm_fixed.h>
34 #include "radeon.h"
35 #include "atom.h"
36 #include "atom-bits.h"
37
atombios_overscan_setup(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)38 static void atombios_overscan_setup(struct drm_crtc *crtc,
39 struct drm_display_mode *mode,
40 struct drm_display_mode *adjusted_mode)
41 {
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
45 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
46 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
47 int a1, a2;
48
49 memset(&args, 0, sizeof(args));
50
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
59 break;
60 case RMX_ASPECT:
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
63
64 if (a1 > a2) {
65 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
66 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
67 } else if (a2 > a1) {
68 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
69 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 }
71 break;
72 case RMX_FULL:
73 default:
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
78 break;
79 }
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 }
82
atombios_scaler_setup(struct drm_crtc * crtc)83 static void atombios_scaler_setup(struct drm_crtc *crtc)
84 {
85 struct drm_device *dev = crtc->dev;
86 struct radeon_device *rdev = dev->dev_private;
87 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
88 ENABLE_SCALER_PS_ALLOCATION args;
89 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
90 struct radeon_encoder *radeon_encoder =
91 to_radeon_encoder(radeon_crtc->encoder);
92 /* fixme - fill in enc_priv for atom dac */
93 enum radeon_tv_std tv_std = TV_STD_NTSC;
94 bool is_tv = false, is_cv = false;
95
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
97 return;
98
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104
105 memset(&args, 0, sizeof(args));
106
107 args.ucScaler = radeon_crtc->crtc_id;
108
109 if (is_tv) {
110 switch (tv_std) {
111 case TV_STD_NTSC:
112 default:
113 args.ucTVStandard = ATOM_TV_NTSC;
114 break;
115 case TV_STD_PAL:
116 args.ucTVStandard = ATOM_TV_PAL;
117 break;
118 case TV_STD_PAL_M:
119 args.ucTVStandard = ATOM_TV_PALM;
120 break;
121 case TV_STD_PAL_60:
122 args.ucTVStandard = ATOM_TV_PAL60;
123 break;
124 case TV_STD_NTSC_J:
125 args.ucTVStandard = ATOM_TV_NTSCJ;
126 break;
127 case TV_STD_SCART_PAL:
128 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
129 break;
130 case TV_STD_SECAM:
131 args.ucTVStandard = ATOM_TV_SECAM;
132 break;
133 case TV_STD_PAL_CN:
134 args.ucTVStandard = ATOM_TV_PALCN;
135 break;
136 }
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
138 } else if (is_cv) {
139 args.ucTVStandard = ATOM_TV_CV;
140 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
141 } else {
142 switch (radeon_crtc->rmx_type) {
143 case RMX_FULL:
144 args.ucEnable = ATOM_SCALER_EXPANSION;
145 break;
146 case RMX_CENTER:
147 args.ucEnable = ATOM_SCALER_CENTER;
148 break;
149 case RMX_ASPECT:
150 args.ucEnable = ATOM_SCALER_EXPANSION;
151 break;
152 default:
153 if (ASIC_IS_AVIVO(rdev))
154 args.ucEnable = ATOM_SCALER_DISABLE;
155 else
156 args.ucEnable = ATOM_SCALER_CENTER;
157 break;
158 }
159 }
160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
161 if ((is_tv || is_cv)
162 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
163 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
164 }
165 }
166
atombios_lock_crtc(struct drm_crtc * crtc,int lock)167 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
168 {
169 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
170 struct drm_device *dev = crtc->dev;
171 struct radeon_device *rdev = dev->dev_private;
172 int index =
173 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
174 ENABLE_CRTC_PS_ALLOCATION args;
175
176 memset(&args, 0, sizeof(args));
177
178 args.ucCRTC = radeon_crtc->crtc_id;
179 args.ucEnable = lock;
180
181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
182 }
183
atombios_enable_crtc(struct drm_crtc * crtc,int state)184 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
185 {
186 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
187 struct drm_device *dev = crtc->dev;
188 struct radeon_device *rdev = dev->dev_private;
189 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
190 ENABLE_CRTC_PS_ALLOCATION args;
191
192 memset(&args, 0, sizeof(args));
193
194 args.ucCRTC = radeon_crtc->crtc_id;
195 args.ucEnable = state;
196
197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
198 }
199
atombios_enable_crtc_memreq(struct drm_crtc * crtc,int state)200 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
201 {
202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
203 struct drm_device *dev = crtc->dev;
204 struct radeon_device *rdev = dev->dev_private;
205 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
206 ENABLE_CRTC_PS_ALLOCATION args;
207
208 memset(&args, 0, sizeof(args));
209
210 args.ucCRTC = radeon_crtc->crtc_id;
211 args.ucEnable = state;
212
213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
214 }
215
atombios_blank_crtc(struct drm_crtc * crtc,int state)216 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
217 {
218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
219 struct drm_device *dev = crtc->dev;
220 struct radeon_device *rdev = dev->dev_private;
221 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
222 BLANK_CRTC_PS_ALLOCATION args;
223
224 memset(&args, 0, sizeof(args));
225
226 args.ucCRTC = radeon_crtc->crtc_id;
227 args.ucBlanking = state;
228
229 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
230 }
231
atombios_powergate_crtc(struct drm_crtc * crtc,int state)232 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
233 {
234 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
235 struct drm_device *dev = crtc->dev;
236 struct radeon_device *rdev = dev->dev_private;
237 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
238 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
239
240 memset(&args, 0, sizeof(args));
241
242 args.ucDispPipeId = radeon_crtc->crtc_id;
243 args.ucEnable = state;
244
245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
246 }
247
atombios_crtc_dpms(struct drm_crtc * crtc,int mode)248 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
249 {
250 struct drm_device *dev = crtc->dev;
251 struct radeon_device *rdev = dev->dev_private;
252 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
253
254 switch (mode) {
255 case DRM_MODE_DPMS_ON:
256 radeon_crtc->enabled = true;
257 /* adjust pm to dpms changes BEFORE enabling crtcs */
258 radeon_pm_compute_clocks(rdev);
259 atombios_enable_crtc(crtc, ATOM_ENABLE);
260 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
261 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
262 atombios_blank_crtc(crtc, ATOM_DISABLE);
263 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
264 radeon_crtc_load_lut(crtc);
265 break;
266 case DRM_MODE_DPMS_STANDBY:
267 case DRM_MODE_DPMS_SUSPEND:
268 case DRM_MODE_DPMS_OFF:
269 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
270 if (radeon_crtc->enabled)
271 atombios_blank_crtc(crtc, ATOM_ENABLE);
272 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
273 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
274 atombios_enable_crtc(crtc, ATOM_DISABLE);
275 radeon_crtc->enabled = false;
276 /* adjust pm to dpms changes AFTER disabling crtcs */
277 radeon_pm_compute_clocks(rdev);
278 break;
279 }
280 }
281
282 static void
atombios_set_crtc_dtd_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)283 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
284 struct drm_display_mode *mode)
285 {
286 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
287 struct drm_device *dev = crtc->dev;
288 struct radeon_device *rdev = dev->dev_private;
289 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
290 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
291 u16 misc = 0;
292
293 memset(&args, 0, sizeof(args));
294 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
295 args.usH_Blanking_Time =
296 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
297 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
298 args.usV_Blanking_Time =
299 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
300 args.usH_SyncOffset =
301 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
302 args.usH_SyncWidth =
303 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
304 args.usV_SyncOffset =
305 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
306 args.usV_SyncWidth =
307 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
308 args.ucH_Border = radeon_crtc->h_border;
309 args.ucV_Border = radeon_crtc->v_border;
310
311 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
312 misc |= ATOM_VSYNC_POLARITY;
313 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
314 misc |= ATOM_HSYNC_POLARITY;
315 if (mode->flags & DRM_MODE_FLAG_CSYNC)
316 misc |= ATOM_COMPOSITESYNC;
317 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
318 misc |= ATOM_INTERLACE;
319 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
320 misc |= ATOM_DOUBLE_CLOCK_MODE;
321
322 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
323 args.ucCRTC = radeon_crtc->crtc_id;
324
325 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
326 }
327
atombios_crtc_set_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)328 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
329 struct drm_display_mode *mode)
330 {
331 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
332 struct drm_device *dev = crtc->dev;
333 struct radeon_device *rdev = dev->dev_private;
334 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
335 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
336 u16 misc = 0;
337
338 memset(&args, 0, sizeof(args));
339 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
340 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
341 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
342 args.usH_SyncWidth =
343 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
344 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
345 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
346 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
347 args.usV_SyncWidth =
348 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
349
350 args.ucOverscanRight = radeon_crtc->h_border;
351 args.ucOverscanLeft = radeon_crtc->h_border;
352 args.ucOverscanBottom = radeon_crtc->v_border;
353 args.ucOverscanTop = radeon_crtc->v_border;
354
355 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
356 misc |= ATOM_VSYNC_POLARITY;
357 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
358 misc |= ATOM_HSYNC_POLARITY;
359 if (mode->flags & DRM_MODE_FLAG_CSYNC)
360 misc |= ATOM_COMPOSITESYNC;
361 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
362 misc |= ATOM_INTERLACE;
363 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
364 misc |= ATOM_DOUBLE_CLOCK_MODE;
365
366 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
367 args.ucCRTC = radeon_crtc->crtc_id;
368
369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
370 }
371
atombios_disable_ss(struct radeon_device * rdev,int pll_id)372 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
373 {
374 u32 ss_cntl;
375
376 if (ASIC_IS_DCE4(rdev)) {
377 switch (pll_id) {
378 case ATOM_PPLL1:
379 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
380 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
381 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
382 break;
383 case ATOM_PPLL2:
384 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
385 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
386 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_DCPLL:
389 case ATOM_PPLL_INVALID:
390 return;
391 }
392 } else if (ASIC_IS_AVIVO(rdev)) {
393 switch (pll_id) {
394 case ATOM_PPLL1:
395 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
396 ss_cntl &= ~1;
397 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
398 break;
399 case ATOM_PPLL2:
400 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
401 ss_cntl &= ~1;
402 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
403 break;
404 case ATOM_DCPLL:
405 case ATOM_PPLL_INVALID:
406 return;
407 }
408 }
409 }
410
411
412 union atom_enable_ss {
413 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
414 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
415 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
416 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
417 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
418 };
419
atombios_crtc_program_ss(struct radeon_device * rdev,int enable,int pll_id,int crtc_id,struct radeon_atom_ss * ss)420 static void atombios_crtc_program_ss(struct radeon_device *rdev,
421 int enable,
422 int pll_id,
423 int crtc_id,
424 struct radeon_atom_ss *ss)
425 {
426 unsigned i;
427 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
428 union atom_enable_ss args;
429
430 if (!enable) {
431 for (i = 0; i < rdev->num_crtc; i++) {
432 if (rdev->mode_info.crtcs[i] &&
433 rdev->mode_info.crtcs[i]->enabled &&
434 i != crtc_id &&
435 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
436 /* one other crtc is using this pll don't turn
437 * off spread spectrum as it might turn off
438 * display on active crtc
439 */
440 return;
441 }
442 }
443 }
444
445 memset(&args, 0, sizeof(args));
446
447 if (ASIC_IS_DCE5(rdev)) {
448 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
449 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
450 switch (pll_id) {
451 case ATOM_PPLL1:
452 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
453 break;
454 case ATOM_PPLL2:
455 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
456 break;
457 case ATOM_DCPLL:
458 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
459 break;
460 case ATOM_PPLL_INVALID:
461 return;
462 }
463 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
464 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
465 args.v3.ucEnable = enable;
466 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
467 args.v3.ucEnable = ATOM_DISABLE;
468 } else if (ASIC_IS_DCE4(rdev)) {
469 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
470 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
471 switch (pll_id) {
472 case ATOM_PPLL1:
473 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
474 break;
475 case ATOM_PPLL2:
476 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
477 break;
478 case ATOM_DCPLL:
479 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
480 break;
481 case ATOM_PPLL_INVALID:
482 return;
483 }
484 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
485 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
486 args.v2.ucEnable = enable;
487 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
488 args.v2.ucEnable = ATOM_DISABLE;
489 } else if (ASIC_IS_DCE3(rdev)) {
490 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
491 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
492 args.v1.ucSpreadSpectrumStep = ss->step;
493 args.v1.ucSpreadSpectrumDelay = ss->delay;
494 args.v1.ucSpreadSpectrumRange = ss->range;
495 args.v1.ucPpll = pll_id;
496 args.v1.ucEnable = enable;
497 } else if (ASIC_IS_AVIVO(rdev)) {
498 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
499 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
500 atombios_disable_ss(rdev, pll_id);
501 return;
502 }
503 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
504 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
505 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
506 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
507 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
508 args.lvds_ss_2.ucEnable = enable;
509 } else {
510 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
511 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
512 atombios_disable_ss(rdev, pll_id);
513 return;
514 }
515 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
516 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
517 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
518 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
519 args.lvds_ss.ucEnable = enable;
520 }
521 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
522 }
523
524 union adjust_pixel_clock {
525 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
526 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
527 };
528
atombios_adjust_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)529 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
530 struct drm_display_mode *mode)
531 {
532 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
533 struct drm_device *dev = crtc->dev;
534 struct radeon_device *rdev = dev->dev_private;
535 struct drm_encoder *encoder = radeon_crtc->encoder;
536 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
537 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
538 u32 adjusted_clock = mode->clock;
539 int encoder_mode = atombios_get_encoder_mode(encoder);
540 u32 dp_clock = mode->clock;
541 int bpc = radeon_get_monitor_bpc(connector);
542 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
543
544 /* reset the pll flags */
545 radeon_crtc->pll_flags = 0;
546
547 if (ASIC_IS_AVIVO(rdev)) {
548 if ((rdev->family == CHIP_RS600) ||
549 (rdev->family == CHIP_RS690) ||
550 (rdev->family == CHIP_RS740))
551 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
552 RADEON_PLL_PREFER_CLOSEST_LOWER);
553
554 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
555 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
556 else
557 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
558
559 if (rdev->family < CHIP_RV770)
560 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
561 /* use frac fb div on APUs */
562 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
563 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
564 /* use frac fb div on RS780/RS880 */
565 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
566 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
567 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
568 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
569 } else {
570 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
571
572 if (mode->clock > 200000) /* range limits??? */
573 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
574 else
575 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
576 }
577
578 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
579 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
580 if (connector) {
581 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
582 struct radeon_connector_atom_dig *dig_connector =
583 radeon_connector->con_priv;
584
585 dp_clock = dig_connector->dp_clock;
586 }
587 }
588
589 /* use recommended ref_div for ss */
590 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
591 if (radeon_crtc->ss_enabled) {
592 if (radeon_crtc->ss.refdiv) {
593 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
594 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
595 if (ASIC_IS_AVIVO(rdev))
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
597 }
598 }
599 }
600
601 if (ASIC_IS_AVIVO(rdev)) {
602 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
603 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
604 adjusted_clock = mode->clock * 2;
605 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
606 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
607 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
608 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
609 } else {
610 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
611 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
612 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
613 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
614 }
615
616 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
617 * accordingly based on the encoder/transmitter to work around
618 * special hw requirements.
619 */
620 if (ASIC_IS_DCE3(rdev)) {
621 union adjust_pixel_clock args;
622 u8 frev, crev;
623 int index;
624
625 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
626 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
627 &crev))
628 return adjusted_clock;
629
630 memset(&args, 0, sizeof(args));
631
632 switch (frev) {
633 case 1:
634 switch (crev) {
635 case 1:
636 case 2:
637 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
638 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
639 args.v1.ucEncodeMode = encoder_mode;
640 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
641 args.v1.ucConfig |=
642 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
643
644 atom_execute_table(rdev->mode_info.atom_context,
645 index, (uint32_t *)&args);
646 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
647 break;
648 case 3:
649 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
650 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
651 args.v3.sInput.ucEncodeMode = encoder_mode;
652 args.v3.sInput.ucDispPllConfig = 0;
653 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
654 args.v3.sInput.ucDispPllConfig |=
655 DISPPLL_CONFIG_SS_ENABLE;
656 if (ENCODER_MODE_IS_DP(encoder_mode)) {
657 args.v3.sInput.ucDispPllConfig |=
658 DISPPLL_CONFIG_COHERENT_MODE;
659 /* 16200 or 27000 */
660 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
661 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
662 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
663 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
664 /* deep color support */
665 args.v3.sInput.usPixelClock =
666 cpu_to_le16((mode->clock * bpc / 8) / 10);
667 if (dig->coherent_mode)
668 args.v3.sInput.ucDispPllConfig |=
669 DISPPLL_CONFIG_COHERENT_MODE;
670 if (is_duallink)
671 args.v3.sInput.ucDispPllConfig |=
672 DISPPLL_CONFIG_DUAL_LINK;
673 }
674 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
675 ENCODER_OBJECT_ID_NONE)
676 args.v3.sInput.ucExtTransmitterID =
677 radeon_encoder_get_dp_bridge_encoder_id(encoder);
678 else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
681 atom_execute_table(rdev->mode_info.atom_context,
682 index, (uint32_t *)&args);
683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
684 if (args.v3.sOutput.ucRefDiv) {
685 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
686 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
687 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
688 }
689 if (args.v3.sOutput.ucPostDiv) {
690 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
691 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
692 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
693 }
694 break;
695 default:
696 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
697 return adjusted_clock;
698 }
699 break;
700 default:
701 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
702 return adjusted_clock;
703 }
704 }
705 return adjusted_clock;
706 }
707
708 union set_pixel_clock {
709 SET_PIXEL_CLOCK_PS_ALLOCATION base;
710 PIXEL_CLOCK_PARAMETERS v1;
711 PIXEL_CLOCK_PARAMETERS_V2 v2;
712 PIXEL_CLOCK_PARAMETERS_V3 v3;
713 PIXEL_CLOCK_PARAMETERS_V5 v5;
714 PIXEL_CLOCK_PARAMETERS_V6 v6;
715 };
716
717 /* on DCE5, make sure the voltage is high enough to support the
718 * required disp clk.
719 */
atombios_crtc_set_disp_eng_pll(struct radeon_device * rdev,u32 dispclk)720 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
721 u32 dispclk)
722 {
723 u8 frev, crev;
724 int index;
725 union set_pixel_clock args;
726
727 memset(&args, 0, sizeof(args));
728
729 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
730 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
731 &crev))
732 return;
733
734 switch (frev) {
735 case 1:
736 switch (crev) {
737 case 5:
738 /* if the default dcpll clock is specified,
739 * SetPixelClock provides the dividers
740 */
741 args.v5.ucCRTC = ATOM_CRTC_INVALID;
742 args.v5.usPixelClock = cpu_to_le16(dispclk);
743 args.v5.ucPpll = ATOM_DCPLL;
744 break;
745 case 6:
746 /* if the default dcpll clock is specified,
747 * SetPixelClock provides the dividers
748 */
749 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
750 if (ASIC_IS_DCE61(rdev))
751 args.v6.ucPpll = ATOM_EXT_PLL1;
752 else if (ASIC_IS_DCE6(rdev))
753 args.v6.ucPpll = ATOM_PPLL0;
754 else
755 args.v6.ucPpll = ATOM_DCPLL;
756 break;
757 default:
758 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
759 return;
760 }
761 break;
762 default:
763 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
764 return;
765 }
766 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
767 }
768
atombios_crtc_program_pll(struct drm_crtc * crtc,u32 crtc_id,int pll_id,u32 encoder_mode,u32 encoder_id,u32 clock,u32 ref_div,u32 fb_div,u32 frac_fb_div,u32 post_div,int bpc,bool ss_enabled,struct radeon_atom_ss * ss)769 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
770 u32 crtc_id,
771 int pll_id,
772 u32 encoder_mode,
773 u32 encoder_id,
774 u32 clock,
775 u32 ref_div,
776 u32 fb_div,
777 u32 frac_fb_div,
778 u32 post_div,
779 int bpc,
780 bool ss_enabled,
781 struct radeon_atom_ss *ss)
782 {
783 struct drm_device *dev = crtc->dev;
784 struct radeon_device *rdev = dev->dev_private;
785 u8 frev, crev;
786 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
787 union set_pixel_clock args;
788
789 memset(&args, 0, sizeof(args));
790
791 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
792 &crev))
793 return;
794
795 switch (frev) {
796 case 1:
797 switch (crev) {
798 case 1:
799 if (clock == ATOM_DISABLE)
800 return;
801 args.v1.usPixelClock = cpu_to_le16(clock / 10);
802 args.v1.usRefDiv = cpu_to_le16(ref_div);
803 args.v1.usFbDiv = cpu_to_le16(fb_div);
804 args.v1.ucFracFbDiv = frac_fb_div;
805 args.v1.ucPostDiv = post_div;
806 args.v1.ucPpll = pll_id;
807 args.v1.ucCRTC = crtc_id;
808 args.v1.ucRefDivSrc = 1;
809 break;
810 case 2:
811 args.v2.usPixelClock = cpu_to_le16(clock / 10);
812 args.v2.usRefDiv = cpu_to_le16(ref_div);
813 args.v2.usFbDiv = cpu_to_le16(fb_div);
814 args.v2.ucFracFbDiv = frac_fb_div;
815 args.v2.ucPostDiv = post_div;
816 args.v2.ucPpll = pll_id;
817 args.v2.ucCRTC = crtc_id;
818 args.v2.ucRefDivSrc = 1;
819 break;
820 case 3:
821 args.v3.usPixelClock = cpu_to_le16(clock / 10);
822 args.v3.usRefDiv = cpu_to_le16(ref_div);
823 args.v3.usFbDiv = cpu_to_le16(fb_div);
824 args.v3.ucFracFbDiv = frac_fb_div;
825 args.v3.ucPostDiv = post_div;
826 args.v3.ucPpll = pll_id;
827 if (crtc_id == ATOM_CRTC2)
828 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
829 else
830 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
831 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
832 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
833 args.v3.ucTransmitterId = encoder_id;
834 args.v3.ucEncoderMode = encoder_mode;
835 break;
836 case 5:
837 args.v5.ucCRTC = crtc_id;
838 args.v5.usPixelClock = cpu_to_le16(clock / 10);
839 args.v5.ucRefDiv = ref_div;
840 args.v5.usFbDiv = cpu_to_le16(fb_div);
841 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
842 args.v5.ucPostDiv = post_div;
843 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
844 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
845 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
846 switch (bpc) {
847 case 8:
848 default:
849 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
850 break;
851 case 10:
852 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
853 break;
854 }
855 args.v5.ucTransmitterID = encoder_id;
856 args.v5.ucEncoderMode = encoder_mode;
857 args.v5.ucPpll = pll_id;
858 break;
859 case 6:
860 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
861 args.v6.ucRefDiv = ref_div;
862 args.v6.usFbDiv = cpu_to_le16(fb_div);
863 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
864 args.v6.ucPostDiv = post_div;
865 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
866 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
867 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
868 switch (bpc) {
869 case 8:
870 default:
871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
872 break;
873 case 10:
874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
875 break;
876 case 12:
877 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
878 break;
879 case 16:
880 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
881 break;
882 }
883 args.v6.ucTransmitterID = encoder_id;
884 args.v6.ucEncoderMode = encoder_mode;
885 args.v6.ucPpll = pll_id;
886 break;
887 default:
888 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
889 return;
890 }
891 break;
892 default:
893 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
894 return;
895 }
896
897 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
898 }
899
atombios_crtc_prepare_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)900 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
901 {
902 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
903 struct drm_device *dev = crtc->dev;
904 struct radeon_device *rdev = dev->dev_private;
905 struct radeon_encoder *radeon_encoder =
906 to_radeon_encoder(radeon_crtc->encoder);
907 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
908
909 radeon_crtc->bpc = 8;
910 radeon_crtc->ss_enabled = false;
911
912 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
913 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
914 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
915 struct drm_connector *connector =
916 radeon_get_connector_for_encoder(radeon_crtc->encoder);
917 struct radeon_connector *radeon_connector =
918 to_radeon_connector(connector);
919 struct radeon_connector_atom_dig *dig_connector =
920 radeon_connector->con_priv;
921 int dp_clock;
922 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
923
924 switch (encoder_mode) {
925 case ATOM_ENCODER_MODE_DP_MST:
926 case ATOM_ENCODER_MODE_DP:
927 /* DP/eDP */
928 dp_clock = dig_connector->dp_clock / 10;
929 if (ASIC_IS_DCE4(rdev))
930 radeon_crtc->ss_enabled =
931 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
932 ASIC_INTERNAL_SS_ON_DP,
933 dp_clock);
934 else {
935 if (dp_clock == 16200) {
936 radeon_crtc->ss_enabled =
937 radeon_atombios_get_ppll_ss_info(rdev,
938 &radeon_crtc->ss,
939 ATOM_DP_SS_ID2);
940 if (!radeon_crtc->ss_enabled)
941 radeon_crtc->ss_enabled =
942 radeon_atombios_get_ppll_ss_info(rdev,
943 &radeon_crtc->ss,
944 ATOM_DP_SS_ID1);
945 } else
946 radeon_crtc->ss_enabled =
947 radeon_atombios_get_ppll_ss_info(rdev,
948 &radeon_crtc->ss,
949 ATOM_DP_SS_ID1);
950 }
951 break;
952 case ATOM_ENCODER_MODE_LVDS:
953 if (ASIC_IS_DCE4(rdev))
954 radeon_crtc->ss_enabled =
955 radeon_atombios_get_asic_ss_info(rdev,
956 &radeon_crtc->ss,
957 dig->lcd_ss_id,
958 mode->clock / 10);
959 else
960 radeon_crtc->ss_enabled =
961 radeon_atombios_get_ppll_ss_info(rdev,
962 &radeon_crtc->ss,
963 dig->lcd_ss_id);
964 break;
965 case ATOM_ENCODER_MODE_DVI:
966 if (ASIC_IS_DCE4(rdev))
967 radeon_crtc->ss_enabled =
968 radeon_atombios_get_asic_ss_info(rdev,
969 &radeon_crtc->ss,
970 ASIC_INTERNAL_SS_ON_TMDS,
971 mode->clock / 10);
972 break;
973 case ATOM_ENCODER_MODE_HDMI:
974 if (ASIC_IS_DCE4(rdev))
975 radeon_crtc->ss_enabled =
976 radeon_atombios_get_asic_ss_info(rdev,
977 &radeon_crtc->ss,
978 ASIC_INTERNAL_SS_ON_HDMI,
979 mode->clock / 10);
980 break;
981 default:
982 break;
983 }
984 }
985
986 /* adjust pixel clock as needed */
987 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
988
989 return true;
990 }
991
atombios_crtc_set_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)992 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
993 {
994 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
995 struct drm_device *dev = crtc->dev;
996 struct radeon_device *rdev = dev->dev_private;
997 struct radeon_encoder *radeon_encoder =
998 to_radeon_encoder(radeon_crtc->encoder);
999 u32 pll_clock = mode->clock;
1000 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1001 struct radeon_pll *pll;
1002 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1003
1004 switch (radeon_crtc->pll_id) {
1005 case ATOM_PPLL1:
1006 pll = &rdev->clock.p1pll;
1007 break;
1008 case ATOM_PPLL2:
1009 pll = &rdev->clock.p2pll;
1010 break;
1011 case ATOM_DCPLL:
1012 case ATOM_PPLL_INVALID:
1013 default:
1014 pll = &rdev->clock.dcpll;
1015 break;
1016 }
1017
1018 /* update pll params */
1019 pll->flags = radeon_crtc->pll_flags;
1020 pll->reference_div = radeon_crtc->pll_reference_div;
1021 pll->post_div = radeon_crtc->pll_post_div;
1022
1023 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1024 /* TV seems to prefer the legacy algo on some boards */
1025 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1026 &fb_div, &frac_fb_div, &ref_div, &post_div);
1027 else if (ASIC_IS_AVIVO(rdev))
1028 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1029 &fb_div, &frac_fb_div, &ref_div, &post_div);
1030 else
1031 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1032 &fb_div, &frac_fb_div, &ref_div, &post_div);
1033
1034 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1035 radeon_crtc->crtc_id, &radeon_crtc->ss);
1036
1037 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1038 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1039 ref_div, fb_div, frac_fb_div, post_div,
1040 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1041
1042 if (radeon_crtc->ss_enabled) {
1043 /* calculate ss amount and step size */
1044 if (ASIC_IS_DCE4(rdev)) {
1045 u32 step_size;
1046 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;
1047 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1048 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1049 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1050 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1051 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1052 (125 * 25 * pll->reference_freq / 100);
1053 else
1054 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1055 (125 * 25 * pll->reference_freq / 100);
1056 radeon_crtc->ss.step = step_size;
1057 }
1058
1059 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1060 radeon_crtc->crtc_id, &radeon_crtc->ss);
1061 }
1062 }
1063
dce4_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1064 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1065 struct drm_framebuffer *fb,
1066 int x, int y, int atomic)
1067 {
1068 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1069 struct drm_device *dev = crtc->dev;
1070 struct radeon_device *rdev = dev->dev_private;
1071 struct radeon_framebuffer *radeon_fb;
1072 struct drm_framebuffer *target_fb;
1073 struct drm_gem_object *obj;
1074 struct radeon_bo *rbo;
1075 uint64_t fb_location;
1076 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1077 unsigned bankw, bankh, mtaspect, tile_split;
1078 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1079 u32 tmp, viewport_w, viewport_h;
1080 int r;
1081
1082 /* no fb bound */
1083 if (!atomic && !crtc->fb) {
1084 DRM_DEBUG_KMS("No FB bound\n");
1085 return 0;
1086 }
1087
1088 if (atomic) {
1089 radeon_fb = to_radeon_framebuffer(fb);
1090 target_fb = fb;
1091 }
1092 else {
1093 radeon_fb = to_radeon_framebuffer(crtc->fb);
1094 target_fb = crtc->fb;
1095 }
1096
1097 /* If atomic, assume fb object is pinned & idle & fenced and
1098 * just update base pointers
1099 */
1100 obj = radeon_fb->obj;
1101 rbo = gem_to_radeon_bo(obj);
1102 r = radeon_bo_reserve(rbo, false);
1103 if (unlikely(r != 0))
1104 return r;
1105
1106 if (atomic)
1107 fb_location = radeon_bo_gpu_offset(rbo);
1108 else {
1109 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1110 if (unlikely(r != 0)) {
1111 radeon_bo_unreserve(rbo);
1112 return -EINVAL;
1113 }
1114 }
1115
1116 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1117 radeon_bo_unreserve(rbo);
1118
1119 switch (target_fb->bits_per_pixel) {
1120 case 8:
1121 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1122 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1123 break;
1124 case 15:
1125 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1126 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1127 break;
1128 case 16:
1129 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1130 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1131 #ifdef __BIG_ENDIAN
1132 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1133 #endif
1134 break;
1135 case 24:
1136 case 32:
1137 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1138 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1139 #ifdef __BIG_ENDIAN
1140 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1141 #endif
1142 break;
1143 default:
1144 DRM_ERROR("Unsupported screen depth %d\n",
1145 target_fb->bits_per_pixel);
1146 return -EINVAL;
1147 }
1148
1149 if (tiling_flags & RADEON_TILING_MACRO) {
1150 if (rdev->family >= CHIP_TAHITI)
1151 tmp = rdev->config.si.tile_config;
1152 else if (rdev->family >= CHIP_CAYMAN)
1153 tmp = rdev->config.cayman.tile_config;
1154 else
1155 tmp = rdev->config.evergreen.tile_config;
1156
1157 switch ((tmp & 0xf0) >> 4) {
1158 case 0: /* 4 banks */
1159 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1160 break;
1161 case 1: /* 8 banks */
1162 default:
1163 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1164 break;
1165 case 2: /* 16 banks */
1166 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1167 break;
1168 }
1169
1170 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1171
1172 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1173 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1174 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1175 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1176 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1177 } else if (tiling_flags & RADEON_TILING_MICRO)
1178 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1179
1180 if ((rdev->family == CHIP_TAHITI) ||
1181 (rdev->family == CHIP_PITCAIRN))
1182 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1183 else if (rdev->family == CHIP_VERDE)
1184 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1185
1186 switch (radeon_crtc->crtc_id) {
1187 case 0:
1188 WREG32(AVIVO_D1VGA_CONTROL, 0);
1189 break;
1190 case 1:
1191 WREG32(AVIVO_D2VGA_CONTROL, 0);
1192 break;
1193 case 2:
1194 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1195 break;
1196 case 3:
1197 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1198 break;
1199 case 4:
1200 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1201 break;
1202 case 5:
1203 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1204 break;
1205 default:
1206 break;
1207 }
1208
1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1210 upper_32_bits(fb_location));
1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1212 upper_32_bits(fb_location));
1213 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1214 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1215 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1216 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1217 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1218 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1219
1220 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1221 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1222 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1223 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1224 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1225 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1226
1227 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1228 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1229 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1230
1231 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1232 target_fb->height);
1233 x &= ~3;
1234 y &= ~1;
1235 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1236 (x << 16) | y);
1237 viewport_w = crtc->mode.hdisplay;
1238 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1239 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1240 (viewport_w << 16) | viewport_h);
1241
1242 /* pageflip setup */
1243 /* make sure flip is at vb rather than hb */
1244 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1245 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1246 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1247
1248 /* set pageflip to happen anywhere in vblank interval */
1249 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1250
1251 if (!atomic && fb && fb != crtc->fb) {
1252 radeon_fb = to_radeon_framebuffer(fb);
1253 rbo = gem_to_radeon_bo(radeon_fb->obj);
1254 r = radeon_bo_reserve(rbo, false);
1255 if (unlikely(r != 0))
1256 return r;
1257 radeon_bo_unpin(rbo);
1258 radeon_bo_unreserve(rbo);
1259 }
1260
1261 /* Bytes per pixel may have changed */
1262 radeon_bandwidth_update(rdev);
1263
1264 return 0;
1265 }
1266
avivo_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1267 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1268 struct drm_framebuffer *fb,
1269 int x, int y, int atomic)
1270 {
1271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1272 struct drm_device *dev = crtc->dev;
1273 struct radeon_device *rdev = dev->dev_private;
1274 struct radeon_framebuffer *radeon_fb;
1275 struct drm_gem_object *obj;
1276 struct radeon_bo *rbo;
1277 struct drm_framebuffer *target_fb;
1278 uint64_t fb_location;
1279 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1280 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1281 u32 tmp, viewport_w, viewport_h;
1282 int r;
1283
1284 /* no fb bound */
1285 if (!atomic && !crtc->fb) {
1286 DRM_DEBUG_KMS("No FB bound\n");
1287 return 0;
1288 }
1289
1290 if (atomic) {
1291 radeon_fb = to_radeon_framebuffer(fb);
1292 target_fb = fb;
1293 }
1294 else {
1295 radeon_fb = to_radeon_framebuffer(crtc->fb);
1296 target_fb = crtc->fb;
1297 }
1298
1299 obj = radeon_fb->obj;
1300 rbo = gem_to_radeon_bo(obj);
1301 r = radeon_bo_reserve(rbo, false);
1302 if (unlikely(r != 0))
1303 return r;
1304
1305 /* If atomic, assume fb object is pinned & idle & fenced and
1306 * just update base pointers
1307 */
1308 if (atomic)
1309 fb_location = radeon_bo_gpu_offset(rbo);
1310 else {
1311 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1312 if (unlikely(r != 0)) {
1313 radeon_bo_unreserve(rbo);
1314 return -EINVAL;
1315 }
1316 }
1317 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1318 radeon_bo_unreserve(rbo);
1319
1320 switch (target_fb->bits_per_pixel) {
1321 case 8:
1322 fb_format =
1323 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1324 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1325 break;
1326 case 15:
1327 fb_format =
1328 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1329 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1330 break;
1331 case 16:
1332 fb_format =
1333 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1334 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1335 #ifdef __BIG_ENDIAN
1336 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1337 #endif
1338 break;
1339 case 24:
1340 case 32:
1341 fb_format =
1342 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1343 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1344 #ifdef __BIG_ENDIAN
1345 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1346 #endif
1347 break;
1348 default:
1349 DRM_ERROR("Unsupported screen depth %d\n",
1350 target_fb->bits_per_pixel);
1351 return -EINVAL;
1352 }
1353
1354 if (rdev->family >= CHIP_R600) {
1355 if (tiling_flags & RADEON_TILING_MACRO)
1356 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1357 else if (tiling_flags & RADEON_TILING_MICRO)
1358 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1359 } else {
1360 if (tiling_flags & RADEON_TILING_MACRO)
1361 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1362
1363 if (tiling_flags & RADEON_TILING_MICRO)
1364 fb_format |= AVIVO_D1GRPH_TILED;
1365 }
1366
1367 if (radeon_crtc->crtc_id == 0)
1368 WREG32(AVIVO_D1VGA_CONTROL, 0);
1369 else
1370 WREG32(AVIVO_D2VGA_CONTROL, 0);
1371
1372 if (rdev->family >= CHIP_RV770) {
1373 if (radeon_crtc->crtc_id) {
1374 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1375 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1376 } else {
1377 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1378 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1379 }
1380 }
1381 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1382 (u32) fb_location);
1383 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1384 radeon_crtc->crtc_offset, (u32) fb_location);
1385 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1386 if (rdev->family >= CHIP_R600)
1387 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1388
1389 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1390 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1391 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1392 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1393 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1394 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1395
1396 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1397 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1398 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1399
1400 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1401 target_fb->height);
1402 x &= ~3;
1403 y &= ~1;
1404 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1405 (x << 16) | y);
1406 viewport_w = crtc->mode.hdisplay;
1407 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1408 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1409 (viewport_w << 16) | viewport_h);
1410
1411 /* pageflip setup */
1412 /* make sure flip is at vb rather than hb */
1413 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1414 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1415 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1416
1417 /* set pageflip to happen anywhere in vblank interval */
1418 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1419
1420 if (!atomic && fb && fb != crtc->fb) {
1421 radeon_fb = to_radeon_framebuffer(fb);
1422 rbo = gem_to_radeon_bo(radeon_fb->obj);
1423 r = radeon_bo_reserve(rbo, false);
1424 if (unlikely(r != 0))
1425 return r;
1426 radeon_bo_unpin(rbo);
1427 radeon_bo_unreserve(rbo);
1428 }
1429
1430 /* Bytes per pixel may have changed */
1431 radeon_bandwidth_update(rdev);
1432
1433 return 0;
1434 }
1435
atombios_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)1436 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1437 struct drm_framebuffer *old_fb)
1438 {
1439 struct drm_device *dev = crtc->dev;
1440 struct radeon_device *rdev = dev->dev_private;
1441
1442 if (ASIC_IS_DCE4(rdev))
1443 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1444 else if (ASIC_IS_AVIVO(rdev))
1445 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1446 else
1447 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1448 }
1449
atombios_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)1450 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1451 struct drm_framebuffer *fb,
1452 int x, int y, enum mode_set_atomic state)
1453 {
1454 struct drm_device *dev = crtc->dev;
1455 struct radeon_device *rdev = dev->dev_private;
1456
1457 if (ASIC_IS_DCE4(rdev))
1458 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1459 else if (ASIC_IS_AVIVO(rdev))
1460 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1461 else
1462 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1463 }
1464
1465 /* properly set additional regs when using atombios */
radeon_legacy_atom_fixup(struct drm_crtc * crtc)1466 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1467 {
1468 struct drm_device *dev = crtc->dev;
1469 struct radeon_device *rdev = dev->dev_private;
1470 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1471 u32 disp_merge_cntl;
1472
1473 switch (radeon_crtc->crtc_id) {
1474 case 0:
1475 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1476 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1477 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1478 break;
1479 case 1:
1480 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1481 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1482 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1483 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1484 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1485 break;
1486 }
1487 }
1488
1489 /**
1490 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1491 *
1492 * @crtc: drm crtc
1493 *
1494 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1495 */
radeon_get_pll_use_mask(struct drm_crtc * crtc)1496 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1497 {
1498 struct drm_device *dev = crtc->dev;
1499 struct drm_crtc *test_crtc;
1500 struct radeon_crtc *test_radeon_crtc;
1501 u32 pll_in_use = 0;
1502
1503 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1504 if (crtc == test_crtc)
1505 continue;
1506
1507 test_radeon_crtc = to_radeon_crtc(test_crtc);
1508 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1509 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1510 }
1511 return pll_in_use;
1512 }
1513
1514 /**
1515 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1516 *
1517 * @crtc: drm crtc
1518 *
1519 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1520 * also in DP mode. For DP, a single PPLL can be used for all DP
1521 * crtcs/encoders.
1522 */
radeon_get_shared_dp_ppll(struct drm_crtc * crtc)1523 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1524 {
1525 struct drm_device *dev = crtc->dev;
1526 struct drm_crtc *test_crtc;
1527 struct radeon_crtc *test_radeon_crtc;
1528
1529 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1530 if (crtc == test_crtc)
1531 continue;
1532 test_radeon_crtc = to_radeon_crtc(test_crtc);
1533 if (test_radeon_crtc->encoder &&
1534 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1535 /* for DP use the same PLL for all */
1536 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1537 return test_radeon_crtc->pll_id;
1538 }
1539 }
1540 return ATOM_PPLL_INVALID;
1541 }
1542
1543 /**
1544 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1545 *
1546 * @crtc: drm crtc
1547 * @encoder: drm encoder
1548 *
1549 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1550 * be shared (i.e., same clock).
1551 */
radeon_get_shared_nondp_ppll(struct drm_crtc * crtc)1552 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1553 {
1554 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1555 struct drm_device *dev = crtc->dev;
1556 struct drm_crtc *test_crtc;
1557 struct radeon_crtc *test_radeon_crtc;
1558 u32 adjusted_clock, test_adjusted_clock;
1559
1560 adjusted_clock = radeon_crtc->adjusted_clock;
1561
1562 if (adjusted_clock == 0)
1563 return ATOM_PPLL_INVALID;
1564
1565 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1566 if (crtc == test_crtc)
1567 continue;
1568 test_radeon_crtc = to_radeon_crtc(test_crtc);
1569 if (test_radeon_crtc->encoder &&
1570 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1571 /* check if we are already driving this connector with another crtc */
1572 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1573 /* if we are, return that pll */
1574 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1575 return test_radeon_crtc->pll_id;
1576 }
1577 /* for non-DP check the clock */
1578 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1579 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1580 (adjusted_clock == test_adjusted_clock) &&
1581 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1582 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1583 return test_radeon_crtc->pll_id;
1584 }
1585 }
1586 return ATOM_PPLL_INVALID;
1587 }
1588
1589 /**
1590 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1591 *
1592 * @crtc: drm crtc
1593 *
1594 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1595 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1596 * monitors a dedicated PPLL must be used. If a particular board has
1597 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1598 * as there is no need to program the PLL itself. If we are not able to
1599 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1600 * avoid messing up an existing monitor.
1601 *
1602 * Asic specific PLL information
1603 *
1604 * DCE 6.1
1605 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1606 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1607 *
1608 * DCE 6.0
1609 * - PPLL0 is available to all UNIPHY (DP only)
1610 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1611 *
1612 * DCE 5.0
1613 * - DCPLL is available to all UNIPHY (DP only)
1614 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1615 *
1616 * DCE 3.0/4.0/4.1
1617 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1618 *
1619 */
radeon_atom_pick_pll(struct drm_crtc * crtc)1620 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1621 {
1622 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1623 struct drm_device *dev = crtc->dev;
1624 struct radeon_device *rdev = dev->dev_private;
1625 struct radeon_encoder *radeon_encoder =
1626 to_radeon_encoder(radeon_crtc->encoder);
1627 u32 pll_in_use;
1628 int pll;
1629
1630 if (ASIC_IS_DCE61(rdev)) {
1631 struct radeon_encoder_atom_dig *dig =
1632 radeon_encoder->enc_priv;
1633
1634 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1635 (dig->linkb == false))
1636 /* UNIPHY A uses PPLL2 */
1637 return ATOM_PPLL2;
1638 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1639 /* UNIPHY B/C/D/E/F */
1640 if (rdev->clock.dp_extclk)
1641 /* skip PPLL programming if using ext clock */
1642 return ATOM_PPLL_INVALID;
1643 else {
1644 /* use the same PPLL for all DP monitors */
1645 pll = radeon_get_shared_dp_ppll(crtc);
1646 if (pll != ATOM_PPLL_INVALID)
1647 return pll;
1648 }
1649 } else {
1650 /* use the same PPLL for all monitors with the same clock */
1651 pll = radeon_get_shared_nondp_ppll(crtc);
1652 if (pll != ATOM_PPLL_INVALID)
1653 return pll;
1654 }
1655 /* UNIPHY B/C/D/E/F */
1656 pll_in_use = radeon_get_pll_use_mask(crtc);
1657 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1658 return ATOM_PPLL0;
1659 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1660 return ATOM_PPLL1;
1661 DRM_ERROR("unable to allocate a PPLL\n");
1662 return ATOM_PPLL_INVALID;
1663 } else if (ASIC_IS_DCE4(rdev)) {
1664 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1665 * depending on the asic:
1666 * DCE4: PPLL or ext clock
1667 * DCE5: PPLL, DCPLL, or ext clock
1668 * DCE6: PPLL, PPLL0, or ext clock
1669 *
1670 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1671 * PPLL/DCPLL programming and only program the DP DTO for the
1672 * crtc virtual pixel clock.
1673 */
1674 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1675 if (rdev->clock.dp_extclk)
1676 /* skip PPLL programming if using ext clock */
1677 return ATOM_PPLL_INVALID;
1678 else if (ASIC_IS_DCE6(rdev))
1679 /* use PPLL0 for all DP */
1680 return ATOM_PPLL0;
1681 else if (ASIC_IS_DCE5(rdev))
1682 /* use DCPLL for all DP */
1683 return ATOM_DCPLL;
1684 else {
1685 /* use the same PPLL for all DP monitors */
1686 pll = radeon_get_shared_dp_ppll(crtc);
1687 if (pll != ATOM_PPLL_INVALID)
1688 return pll;
1689 }
1690 } else {
1691 /* use the same PPLL for all monitors with the same clock */
1692 pll = radeon_get_shared_nondp_ppll(crtc);
1693 if (pll != ATOM_PPLL_INVALID)
1694 return pll;
1695 }
1696 /* all other cases */
1697 pll_in_use = radeon_get_pll_use_mask(crtc);
1698 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1699 return ATOM_PPLL1;
1700 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1701 return ATOM_PPLL2;
1702 DRM_ERROR("unable to allocate a PPLL\n");
1703 return ATOM_PPLL_INVALID;
1704 } else {
1705 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1706 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1707 * the matching btw pll and crtc is done through
1708 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1709 * pll (1 or 2) to select which register to write. ie if using
1710 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1711 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1712 * choose which value to write. Which is reverse order from
1713 * register logic. So only case that works is when pllid is
1714 * same as crtcid or when both pll and crtc are enabled and
1715 * both use same clock.
1716 *
1717 * So just return crtc id as if crtc and pll were hard linked
1718 * together even if they aren't
1719 */
1720 return radeon_crtc->crtc_id;
1721 }
1722 }
1723
radeon_atom_disp_eng_pll_init(struct radeon_device * rdev)1724 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1725 {
1726 /* always set DCPLL */
1727 if (ASIC_IS_DCE6(rdev))
1728 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1729 else if (ASIC_IS_DCE4(rdev)) {
1730 struct radeon_atom_ss ss;
1731 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1732 ASIC_INTERNAL_SS_ON_DCPLL,
1733 rdev->clock.default_dispclk);
1734 if (ss_enabled)
1735 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1736 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1737 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1738 if (ss_enabled)
1739 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1740 }
1741
1742 }
1743
atombios_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)1744 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1745 struct drm_display_mode *mode,
1746 struct drm_display_mode *adjusted_mode,
1747 int x, int y, struct drm_framebuffer *old_fb)
1748 {
1749 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1750 struct drm_device *dev = crtc->dev;
1751 struct radeon_device *rdev = dev->dev_private;
1752 struct radeon_encoder *radeon_encoder =
1753 to_radeon_encoder(radeon_crtc->encoder);
1754 bool is_tvcv = false;
1755
1756 if (radeon_encoder->active_device &
1757 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1758 is_tvcv = true;
1759
1760 atombios_crtc_set_pll(crtc, adjusted_mode);
1761
1762 if (ASIC_IS_DCE4(rdev))
1763 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1764 else if (ASIC_IS_AVIVO(rdev)) {
1765 if (is_tvcv)
1766 atombios_crtc_set_timing(crtc, adjusted_mode);
1767 else
1768 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1769 } else {
1770 atombios_crtc_set_timing(crtc, adjusted_mode);
1771 if (radeon_crtc->crtc_id == 0)
1772 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1773 radeon_legacy_atom_fixup(crtc);
1774 }
1775 atombios_crtc_set_base(crtc, x, y, old_fb);
1776 atombios_overscan_setup(crtc, mode, adjusted_mode);
1777 atombios_scaler_setup(crtc);
1778 return 0;
1779 }
1780
atombios_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1781 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1782 const struct drm_display_mode *mode,
1783 struct drm_display_mode *adjusted_mode)
1784 {
1785 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1786 struct drm_device *dev = crtc->dev;
1787 struct drm_encoder *encoder;
1788
1789 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1790 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1791 if (encoder->crtc == crtc) {
1792 radeon_crtc->encoder = encoder;
1793 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1794 break;
1795 }
1796 }
1797 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1798 radeon_crtc->encoder = NULL;
1799 radeon_crtc->connector = NULL;
1800 return false;
1801 }
1802 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1803 return false;
1804 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1805 return false;
1806 /* pick pll */
1807 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1808 /* if we can't get a PPLL for a non-DP encoder, fail */
1809 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1810 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1811 return false;
1812
1813 return true;
1814 }
1815
atombios_crtc_prepare(struct drm_crtc * crtc)1816 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1817 {
1818 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1819 struct drm_device *dev = crtc->dev;
1820 struct radeon_device *rdev = dev->dev_private;
1821
1822 radeon_crtc->in_mode_set = true;
1823
1824 /* disable crtc pair power gating before programming */
1825 if (ASIC_IS_DCE6(rdev))
1826 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1827
1828 atombios_lock_crtc(crtc, ATOM_ENABLE);
1829 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1830 }
1831
atombios_crtc_commit(struct drm_crtc * crtc)1832 static void atombios_crtc_commit(struct drm_crtc *crtc)
1833 {
1834 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1835
1836 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1837 atombios_lock_crtc(crtc, ATOM_DISABLE);
1838 radeon_crtc->in_mode_set = false;
1839 }
1840
atombios_crtc_disable(struct drm_crtc * crtc)1841 static void atombios_crtc_disable(struct drm_crtc *crtc)
1842 {
1843 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1844 struct drm_device *dev = crtc->dev;
1845 struct radeon_device *rdev = dev->dev_private;
1846 struct radeon_atom_ss ss;
1847 int i;
1848
1849 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1850 if (ASIC_IS_DCE6(rdev))
1851 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1852
1853 for (i = 0; i < rdev->num_crtc; i++) {
1854 if (rdev->mode_info.crtcs[i] &&
1855 rdev->mode_info.crtcs[i]->enabled &&
1856 i != radeon_crtc->crtc_id &&
1857 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1858 /* one other crtc is using this pll don't turn
1859 * off the pll
1860 */
1861 goto done;
1862 }
1863 }
1864
1865 switch (radeon_crtc->pll_id) {
1866 case ATOM_PPLL1:
1867 case ATOM_PPLL2:
1868 /* disable the ppll */
1869 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1870 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1871 break;
1872 case ATOM_PPLL0:
1873 /* disable the ppll */
1874 if (ASIC_IS_DCE61(rdev))
1875 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1876 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1877 break;
1878 default:
1879 break;
1880 }
1881 done:
1882 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1883 radeon_crtc->adjusted_clock = 0;
1884 radeon_crtc->encoder = NULL;
1885 radeon_crtc->connector = NULL;
1886 }
1887
1888 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1889 .dpms = atombios_crtc_dpms,
1890 .mode_fixup = atombios_crtc_mode_fixup,
1891 .mode_set = atombios_crtc_mode_set,
1892 .mode_set_base = atombios_crtc_set_base,
1893 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1894 .prepare = atombios_crtc_prepare,
1895 .commit = atombios_crtc_commit,
1896 .load_lut = radeon_crtc_load_lut,
1897 .disable = atombios_crtc_disable,
1898 };
1899
radeon_atombios_init_crtc(struct drm_device * dev,struct radeon_crtc * radeon_crtc)1900 void radeon_atombios_init_crtc(struct drm_device *dev,
1901 struct radeon_crtc *radeon_crtc)
1902 {
1903 struct radeon_device *rdev = dev->dev_private;
1904
1905 if (ASIC_IS_DCE4(rdev)) {
1906 switch (radeon_crtc->crtc_id) {
1907 case 0:
1908 default:
1909 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1910 break;
1911 case 1:
1912 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1913 break;
1914 case 2:
1915 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1916 break;
1917 case 3:
1918 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1919 break;
1920 case 4:
1921 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1922 break;
1923 case 5:
1924 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1925 break;
1926 }
1927 } else {
1928 if (radeon_crtc->crtc_id == 1)
1929 radeon_crtc->crtc_offset =
1930 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1931 else
1932 radeon_crtc->crtc_offset = 0;
1933 }
1934 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1935 radeon_crtc->adjusted_clock = 0;
1936 radeon_crtc->encoder = NULL;
1937 radeon_crtc->connector = NULL;
1938 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1939 }
1940