1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35
36 #include <sys/gpio.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/rman.h>
42
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
46
47 #include <dev/fdt/simplebus.h>
48
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51
52 #include <dev/fdt/fdt_pinctrl.h>
53
54 #include <dev/extres/syscon/syscon.h>
55
56 #include "gpio_if.h"
57 #include "syscon_if.h"
58 #include "fdt_pinctrl_if.h"
59
60 struct rk_pinctrl_pin_drive {
61 uint32_t bank;
62 uint32_t subbank;
63 uint32_t offset;
64 uint32_t value;
65 uint32_t ma;
66 };
67
68 struct rk_pinctrl_bank {
69 uint32_t bank;
70 uint32_t subbank;
71 uint32_t offset;
72 uint32_t nbits;
73 };
74
75 struct rk_pinctrl_pin_fixup {
76 uint32_t bank;
77 uint32_t subbank;
78 uint32_t pin;
79 uint32_t reg;
80 uint32_t bit;
81 uint32_t mask;
82 };
83
84 struct rk_pinctrl_gpio {
85 uint32_t bank;
86 char *gpio_name;
87 device_t gpio_dev;
88 };
89
90 struct rk_pinctrl_softc;
91
92 struct rk_pinctrl_conf {
93 struct rk_pinctrl_bank *iomux_conf;
94 uint32_t iomux_nbanks;
95 struct rk_pinctrl_pin_fixup *pin_fixup;
96 uint32_t npin_fixup;
97 struct rk_pinctrl_pin_drive *pin_drive;
98 uint32_t npin_drive;
99 struct rk_pinctrl_gpio *gpio_bank;
100 uint32_t ngpio_bank;
101 uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t);
102 struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t);
103 int (*parse_bias)(phandle_t, int);
104 int (*resolv_bias_value)(int, int);
105 int (*get_bias_value)(int, int);
106 };
107
108 struct rk_pinctrl_softc {
109 struct simplebus_softc simplebus_sc;
110 device_t dev;
111 struct syscon *grf;
112 struct syscon *pmu;
113 struct rk_pinctrl_conf *conf;
114 struct mtx mtx;
115 };
116
117 #define RK_PINCTRL_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx)
118 #define RK_PINCTRL_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx)
119 #define RK_PINCTRL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
120
121 #define RK_IOMUX(_bank, _subbank, _offset, _nbits) \
122 { \
123 .bank = _bank, \
124 .subbank = _subbank, \
125 .offset = _offset, \
126 .nbits = _nbits, \
127 }
128
129 #define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \
130 { \
131 .bank = _bank, \
132 .pin = _pin, \
133 .reg = _reg, \
134 .bit = _bit, \
135 .mask = _mask, \
136 }
137
138 #define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \
139 { \
140 .bank = _bank, \
141 .subbank = _subbank, \
142 .offset = _offset, \
143 .value = _value, \
144 .ma = _ma, \
145 }
146 #define RK_GPIO(_bank, _name) \
147 { \
148 .bank = _bank, \
149 .gpio_name = _name, \
150 }
151
152 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = {
153 RK_GPIO(0, "gpio0"),
154 RK_GPIO(1, "gpio1"),
155 RK_GPIO(2, "gpio2"),
156 RK_GPIO(3, "gpio3"),
157 RK_GPIO(4, "gpio4"),
158 RK_GPIO(5, "gpio5"),
159 RK_GPIO(6, "gpio6"),
160 RK_GPIO(7, "gpio7"),
161 RK_GPIO(8, "gpio8"),
162 };
163
164 static struct rk_pinctrl_bank rk3288_iomux_bank[] = {
165 /* bank sub offs nbits */
166 /* PMU */
167 RK_IOMUX(0, 0, 0x0084, 2),
168 RK_IOMUX(0, 1, 0x0088, 2),
169 RK_IOMUX(0, 2, 0x008C, 2),
170 /* GFR */
171 RK_IOMUX(1, 3, 0x000C, 2),
172 RK_IOMUX(2, 0, 0x0010, 2),
173 RK_IOMUX(2, 1, 0x0014, 2),
174 RK_IOMUX(2, 2, 0x0018, 2),
175 RK_IOMUX(2, 3, 0x001C, 2),
176 RK_IOMUX(3, 0, 0x0020, 2),
177 RK_IOMUX(3, 1, 0x0024, 2),
178 RK_IOMUX(3, 2, 0x0028, 2),
179 RK_IOMUX(3, 3, 0x002C, 4),
180 RK_IOMUX(4, 0, 0x0034, 4),
181 RK_IOMUX(4, 1, 0x003C, 4),
182 RK_IOMUX(4, 2, 0x0044, 2),
183 RK_IOMUX(4, 3, 0x0048, 2),
184 /* 5,0 - Empty */
185 RK_IOMUX(5, 1, 0x0050, 2),
186 RK_IOMUX(5, 2, 0x0054, 2),
187 /* 5,3 - Empty */
188 RK_IOMUX(6, 0, 0x005C, 2),
189 RK_IOMUX(6, 1, 0x0060, 2),
190 RK_IOMUX(6, 2, 0x0064, 2),
191 /* 6,3 - Empty */
192 RK_IOMUX(7, 0, 0x006C, 2),
193 RK_IOMUX(7, 1, 0x0070, 2),
194 RK_IOMUX(7, 2, 0x0074, 4),
195 /* 7,3 - Empty */
196 RK_IOMUX(8, 0, 0x0080, 2),
197 RK_IOMUX(8, 1, 0x0084, 2),
198 /* 8,2 - Empty */
199 /* 8,3 - Empty */
200
201 };
202
203 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = {
204 };
205
206 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = {
207 /* bank sub offs val ma */
208 /* GPIO0A (PMU)*/
209 RK_PINDRIVE(0, 0, 0x070, 0, 2),
210 RK_PINDRIVE(0, 0, 0x070, 1, 4),
211 RK_PINDRIVE(0, 0, 0x070, 2, 8),
212 RK_PINDRIVE(0, 0, 0x070, 3, 12),
213
214 /* GPIO0B (PMU)*/
215 RK_PINDRIVE(0, 1, 0x074, 0, 2),
216 RK_PINDRIVE(0, 1, 0x074, 1, 4),
217 RK_PINDRIVE(0, 1, 0x074, 2, 8),
218 RK_PINDRIVE(0, 1, 0x074, 3, 12),
219
220 /* GPIO0C (PMU)*/
221 RK_PINDRIVE(0, 2, 0x078, 0, 2),
222 RK_PINDRIVE(0, 2, 0x078, 1, 4),
223 RK_PINDRIVE(0, 2, 0x078, 2, 8),
224 RK_PINDRIVE(0, 2, 0x078, 3, 12),
225
226 /* GPIO1D */
227 RK_PINDRIVE(1, 3, 0x1CC, 0, 2),
228 RK_PINDRIVE(1, 3, 0x1CC, 1, 4),
229 RK_PINDRIVE(1, 3, 0x1CC, 2, 8),
230 RK_PINDRIVE(1, 3, 0x1CC, 3, 12),
231
232 /* GPIO2A */
233 RK_PINDRIVE(2, 0, 0x1D0, 0, 2),
234 RK_PINDRIVE(2, 0, 0x1D0, 1, 4),
235 RK_PINDRIVE(2, 0, 0x1D0, 2, 8),
236 RK_PINDRIVE(2, 0, 0x1D0, 3, 12),
237
238 /* GPIO2B */
239 RK_PINDRIVE(2, 1, 0x1D4, 0, 2),
240 RK_PINDRIVE(2, 1, 0x1D4, 1, 4),
241 RK_PINDRIVE(2, 1, 0x1D4, 2, 8),
242 RK_PINDRIVE(2, 1, 0x1D4, 3, 12),
243
244 /* GPIO2C */
245 RK_PINDRIVE(2, 2, 0x1D8, 0, 2),
246 RK_PINDRIVE(2, 2, 0x1D8, 1, 4),
247 RK_PINDRIVE(2, 2, 0x1D8, 2, 8),
248 RK_PINDRIVE(2, 2, 0x1D8, 3, 12),
249
250 /* GPIO2D */
251 RK_PINDRIVE(2, 3, 0x1DC, 0, 2),
252 RK_PINDRIVE(2, 3, 0x1DC, 1, 4),
253 RK_PINDRIVE(2, 3, 0x1DC, 2, 8),
254 RK_PINDRIVE(2, 3, 0x1DC, 3, 12),
255
256 /* GPIO3A */
257 RK_PINDRIVE(3, 0, 0x1E0, 0, 2),
258 RK_PINDRIVE(3, 0, 0x1E0, 1, 4),
259 RK_PINDRIVE(3, 0, 0x1E0, 2, 8),
260 RK_PINDRIVE(3, 0, 0x1E0, 3, 12),
261
262 /* GPIO3B */
263 RK_PINDRIVE(3, 1, 0x1E4, 0, 2),
264 RK_PINDRIVE(3, 1, 0x1E4, 1, 4),
265 RK_PINDRIVE(3, 1, 0x1E4, 2, 8),
266 RK_PINDRIVE(3, 1, 0x1E4, 3, 12),
267
268 /* GPIO3C */
269 RK_PINDRIVE(3, 2, 0x1E8, 0, 2),
270 RK_PINDRIVE(3, 2, 0x1E8, 1, 4),
271 RK_PINDRIVE(3, 2, 0x1E8, 2, 8),
272 RK_PINDRIVE(3, 2, 0x1E8, 3, 12),
273
274 /* GPIO3D */
275 RK_PINDRIVE(3, 3, 0x1EC, 0, 2),
276 RK_PINDRIVE(3, 3, 0x1EC, 1, 4),
277 RK_PINDRIVE(3, 3, 0x1EC, 2, 8),
278 RK_PINDRIVE(3, 3, 0x1EC, 3, 12),
279
280 /* GPIO4A */
281 RK_PINDRIVE(4, 0, 0x1F0, 0, 2),
282 RK_PINDRIVE(4, 0, 0x1F0, 1, 4),
283 RK_PINDRIVE(4, 0, 0x1F0, 2, 8),
284 RK_PINDRIVE(4, 0, 0x1F0, 3, 12),
285
286 /* GPIO4B */
287 RK_PINDRIVE(4, 1, 0x1F4, 0, 2),
288 RK_PINDRIVE(4, 1, 0x1F4, 1, 4),
289 RK_PINDRIVE(4, 1, 0x1F4, 2, 8),
290 RK_PINDRIVE(4, 1, 0x1F4, 3, 12),
291
292 /* GPIO4C */
293 RK_PINDRIVE(4, 2, 0x1F8, 0, 2),
294 RK_PINDRIVE(4, 2, 0x1F8, 1, 4),
295 RK_PINDRIVE(4, 2, 0x1F8, 2, 8),
296 RK_PINDRIVE(4, 2, 0x1F8, 3, 12),
297
298 /* GPIO4D */
299 RK_PINDRIVE(4, 3, 0x1FC, 0, 2),
300 RK_PINDRIVE(4, 3, 0x1FC, 1, 4),
301 RK_PINDRIVE(4, 3, 0x1FC, 2, 8),
302 RK_PINDRIVE(4, 3, 0x1FC, 3, 12),
303
304 /* GPIO5B */
305 RK_PINDRIVE(5, 1, 0x204, 0, 2),
306 RK_PINDRIVE(5, 1, 0x204, 1, 4),
307 RK_PINDRIVE(5, 1, 0x204, 2, 8),
308 RK_PINDRIVE(5, 1, 0x204, 3, 12),
309
310 /* GPIO5C */
311 RK_PINDRIVE(5, 2, 0x208, 0, 2),
312 RK_PINDRIVE(5, 2, 0x208, 1, 4),
313 RK_PINDRIVE(5, 2, 0x208, 2, 8),
314 RK_PINDRIVE(5, 2, 0x208, 3, 12),
315
316 /* GPIO6A */
317 RK_PINDRIVE(6, 0, 0x210, 0, 2),
318 RK_PINDRIVE(6, 0, 0x210, 1, 4),
319 RK_PINDRIVE(6, 0, 0x210, 2, 8),
320 RK_PINDRIVE(6, 0, 0x210, 3, 12),
321
322 /* GPIO6B */
323 RK_PINDRIVE(6, 1, 0x214, 0, 2),
324 RK_PINDRIVE(6, 1, 0x214, 1, 4),
325 RK_PINDRIVE(6, 1, 0x214, 2, 8),
326 RK_PINDRIVE(6, 1, 0x214, 3, 12),
327
328 /* GPIO6C */
329 RK_PINDRIVE(6, 2, 0x218, 0, 2),
330 RK_PINDRIVE(6, 2, 0x218, 1, 4),
331 RK_PINDRIVE(6, 2, 0x218, 2, 8),
332 RK_PINDRIVE(6, 2, 0x218, 3, 12),
333
334 /* GPIO7A */
335 RK_PINDRIVE(7, 0, 0x220, 0, 2),
336 RK_PINDRIVE(7, 0, 0x220, 1, 4),
337 RK_PINDRIVE(7, 0, 0x220, 2, 8),
338 RK_PINDRIVE(7, 0, 0x220, 3, 12),
339
340 /* GPIO7B */
341 RK_PINDRIVE(7, 1, 0x224, 0, 2),
342 RK_PINDRIVE(7, 1, 0x224, 1, 4),
343 RK_PINDRIVE(7, 1, 0x224, 2, 8),
344 RK_PINDRIVE(7, 1, 0x224, 3, 12),
345
346 /* GPIO7C */
347 RK_PINDRIVE(7, 2, 0x228, 0, 2),
348 RK_PINDRIVE(7, 2, 0x228, 1, 4),
349 RK_PINDRIVE(7, 2, 0x228, 2, 8),
350 RK_PINDRIVE(7, 2, 0x228, 3, 12),
351
352 /* GPIO8A */
353 RK_PINDRIVE(8, 0, 0x230, 0, 2),
354 RK_PINDRIVE(8, 0, 0x230, 1, 4),
355 RK_PINDRIVE(8, 0, 0x230, 2, 8),
356 RK_PINDRIVE(8, 0, 0x230, 3, 12),
357
358 /* GPIO8B */
359 RK_PINDRIVE(8, 1, 0x234, 0, 2),
360 RK_PINDRIVE(8, 1, 0x234, 1, 4),
361 RK_PINDRIVE(8, 1, 0x234, 2, 8),
362 RK_PINDRIVE(8, 1, 0x234, 3, 12),
363 };
364
365 static uint32_t
rk3288_get_pd_offset(struct rk_pinctrl_softc * sc,uint32_t bank)366 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
367 {
368 if (bank == 0)
369 return (0x064); /* PMU */
370 return (0x130);
371 }
372
373 static struct syscon *
rk3288_get_syscon(struct rk_pinctrl_softc * sc,uint32_t bank)374 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
375 {
376 if (bank == 0)
377 return (sc->pmu);
378 return (sc->grf);
379 }
380
381 static int
rk3288_parse_bias(phandle_t node,int bank)382 rk3288_parse_bias(phandle_t node, int bank)
383 {
384 if (OF_hasprop(node, "bias-disable"))
385 return (0);
386 if (OF_hasprop(node, "bias-pull-up"))
387 return (1);
388 if (OF_hasprop(node, "bias-pull-down"))
389 return (2);
390
391 return (-1);
392 }
393
394 static int
rk3288_resolv_bias_value(int bank,int bias)395 rk3288_resolv_bias_value(int bank, int bias)
396 {
397 int rv = 0;
398
399 if (bias == 1)
400 rv = GPIO_PIN_PULLUP;
401 else if (bias == 2)
402 rv = GPIO_PIN_PULLDOWN;
403
404 return (rv);
405 }
406
407 static int
rk3288_get_bias_value(int bank,int bias)408 rk3288_get_bias_value(int bank, int bias)
409 {
410 int rv = 0;
411
412 if (bias & GPIO_PIN_PULLUP)
413 rv = 1;
414 else if (bias & GPIO_PIN_PULLDOWN)
415 rv = 2;
416
417 return (rv);
418 }
419
420 struct rk_pinctrl_conf rk3288_conf = {
421 .iomux_conf = rk3288_iomux_bank,
422 .iomux_nbanks = nitems(rk3288_iomux_bank),
423 .pin_fixup = rk3288_pin_fixup,
424 .npin_fixup = nitems(rk3288_pin_fixup),
425 .pin_drive = rk3288_pin_drive,
426 .npin_drive = nitems(rk3288_pin_drive),
427 .gpio_bank = rk3288_gpio_bank,
428 .ngpio_bank = nitems(rk3288_gpio_bank),
429 .get_pd_offset = rk3288_get_pd_offset,
430 .get_syscon = rk3288_get_syscon,
431 .parse_bias = rk3288_parse_bias,
432 .resolv_bias_value = rk3288_resolv_bias_value,
433 .get_bias_value = rk3288_get_bias_value,
434 };
435
436 static struct rk_pinctrl_gpio rk3328_gpio_bank[] = {
437 RK_GPIO(0, "gpio0"),
438 RK_GPIO(1, "gpio1"),
439 RK_GPIO(2, "gpio2"),
440 RK_GPIO(3, "gpio3"),
441 };
442
443 static struct rk_pinctrl_bank rk3328_iomux_bank[] = {
444 /* bank sub offs nbits */
445 RK_IOMUX(0, 0, 0x0000, 2),
446 RK_IOMUX(0, 1, 0x0004, 2),
447 RK_IOMUX(0, 2, 0x0008, 2),
448 RK_IOMUX(0, 3, 0x000C, 2),
449 RK_IOMUX(1, 0, 0x0010, 2),
450 RK_IOMUX(1, 1, 0x0014, 2),
451 RK_IOMUX(1, 2, 0x0018, 2),
452 RK_IOMUX(1, 3, 0x001C, 2),
453 RK_IOMUX(2, 0, 0x0020, 2),
454 RK_IOMUX(2, 1, 0x0024, 3),
455 RK_IOMUX(2, 2, 0x002c, 3),
456 RK_IOMUX(2, 3, 0x0034, 2),
457 RK_IOMUX(3, 0, 0x0038, 3),
458 RK_IOMUX(3, 1, 0x0040, 3),
459 RK_IOMUX(3, 2, 0x0048, 2),
460 RK_IOMUX(3, 3, 0x004c, 2),
461 };
462
463 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = {
464 /* bank pin reg bit mask */
465 RK_PINFIX(2, 12, 0x24, 8, 0x300),
466 RK_PINFIX(2, 15, 0x28, 0, 0x7),
467 RK_PINFIX(2, 23, 0x30, 14, 0x6000),
468 };
469
470 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = {
471 /* bank sub offs val ma */
472 RK_PINDRIVE(0, 0, 0x200, 0, 2),
473 RK_PINDRIVE(0, 0, 0x200, 1, 4),
474 RK_PINDRIVE(0, 0, 0x200, 2, 8),
475 RK_PINDRIVE(0, 0, 0x200, 3, 12),
476
477 RK_PINDRIVE(0, 1, 0x204, 0, 2),
478 RK_PINDRIVE(0, 1, 0x204, 1, 4),
479 RK_PINDRIVE(0, 1, 0x204, 2, 8),
480 RK_PINDRIVE(0, 1, 0x204, 3, 12),
481
482 RK_PINDRIVE(0, 2, 0x208, 0, 2),
483 RK_PINDRIVE(0, 2, 0x208, 1, 4),
484 RK_PINDRIVE(0, 2, 0x208, 2, 8),
485 RK_PINDRIVE(0, 2, 0x208, 3, 12),
486
487 RK_PINDRIVE(0, 3, 0x20C, 0, 2),
488 RK_PINDRIVE(0, 3, 0x20C, 1, 4),
489 RK_PINDRIVE(0, 3, 0x20C, 2, 8),
490 RK_PINDRIVE(0, 3, 0x20C, 3, 12),
491
492 RK_PINDRIVE(1, 0, 0x210, 0, 2),
493 RK_PINDRIVE(1, 0, 0x210, 1, 4),
494 RK_PINDRIVE(1, 0, 0x210, 2, 8),
495 RK_PINDRIVE(1, 0, 0x210, 3, 12),
496
497 RK_PINDRIVE(1, 1, 0x214, 0, 2),
498 RK_PINDRIVE(1, 1, 0x214, 1, 4),
499 RK_PINDRIVE(1, 1, 0x214, 2, 8),
500 RK_PINDRIVE(1, 1, 0x214, 3, 12),
501
502 RK_PINDRIVE(1, 2, 0x218, 0, 2),
503 RK_PINDRIVE(1, 2, 0x218, 1, 4),
504 RK_PINDRIVE(1, 2, 0x218, 2, 8),
505 RK_PINDRIVE(1, 2, 0x218, 3, 12),
506
507 RK_PINDRIVE(1, 3, 0x21C, 0, 2),
508 RK_PINDRIVE(1, 3, 0x21C, 1, 4),
509 RK_PINDRIVE(1, 3, 0x21C, 2, 8),
510 RK_PINDRIVE(1, 3, 0x21C, 3, 12),
511
512 RK_PINDRIVE(2, 0, 0x220, 0, 2),
513 RK_PINDRIVE(2, 0, 0x220, 1, 4),
514 RK_PINDRIVE(2, 0, 0x220, 2, 8),
515 RK_PINDRIVE(2, 0, 0x220, 3, 12),
516
517 RK_PINDRIVE(2, 1, 0x224, 0, 2),
518 RK_PINDRIVE(2, 1, 0x224, 1, 4),
519 RK_PINDRIVE(2, 1, 0x224, 2, 8),
520 RK_PINDRIVE(2, 1, 0x224, 3, 12),
521
522 RK_PINDRIVE(2, 2, 0x228, 0, 2),
523 RK_PINDRIVE(2, 2, 0x228, 1, 4),
524 RK_PINDRIVE(2, 2, 0x228, 2, 8),
525 RK_PINDRIVE(2, 2, 0x228, 3, 12),
526
527 RK_PINDRIVE(2, 3, 0x22C, 0, 2),
528 RK_PINDRIVE(2, 3, 0x22C, 1, 4),
529 RK_PINDRIVE(2, 3, 0x22C, 2, 8),
530 RK_PINDRIVE(2, 3, 0x22C, 3, 12),
531
532 RK_PINDRIVE(3, 0, 0x230, 0, 2),
533 RK_PINDRIVE(3, 0, 0x230, 1, 4),
534 RK_PINDRIVE(3, 0, 0x230, 2, 8),
535 RK_PINDRIVE(3, 0, 0x230, 3, 12),
536
537 RK_PINDRIVE(3, 1, 0x234, 0, 2),
538 RK_PINDRIVE(3, 1, 0x234, 1, 4),
539 RK_PINDRIVE(3, 1, 0x234, 2, 8),
540 RK_PINDRIVE(3, 1, 0x234, 3, 12),
541
542 RK_PINDRIVE(3, 2, 0x238, 0, 2),
543 RK_PINDRIVE(3, 2, 0x238, 1, 4),
544 RK_PINDRIVE(3, 2, 0x238, 2, 8),
545 RK_PINDRIVE(3, 2, 0x238, 3, 12),
546
547 RK_PINDRIVE(3, 3, 0x23C, 0, 2),
548 RK_PINDRIVE(3, 3, 0x23C, 1, 4),
549 RK_PINDRIVE(3, 3, 0x23C, 2, 8),
550 RK_PINDRIVE(3, 3, 0x23C, 3, 12),
551 };
552
553 static uint32_t
rk3328_get_pd_offset(struct rk_pinctrl_softc * sc,uint32_t bank)554 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
555 {
556 return (0x100);
557 }
558
559 static struct syscon *
rk3328_get_syscon(struct rk_pinctrl_softc * sc,uint32_t bank)560 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
561 {
562 return (sc->grf);
563 }
564
565 struct rk_pinctrl_conf rk3328_conf = {
566 .iomux_conf = rk3328_iomux_bank,
567 .iomux_nbanks = nitems(rk3328_iomux_bank),
568 .pin_fixup = rk3328_pin_fixup,
569 .npin_fixup = nitems(rk3328_pin_fixup),
570 .pin_drive = rk3328_pin_drive,
571 .npin_drive = nitems(rk3328_pin_drive),
572 .gpio_bank = rk3328_gpio_bank,
573 .ngpio_bank = nitems(rk3328_gpio_bank),
574 .get_pd_offset = rk3328_get_pd_offset,
575 .get_syscon = rk3328_get_syscon,
576 .parse_bias = rk3288_parse_bias,
577 .resolv_bias_value = rk3288_resolv_bias_value,
578 .get_bias_value = rk3288_get_bias_value,
579 };
580
581 static struct rk_pinctrl_gpio rk3399_gpio_bank[] = {
582 RK_GPIO(0, "gpio0"),
583 RK_GPIO(1, "gpio1"),
584 RK_GPIO(2, "gpio2"),
585 RK_GPIO(3, "gpio3"),
586 RK_GPIO(4, "gpio4"),
587 };
588
589 static struct rk_pinctrl_bank rk3399_iomux_bank[] = {
590 /* bank sub offs nbits */
591 RK_IOMUX(0, 0, 0x0000, 2),
592 RK_IOMUX(0, 1, 0x0004, 2),
593 RK_IOMUX(0, 2, 0x0008, 2),
594 RK_IOMUX(0, 3, 0x000C, 2),
595 RK_IOMUX(1, 0, 0x0010, 2),
596 RK_IOMUX(1, 1, 0x0014, 2),
597 RK_IOMUX(1, 2, 0x0018, 2),
598 RK_IOMUX(1, 3, 0x001C, 2),
599 RK_IOMUX(2, 0, 0xE000, 2),
600 RK_IOMUX(2, 1, 0xE004, 2),
601 RK_IOMUX(2, 2, 0xE008, 2),
602 RK_IOMUX(2, 3, 0xE00C, 2),
603 RK_IOMUX(3, 0, 0xE010, 2),
604 RK_IOMUX(3, 1, 0xE014, 2),
605 RK_IOMUX(3, 2, 0xE018, 2),
606 RK_IOMUX(3, 3, 0xE01C, 2),
607 RK_IOMUX(4, 0, 0xE020, 2),
608 RK_IOMUX(4, 1, 0xE024, 2),
609 RK_IOMUX(4, 2, 0xE028, 2),
610 RK_IOMUX(4, 3, 0xE02C, 2),
611 };
612
613 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {};
614
615 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = {
616 /* bank sub offs val ma */
617 /* GPIO0A */
618 RK_PINDRIVE(0, 0, 0x80, 0, 5),
619 RK_PINDRIVE(0, 0, 0x80, 1, 10),
620 RK_PINDRIVE(0, 0, 0x80, 2, 15),
621 RK_PINDRIVE(0, 0, 0x80, 3, 20),
622
623 /* GPIOB */
624 RK_PINDRIVE(0, 1, 0x88, 0, 5),
625 RK_PINDRIVE(0, 1, 0x88, 1, 10),
626 RK_PINDRIVE(0, 1, 0x88, 2, 15),
627 RK_PINDRIVE(0, 1, 0x88, 3, 20),
628
629 /* GPIO1A */
630 RK_PINDRIVE(1, 0, 0xA0, 0, 3),
631 RK_PINDRIVE(1, 0, 0xA0, 1, 6),
632 RK_PINDRIVE(1, 0, 0xA0, 2, 9),
633 RK_PINDRIVE(1, 0, 0xA0, 3, 12),
634
635 /* GPIO1B */
636 RK_PINDRIVE(1, 1, 0xA8, 0, 3),
637 RK_PINDRIVE(1, 1, 0xA8, 1, 6),
638 RK_PINDRIVE(1, 1, 0xA8, 2, 9),
639 RK_PINDRIVE(1, 1, 0xA8, 3, 12),
640
641 /* GPIO1C */
642 RK_PINDRIVE(1, 2, 0xB0, 0, 3),
643 RK_PINDRIVE(1, 2, 0xB0, 1, 6),
644 RK_PINDRIVE(1, 2, 0xB0, 2, 9),
645 RK_PINDRIVE(1, 2, 0xB0, 3, 12),
646
647 /* GPIO1D */
648 RK_PINDRIVE(1, 3, 0xB8, 0, 3),
649 RK_PINDRIVE(1, 3, 0xB8, 1, 6),
650 RK_PINDRIVE(1, 3, 0xB8, 2, 9),
651 RK_PINDRIVE(1, 3, 0xB8, 3, 12),
652 };
653
654 static uint32_t
rk3399_get_pd_offset(struct rk_pinctrl_softc * sc,uint32_t bank)655 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
656 {
657 if (bank < 2)
658 return (0x40);
659
660 return (0xE040);
661 }
662
663 static struct syscon *
rk3399_get_syscon(struct rk_pinctrl_softc * sc,uint32_t bank)664 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
665 {
666 if (bank < 2)
667 return (sc->pmu);
668
669 return (sc->grf);
670 }
671
672 static int
rk3399_parse_bias(phandle_t node,int bank)673 rk3399_parse_bias(phandle_t node, int bank)
674 {
675 int pullup, pulldown;
676
677 if (OF_hasprop(node, "bias-disable"))
678 return (0);
679
680 switch (bank) {
681 case 0:
682 case 2:
683 pullup = 3;
684 pulldown = 1;
685 break;
686 case 1:
687 case 3:
688 case 4:
689 pullup = 1;
690 pulldown = 2;
691 break;
692 }
693
694 if (OF_hasprop(node, "bias-pull-up"))
695 return (pullup);
696 if (OF_hasprop(node, "bias-pull-down"))
697 return (pulldown);
698
699 return (-1);
700 }
701
702 static int
rk3399_resolv_bias_value(int bank,int bias)703 rk3399_resolv_bias_value(int bank, int bias)
704 {
705 int rv = 0;
706
707 switch (bank) {
708 case 0:
709 case 2:
710 if (bias == 3)
711 rv = GPIO_PIN_PULLUP;
712 else if (bias == 1)
713 rv = GPIO_PIN_PULLDOWN;
714 break;
715 case 1:
716 case 3:
717 case 4:
718 if (bias == 1)
719 rv = GPIO_PIN_PULLUP;
720 else if (bias == 2)
721 rv = GPIO_PIN_PULLDOWN;
722 break;
723 }
724
725 return (rv);
726 }
727
728 static int
rk3399_get_bias_value(int bank,int bias)729 rk3399_get_bias_value(int bank, int bias)
730 {
731 int rv = 0;
732
733 switch (bank) {
734 case 0:
735 case 2:
736 if (bias & GPIO_PIN_PULLUP)
737 rv = 3;
738 else if (bias & GPIO_PIN_PULLDOWN)
739 rv = 1;
740 break;
741 case 1:
742 case 3:
743 case 4:
744 if (bias & GPIO_PIN_PULLUP)
745 rv = 1;
746 else if (bias & GPIO_PIN_PULLDOWN)
747 rv = 2;
748 break;
749 }
750
751 return (rv);
752 }
753
754 struct rk_pinctrl_conf rk3399_conf = {
755 .iomux_conf = rk3399_iomux_bank,
756 .iomux_nbanks = nitems(rk3399_iomux_bank),
757 .pin_fixup = rk3399_pin_fixup,
758 .npin_fixup = nitems(rk3399_pin_fixup),
759 .pin_drive = rk3399_pin_drive,
760 .npin_drive = nitems(rk3399_pin_drive),
761 .gpio_bank = rk3399_gpio_bank,
762 .ngpio_bank = nitems(rk3399_gpio_bank),
763 .get_pd_offset = rk3399_get_pd_offset,
764 .get_syscon = rk3399_get_syscon,
765 .parse_bias = rk3399_parse_bias,
766 .resolv_bias_value = rk3399_resolv_bias_value,
767 .get_bias_value = rk3399_get_bias_value,
768 };
769
770 static struct ofw_compat_data compat_data[] = {
771 {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf},
772 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf},
773 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf},
774 {NULL, 0}
775 };
776
777 static int
rk_pinctrl_parse_drive(struct rk_pinctrl_softc * sc,phandle_t node,uint32_t bank,uint32_t subbank,uint32_t * drive,uint32_t * offset)778 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node,
779 uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset)
780 {
781 uint32_t value;
782 int i;
783
784 if (OF_getencprop(node, "drive-strength", &value,
785 sizeof(value)) != 0)
786 return (-1);
787
788 /* Map to the correct drive value */
789 for (i = 0; i < sc->conf->npin_drive; i++) {
790 if (sc->conf->pin_drive[i].bank != bank &&
791 sc->conf->pin_drive[i].subbank != subbank)
792 continue;
793 if (sc->conf->pin_drive[i].ma == value) {
794 *drive = sc->conf->pin_drive[i].value;
795 return (0);
796 }
797 }
798
799 return (-1);
800 }
801
802 static void
rk_pinctrl_get_fixup(struct rk_pinctrl_softc * sc,uint32_t bank,uint32_t pin,uint32_t * reg,uint32_t * mask,uint32_t * bit)803 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin,
804 uint32_t *reg, uint32_t *mask, uint32_t *bit)
805 {
806 int i;
807
808 for (i = 0; i < sc->conf->npin_fixup; i++)
809 if (sc->conf->pin_fixup[i].bank == bank &&
810 sc->conf->pin_fixup[i].pin == pin) {
811 *reg = sc->conf->pin_fixup[i].reg;
812 *mask = sc->conf->pin_fixup[i].mask;
813 *bit = sc->conf->pin_fixup[i].bit;
814
815 return;
816 }
817 }
818
819 static int
rk_pinctrl_handle_io(struct rk_pinctrl_softc * sc,phandle_t node,uint32_t bank,uint32_t pin)820 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank,
821 uint32_t pin)
822 {
823 bool have_cfg, have_direction, have_value;
824 uint32_t direction_value, pin_value;
825 struct rk_pinctrl_gpio *gpio;
826 int i, rv;
827
828 have_cfg = false;
829 have_direction = false;
830 have_value = false;
831
832 /* Get (subset of) GPIO pin properties. */
833 if (OF_hasprop(node, "output-disable")) {
834 have_cfg = true;
835 have_direction = true;
836 direction_value = GPIO_PIN_INPUT;
837 }
838
839 if (OF_hasprop(node, "output-enable")) {
840 have_cfg = true;
841 have_direction = true;
842 direction_value = GPIO_PIN_OUTPUT;
843 }
844
845 if (OF_hasprop(node, "output-low")) {
846 have_cfg = true;
847 have_direction = true;
848 direction_value = GPIO_PIN_OUTPUT;
849 have_value = true;
850 pin_value = 0;
851 }
852
853 if (OF_hasprop(node, "output-high")) {
854 have_cfg = true;
855 have_direction = true;
856 direction_value = GPIO_PIN_OUTPUT;
857 have_value = true;
858 pin_value = 1;
859 }
860
861 if (!have_cfg)
862 return (0);
863
864 /* Find gpio */
865 gpio = NULL;
866 for(i = 0; i < sc->conf->ngpio_bank; i++) {
867 if (bank == sc->conf->gpio_bank[i].bank) {
868 gpio = sc->conf->gpio_bank + i;
869 break;
870 }
871 }
872 if (gpio == NULL) {
873 device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank);
874 return (ENXIO);
875 }
876 if (gpio->gpio_dev == NULL) {
877 device_printf(sc->dev,
878 "No GPIO subdevice found for bank %d\n", bank);
879 return (ENXIO);
880 }
881
882 rv = 0;
883 if (have_value) {
884 rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value);
885 if (rv != 0) {
886 device_printf(sc->dev, "Cannot set GPIO value: %d\n",
887 rv);
888 return (rv);
889 }
890 }
891
892 if (have_direction) {
893 rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value);
894 if (rv != 0) {
895 device_printf(sc->dev,
896 "Cannot set GPIO direction: %d\n", rv);
897 return (rv);
898 }
899 }
900
901 return (0);
902 }
903
904 static void
rk_pinctrl_configure_pin(struct rk_pinctrl_softc * sc,uint32_t * pindata)905 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata)
906 {
907 phandle_t pin_conf;
908 struct syscon *syscon;
909 uint32_t bank, subbank, pin, function, bias;
910 uint32_t bit, mask, reg, drive;
911 int i, rv;
912
913 bank = pindata[0];
914 pin = pindata[1];
915 function = pindata[2];
916 pin_conf = OF_node_from_xref(pindata[3]);
917 subbank = pin / 8;
918
919 for (i = 0; i < sc->conf->iomux_nbanks; i++)
920 if (sc->conf->iomux_conf[i].bank == bank &&
921 sc->conf->iomux_conf[i].subbank == subbank)
922 break;
923
924 if (i == sc->conf->iomux_nbanks) {
925 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin,
926 bank);
927 return;
928 }
929
930 /* Find syscon */
931 syscon = sc->conf->get_syscon(sc, bank);
932
933 /* Setup GPIO properties first */
934 rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin);
935
936 /* Then pin pull-up/down */
937 bias = sc->conf->parse_bias(pin_conf, bank);
938 if (bias >= 0) {
939 reg = sc->conf->get_pd_offset(sc, bank);
940 reg += bank * 0x10 + ((pin / 8) * 0x4);
941 bit = (pin % 8) * 2;
942 mask = (0x3 << bit);
943 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16));
944 }
945
946 /* Then drive strength */
947 rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®);
948 if (rv == 0) {
949 bit = (pin % 8) * 2;
950 mask = (0x3 << bit);
951 SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16));
952 }
953
954 /* Finally set the pin function */
955 reg = sc->conf->iomux_conf[i].offset;
956 switch (sc->conf->iomux_conf[i].nbits) {
957 case 4:
958 if ((pin % 8) >= 4)
959 reg += 0x4;
960 bit = (pin % 4) * 4;
961 mask = (0xF << bit);
962 break;
963 case 3:
964 if ((pin % 8) >= 5)
965 reg += 4;
966 bit = (pin % 8 % 5) * 3;
967 mask = (0x7 << bit);
968 break;
969 case 2:
970 bit = (pin % 8) * 2;
971 mask = (0x3 << bit);
972 break;
973 default:
974 device_printf(sc->dev,
975 "Unknown pin stride width %d in bank %d\n",
976 sc->conf->iomux_conf[i].nbits, bank);
977 return;
978 }
979 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit);
980
981 /*
982 * NOTE: not all syscon registers uses hi-word write mask, thus
983 * register modify method should be used.
984 * XXXX We should not pass write mask to syscon register
985 * without hi-word write mask.
986 */
987 SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16));
988 }
989
990 static int
rk_pinctrl_configure_pins(device_t dev,phandle_t cfgxref)991 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref)
992 {
993 struct rk_pinctrl_softc *sc;
994 phandle_t node;
995 uint32_t *pins;
996 int i, npins;
997
998 sc = device_get_softc(dev);
999 node = OF_node_from_xref(cfgxref);
1000
1001 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins),
1002 (void **)&pins);
1003 if (npins <= 0)
1004 return (ENOENT);
1005
1006 for (i = 0; i != npins; i += 4)
1007 rk_pinctrl_configure_pin(sc, pins + i);
1008
1009 return (0);
1010 }
1011
1012 static int
rk_pinctrl_is_gpio_locked(struct rk_pinctrl_softc * sc,struct syscon * syscon,int bank,uint32_t pin,bool * is_gpio)1013 rk_pinctrl_is_gpio_locked(struct rk_pinctrl_softc *sc, struct syscon *syscon,
1014 int bank, uint32_t pin, bool *is_gpio)
1015 {
1016 uint32_t subbank, bit, mask, reg;
1017 uint32_t pinfunc;
1018 int i;
1019
1020 RK_PINCTRL_LOCK_ASSERT(sc);
1021
1022 subbank = pin / 8;
1023 *is_gpio = false;
1024
1025 for (i = 0; i < sc->conf->iomux_nbanks; i++)
1026 if (sc->conf->iomux_conf[i].bank == bank &&
1027 sc->conf->iomux_conf[i].subbank == subbank)
1028 break;
1029
1030 if (i == sc->conf->iomux_nbanks) {
1031 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin,
1032 bank);
1033 return (EINVAL);
1034 }
1035
1036 syscon = sc->conf->get_syscon(sc, bank);
1037
1038 /* Parse pin function */
1039 reg = sc->conf->iomux_conf[i].offset;
1040 switch (sc->conf->iomux_conf[i].nbits) {
1041 case 4:
1042 if ((pin % 8) >= 4)
1043 reg += 0x4;
1044 bit = (pin % 4) * 4;
1045 mask = (0xF << bit);
1046 break;
1047 case 3:
1048 if ((pin % 8) >= 5)
1049 reg += 4;
1050 bit = (pin % 8 % 5) * 3;
1051 mask = (0x7 << bit);
1052 break;
1053 case 2:
1054 bit = (pin % 8) * 2;
1055 mask = (0x3 << bit);
1056 break;
1057 default:
1058 device_printf(sc->dev,
1059 "Unknown pin stride width %d in bank %d\n",
1060 sc->conf->iomux_conf[i].nbits, bank);
1061 return (EINVAL);
1062 }
1063 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit);
1064
1065 reg = SYSCON_READ_4(syscon, reg);
1066 pinfunc = (reg & mask) >> bit;
1067
1068 /* Test if the pin is in gpio mode */
1069 if (pinfunc == 0)
1070 *is_gpio = true;
1071
1072 return (0);
1073 }
1074
1075 static int
rk_pinctrl_get_bank(struct rk_pinctrl_softc * sc,device_t gpio,int * bank)1076 rk_pinctrl_get_bank(struct rk_pinctrl_softc *sc, device_t gpio, int *bank)
1077 {
1078 int i;
1079
1080 for (i = 0; i < sc->conf->ngpio_bank; i++) {
1081 if (sc->conf->gpio_bank[i].gpio_dev == gpio)
1082 break;
1083 }
1084 if (i == sc->conf->ngpio_bank)
1085 return (EINVAL);
1086
1087 *bank = i;
1088 return (0);
1089 }
1090
1091 static int
rk_pinctrl_is_gpio(device_t pinctrl,device_t gpio,uint32_t pin,bool * is_gpio)1092 rk_pinctrl_is_gpio(device_t pinctrl, device_t gpio, uint32_t pin, bool *is_gpio)
1093 {
1094 struct rk_pinctrl_softc *sc;
1095 struct syscon *syscon;
1096 int bank;
1097 int rv;
1098
1099 sc = device_get_softc(pinctrl);
1100 RK_PINCTRL_LOCK(sc);
1101
1102 rv = rk_pinctrl_get_bank(sc, gpio, &bank);
1103 if (rv != 0)
1104 goto done;
1105 syscon = sc->conf->get_syscon(sc, bank);
1106 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, is_gpio);
1107
1108 done:
1109 RK_PINCTRL_UNLOCK(sc);
1110
1111 return (rv);
1112 }
1113
1114 static int
rk_pinctrl_get_flags(device_t pinctrl,device_t gpio,uint32_t pin,uint32_t * flags)1115 rk_pinctrl_get_flags(device_t pinctrl, device_t gpio, uint32_t pin,
1116 uint32_t *flags)
1117 {
1118 struct rk_pinctrl_softc *sc;
1119 struct syscon *syscon;
1120 uint32_t reg, mask, bit;
1121 uint32_t bias;
1122 int bank;
1123 int rv = 0;
1124 bool is_gpio;
1125
1126 sc = device_get_softc(pinctrl);
1127 RK_PINCTRL_LOCK(sc);
1128
1129 rv = rk_pinctrl_get_bank(sc, gpio, &bank);
1130 if (rv != 0)
1131 goto done;
1132 syscon = sc->conf->get_syscon(sc, bank);
1133 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio);
1134 if (rv != 0)
1135 goto done;
1136 if (!is_gpio) {
1137 rv = EINVAL;
1138 goto done;
1139 }
1140 /* Get the pullup/pulldown configuration */
1141 reg = sc->conf->get_pd_offset(sc, bank);
1142 reg += bank * 0x10 + ((pin / 8) * 0x4);
1143 bit = (pin % 8) * 2;
1144 mask = (0x3 << bit) << 16;
1145 reg = SYSCON_READ_4(syscon, reg);
1146 reg = (reg >> bit) & 0x3;
1147 bias = sc->conf->resolv_bias_value(bank, reg);
1148 *flags = bias;
1149
1150 done:
1151 RK_PINCTRL_UNLOCK(sc);
1152 return (rv);
1153 }
1154
1155 static int
rk_pinctrl_set_flags(device_t pinctrl,device_t gpio,uint32_t pin,uint32_t flags)1156 rk_pinctrl_set_flags(device_t pinctrl, device_t gpio, uint32_t pin,
1157 uint32_t flags)
1158 {
1159 struct rk_pinctrl_softc *sc;
1160 struct syscon *syscon;
1161 uint32_t bit, mask, reg;
1162 uint32_t bias;
1163 int bank;
1164 int rv = 0;
1165 bool is_gpio;
1166
1167 sc = device_get_softc(pinctrl);
1168 RK_PINCTRL_LOCK(sc);
1169
1170 rv = rk_pinctrl_get_bank(sc, gpio, &bank);
1171 if (rv != 0)
1172 goto done;
1173 syscon = sc->conf->get_syscon(sc, bank);
1174 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio);
1175 if (rv != 0)
1176 goto done;
1177 if (!is_gpio) {
1178 rv = EINVAL;
1179 goto done;
1180 }
1181 /* Get the pullup/pulldown configuration */
1182 reg = sc->conf->get_pd_offset(sc, bank);
1183 reg += bank * 0x10 + ((pin / 8) * 0x4);
1184 bit = (pin % 8) * 2;
1185 mask = (0x3 << bit);
1186 bias = sc->conf->get_bias_value(bank, flags);
1187 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16));
1188
1189 done:
1190 RK_PINCTRL_UNLOCK(sc);
1191 return (rv);
1192 }
1193
1194 static int
rk_pinctrl_register_gpio(struct rk_pinctrl_softc * sc,char * gpio_name,device_t gpio_dev)1195 rk_pinctrl_register_gpio(struct rk_pinctrl_softc *sc, char *gpio_name,
1196 device_t gpio_dev)
1197 {
1198 int i;
1199
1200 for(i = 0; i < sc->conf->ngpio_bank; i++) {
1201 if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0)
1202 continue;
1203 sc->conf->gpio_bank[i].gpio_dev = gpio_dev;
1204 return(0);
1205 }
1206 return (ENXIO);
1207 }
1208
1209 static int
rk_pinctrl_probe(device_t dev)1210 rk_pinctrl_probe(device_t dev)
1211 {
1212
1213 if (!ofw_bus_status_okay(dev))
1214 return (ENXIO);
1215
1216 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1217 return (ENXIO);
1218
1219 device_set_desc(dev, "RockChip Pinctrl controller");
1220 return (BUS_PROBE_DEFAULT);
1221 }
1222
1223 static int
rk_pinctrl_attach(device_t dev)1224 rk_pinctrl_attach(device_t dev)
1225 {
1226 struct rk_pinctrl_softc *sc;
1227 phandle_t node;
1228 device_t cdev;
1229 char *gpio_name, *eptr;
1230 int rv;
1231
1232 sc = device_get_softc(dev);
1233 sc->dev = dev;
1234
1235 node = ofw_bus_get_node(dev);
1236
1237 if (OF_hasprop(node, "rockchip,grf") &&
1238 syscon_get_by_ofw_property(dev, node,
1239 "rockchip,grf", &sc->grf) != 0) {
1240 device_printf(dev, "cannot get grf driver handle\n");
1241 return (ENXIO);
1242 }
1243
1244 /* RK3399,RK3288 has banks in PMU. RK3328 does not have a PMU. */
1245 if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") ||
1246 ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) {
1247 if (OF_hasprop(node, "rockchip,pmu") &&
1248 syscon_get_by_ofw_property(dev, node,
1249 "rockchip,pmu", &sc->pmu) != 0) {
1250 device_printf(dev, "cannot get pmu driver handle\n");
1251 return (ENXIO);
1252 }
1253 }
1254
1255 mtx_init(&sc->mtx, "rk pinctrl", "pinctrl", MTX_SPIN);
1256
1257 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev,
1258 compat_data)->ocd_data;
1259
1260 fdt_pinctrl_register(dev, "rockchip,pins");
1261
1262 simplebus_init(dev, node);
1263
1264 bus_generic_probe(dev);
1265
1266 /* Attach child devices */
1267 for (node = OF_child(node); node > 0; node = OF_peer(node)) {
1268 if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank"))
1269 continue;
1270
1271 rv = OF_getprop_alloc(node, "name", (void **)&gpio_name);
1272 if (rv <= 0) {
1273 device_printf(sc->dev, "Cannot GPIO subdevice name.\n");
1274 continue;
1275 }
1276
1277 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL);
1278 if (cdev == NULL) {
1279 device_printf(dev, " Cannot add GPIO subdevice: %s\n",
1280 gpio_name);
1281 OF_prop_free(gpio_name);
1282 continue;
1283 }
1284
1285 rv = device_probe_and_attach(cdev);
1286 if (rv != 0) {
1287 device_printf(sc->dev,
1288 "Cannot attach GPIO subdevice: %s\n", gpio_name);
1289 OF_prop_free(gpio_name);
1290 continue;
1291 }
1292
1293 /* Grep device name from name property */
1294 eptr = gpio_name;
1295 strsep(&eptr, "@");
1296 if (gpio_name == eptr) {
1297 device_printf(sc->dev,
1298 "Unrecognized format of GPIO subdevice name: %s\n",
1299 gpio_name);
1300 OF_prop_free(gpio_name);
1301 continue;
1302 }
1303 rv = rk_pinctrl_register_gpio(sc, gpio_name, cdev);
1304 if (rv != 0) {
1305 device_printf(sc->dev,
1306 "Cannot register GPIO subdevice %s: %d\n",
1307 gpio_name, rv);
1308 OF_prop_free(gpio_name);
1309 continue;
1310 }
1311 OF_prop_free(gpio_name);
1312 }
1313
1314 fdt_pinctrl_configure_tree(dev);
1315
1316 return (bus_generic_attach(dev));
1317 }
1318
1319 static int
rk_pinctrl_detach(device_t dev)1320 rk_pinctrl_detach(device_t dev)
1321 {
1322
1323 return (EBUSY);
1324 }
1325
1326 static device_method_t rk_pinctrl_methods[] = {
1327 /* Device interface */
1328 DEVMETHOD(device_probe, rk_pinctrl_probe),
1329 DEVMETHOD(device_attach, rk_pinctrl_attach),
1330 DEVMETHOD(device_detach, rk_pinctrl_detach),
1331
1332 /* fdt_pinctrl interface */
1333 DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins),
1334 DEVMETHOD(fdt_pinctrl_is_gpio, rk_pinctrl_is_gpio),
1335 DEVMETHOD(fdt_pinctrl_get_flags, rk_pinctrl_get_flags),
1336 DEVMETHOD(fdt_pinctrl_set_flags, rk_pinctrl_set_flags),
1337
1338 DEVMETHOD_END
1339 };
1340
1341 static devclass_t rk_pinctrl_devclass;
1342
1343 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods,
1344 sizeof(struct rk_pinctrl_softc), simplebus_driver);
1345
1346 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver,
1347 rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
1348 MODULE_VERSION(rk_pinctrl, 1);
1349