1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37
38 #include <dev/extres/clk/clk.h>
39
40 #include <arm64/rockchip/clk/rk_clk_armclk.h>
41
42 #include "clkdev_if.h"
43
44 struct rk_clk_armclk_sc {
45 uint32_t muxdiv_offset;
46 uint32_t mux_shift;
47 uint32_t mux_width;
48 uint32_t mux_mask;
49
50 uint32_t div_shift;
51 uint32_t div_width;
52 uint32_t div_mask;
53
54 uint32_t gate_offset;
55 uint32_t gate_shift;
56
57 uint32_t flags;
58
59 uint32_t main_parent;
60 uint32_t alt_parent;
61
62 struct rk_clk_armclk_rates *rates;
63 int nrates;
64 };
65
66 #define WRITE4(_clk, off, val) \
67 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
68 #define READ4(_clk, off, val) \
69 CLKDEV_READ_4(clknode_get_device(_clk), off, val)
70 #define DEVICE_LOCK(_clk) \
71 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
72 #define DEVICE_UNLOCK(_clk) \
73 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
74
75 #define RK_ARMCLK_WRITE_MASK_SHIFT 16
76
77 /* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */
78 #define dprintf(format, arg...)
79
80 static int
rk_clk_armclk_init(struct clknode * clk,device_t dev)81 rk_clk_armclk_init(struct clknode *clk, device_t dev)
82 {
83 struct rk_clk_armclk_sc *sc;
84 uint32_t val, idx;
85
86 sc = clknode_get_softc(clk);
87
88 idx = 0;
89 DEVICE_LOCK(clk);
90 READ4(clk, sc->muxdiv_offset, &val);
91 DEVICE_UNLOCK(clk);
92
93 idx = (val & sc->mux_mask) >> sc->mux_shift;
94
95 clknode_init_parent_idx(clk, idx);
96
97 return (0);
98 }
99
100 static int
rk_clk_armclk_set_mux(struct clknode * clk,int index)101 rk_clk_armclk_set_mux(struct clknode *clk, int index)
102 {
103 struct rk_clk_armclk_sc *sc;
104 uint32_t val = 0;
105
106 sc = clknode_get_softc(clk);
107
108 dprintf("Set mux to %d\n", index);
109 DEVICE_LOCK(clk);
110 val |= index << sc->mux_shift;
111 val |= sc->mux_mask << RK_ARMCLK_WRITE_MASK_SHIFT;
112 dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val);
113 WRITE4(clk, sc->muxdiv_offset, val);
114 DEVICE_UNLOCK(clk);
115
116 return (0);
117 }
118
119 static int
rk_clk_armclk_recalc(struct clknode * clk,uint64_t * freq)120 rk_clk_armclk_recalc(struct clknode *clk, uint64_t *freq)
121 {
122 struct rk_clk_armclk_sc *sc;
123 uint32_t reg, div;
124
125 sc = clknode_get_softc(clk);
126
127 DEVICE_LOCK(clk);
128
129 READ4(clk, sc->muxdiv_offset, ®);
130 dprintf("Read: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, reg);
131
132 DEVICE_UNLOCK(clk);
133
134 div = ((reg & sc->div_mask) >> sc->div_shift) + 1;
135 dprintf("parent_freq=%lu, div=%u\n", *freq, div);
136
137 *freq = *freq / div;
138
139 return (0);
140 }
141
142 static int
rk_clk_armclk_set_freq(struct clknode * clk,uint64_t fparent,uint64_t * fout,int flags,int * stop)143 rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
144 int flags, int *stop)
145 {
146 struct rk_clk_armclk_sc *sc;
147 struct clknode *p_main;
148 const char **p_names;
149 uint64_t best = 0, best_p = 0;
150 uint32_t div = 0, val = 0;
151 int err, i, rate = 0;
152
153 sc = clknode_get_softc(clk);
154
155 dprintf("Finding best parent/div for target freq of %lu\n", *fout);
156 p_names = clknode_get_parent_names(clk);
157 p_main = clknode_find_by_name(p_names[sc->main_parent]);
158
159 for (i = 0; i < sc->nrates; i++) {
160 if (sc->rates[i].freq == *fout) {
161 best = sc->rates[i].freq;
162 div = sc->rates[i].div;
163 best_p = best * div;
164 rate = i;
165 dprintf("Best parent %s (%d) with best freq at %lu\n",
166 clknode_get_name(p_main),
167 sc->main_parent,
168 best);
169 break;
170 }
171 }
172
173 if (rate == sc->nrates)
174 return (0);
175
176 if ((flags & CLK_SET_DRYRUN) != 0) {
177 *fout = best;
178 *stop = 1;
179 return (0);
180 }
181
182 dprintf("Changing parent (%s) freq to %lu\n", clknode_get_name(p_main), best_p);
183 err = clknode_set_freq(p_main, best_p, 0, 1);
184 if (err != 0)
185 printf("Cannot set %s to %lu\n",
186 clknode_get_name(p_main),
187 best_p);
188
189 clknode_set_parent_by_idx(clk, sc->main_parent);
190
191 clknode_get_freq(p_main, &best_p);
192 dprintf("main parent freq at %lu\n", best_p);
193 DEVICE_LOCK(clk);
194 val |= (div - 1) << sc->div_shift;
195 val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT;
196 dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val);
197 WRITE4(clk, sc->muxdiv_offset, val);
198 DEVICE_UNLOCK(clk);
199
200 *fout = best;
201 *stop = 1;
202
203 return (0);
204 }
205
206 static clknode_method_t rk_clk_armclk_clknode_methods[] = {
207 /* Device interface */
208 CLKNODEMETHOD(clknode_init, rk_clk_armclk_init),
209 CLKNODEMETHOD(clknode_set_mux, rk_clk_armclk_set_mux),
210 CLKNODEMETHOD(clknode_recalc_freq, rk_clk_armclk_recalc),
211 CLKNODEMETHOD(clknode_set_freq, rk_clk_armclk_set_freq),
212 CLKNODEMETHOD_END
213 };
214
215 DEFINE_CLASS_1(rk_clk_armclk_clknode, rk_clk_armclk_clknode_class,
216 rk_clk_armclk_clknode_methods, sizeof(struct rk_clk_armclk_sc),
217 clknode_class);
218
219 int
rk_clk_armclk_register(struct clkdom * clkdom,struct rk_clk_armclk_def * clkdef)220 rk_clk_armclk_register(struct clkdom *clkdom, struct rk_clk_armclk_def *clkdef)
221 {
222 struct clknode *clk;
223 struct rk_clk_armclk_sc *sc;
224
225 clk = clknode_create(clkdom, &rk_clk_armclk_clknode_class,
226 &clkdef->clkdef);
227 if (clk == NULL)
228 return (1);
229
230 sc = clknode_get_softc(clk);
231
232 sc->muxdiv_offset = clkdef->muxdiv_offset;
233
234 sc->mux_shift = clkdef->mux_shift;
235 sc->mux_width = clkdef->mux_width;
236 sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift;
237
238 sc->div_shift = clkdef->div_shift;
239 sc->div_width = clkdef->div_width;
240 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift;
241
242 sc->flags = clkdef->flags;
243
244 sc->main_parent = clkdef->main_parent;
245 sc->alt_parent = clkdef->alt_parent;
246
247 sc->rates = clkdef->rates;
248 sc->nrates = clkdef->nrates;
249
250 clknode_register(clkdom, clk);
251
252 return (0);
253 }
254