1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
55
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
64
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
68
69 #ifdef __i386__
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
73
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
76 #endif
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
85
86 #ifdef __i386__
87 int cpu; /* Are we 386, 386sx, 486, etc? */
88 int cpu_class;
89 #endif
90 u_int cpu_feature; /* Feature flags */
91 u_int cpu_feature2; /* Feature flags */
92 u_int amd_feature; /* AMD feature flags */
93 u_int amd_feature2; /* AMD feature flags */
94 u_int amd_rascap; /* AMD RAS capabilities */
95 u_int amd_pminfo; /* AMD advanced power management info */
96 u_int amd_extended_feature_extensions;
97 u_int via_feature_rng; /* VIA RNG features */
98 u_int via_feature_xcrypt; /* VIA ACE features */
99 u_int cpu_high; /* Highest arg to CPUID */
100 u_int cpu_exthigh; /* Highest arg to extended CPUID */
101 u_int cpu_id; /* Stepping ID */
102 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
103 u_int cpu_procinfo2; /* Multicore info */
104 char cpu_vendor[20]; /* CPU Origin code */
105 u_int cpu_vendor_id; /* CPU vendor ID */
106 u_int cpu_fxsr; /* SSE enabled */
107 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
108 u_int cpu_clflush_line_size = 32;
109 u_int cpu_stdext_feature; /* %ebx */
110 u_int cpu_stdext_feature2; /* %ecx */
111 u_int cpu_stdext_feature3; /* %edx */
112 uint64_t cpu_ia32_arch_caps;
113 u_int cpu_max_ext_state_size;
114 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
115 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
116 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
117 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
118 char machine[] = MACHINE;
119
120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
121 &via_feature_rng, 0,
122 "VIA RNG feature available in CPU");
123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
124 &via_feature_xcrypt, 0,
125 "VIA xcrypt feature available in CPU");
126
127 #ifdef __amd64__
128 #ifdef SCTL_MASK32
129 extern int adaptive_machine_arch;
130 #endif
131
132 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
134 {
135 #ifdef SCTL_MASK32
136 static const char machine32[] = "i386";
137 #endif
138 int error;
139
140 #ifdef SCTL_MASK32
141 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
142 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
143 else
144 #endif
145 error = SYSCTL_OUT(req, machine, sizeof(machine));
146 return (error);
147
148 }
149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
150 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
151 #else
152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
153 machine, 0, "Machine class");
154 #endif
155
156 static char cpu_model[128];
157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
158 cpu_model, 0, "Machine model");
159
160 static int hw_clockrate;
161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
162 &hw_clockrate, 0, "CPU instruction clock rate");
163
164 u_int hv_high;
165 char hv_vendor[16];
166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
167 0, "Hypervisor vendor");
168
169 static eventhandler_tag tsc_post_tag;
170
171 static char cpu_brand[48];
172
173 #ifdef __i386__
174 #define MAX_BRAND_INDEX 8
175
176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
177 NULL, /* No brand */
178 "Intel Celeron",
179 "Intel Pentium III",
180 "Intel Pentium III Xeon",
181 NULL,
182 NULL,
183 NULL,
184 NULL,
185 "Intel Pentium 4"
186 };
187
188 static struct {
189 char *cpu_name;
190 int cpu_class;
191 } cpus[] = {
192 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
193 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
194 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
195 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
196 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
197 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
198 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
199 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
200 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
201 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
202 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
203 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
204 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
205 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
206 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
207 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
208 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
209 };
210 #endif
211
212 static struct {
213 char *vendor;
214 u_int vendor_id;
215 } cpu_vendors[] = {
216 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
217 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
218 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
219 #ifdef __i386__
220 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
221 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
222 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
223 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
224 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
225 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
226 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
227 #if 0
228 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
229 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
230 #endif
231 #endif
232 };
233
234 void
printcpuinfo(void)235 printcpuinfo(void)
236 {
237 u_int regs[4], i;
238 char *brand;
239
240 printf("CPU: ");
241 #ifdef __i386__
242 cpu_class = cpus[cpu].cpu_class;
243 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
244 #else
245 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
246 #endif
247
248 /* Check for extended CPUID information and a processor name. */
249 if (cpu_exthigh >= 0x80000004) {
250 brand = cpu_brand;
251 for (i = 0x80000002; i < 0x80000005; i++) {
252 do_cpuid(i, regs);
253 memcpy(brand, regs, sizeof(regs));
254 brand += sizeof(regs);
255 }
256 }
257
258 switch (cpu_vendor_id) {
259 case CPU_VENDOR_INTEL:
260 #ifdef __i386__
261 if ((cpu_id & 0xf00) > 0x300) {
262 u_int brand_index;
263
264 cpu_model[0] = '\0';
265
266 switch (cpu_id & 0x3000) {
267 case 0x1000:
268 strcpy(cpu_model, "Overdrive ");
269 break;
270 case 0x2000:
271 strcpy(cpu_model, "Dual ");
272 break;
273 }
274
275 switch (cpu_id & 0xf00) {
276 case 0x400:
277 strcat(cpu_model, "i486 ");
278 /* Check the particular flavor of 486 */
279 switch (cpu_id & 0xf0) {
280 case 0x00:
281 case 0x10:
282 strcat(cpu_model, "DX");
283 break;
284 case 0x20:
285 strcat(cpu_model, "SX");
286 break;
287 case 0x30:
288 strcat(cpu_model, "DX2");
289 break;
290 case 0x40:
291 strcat(cpu_model, "SL");
292 break;
293 case 0x50:
294 strcat(cpu_model, "SX2");
295 break;
296 case 0x70:
297 strcat(cpu_model,
298 "DX2 Write-Back Enhanced");
299 break;
300 case 0x80:
301 strcat(cpu_model, "DX4");
302 break;
303 }
304 break;
305 case 0x500:
306 /* Check the particular flavor of 586 */
307 strcat(cpu_model, "Pentium");
308 switch (cpu_id & 0xf0) {
309 case 0x00:
310 strcat(cpu_model, " A-step");
311 break;
312 case 0x10:
313 strcat(cpu_model, "/P5");
314 break;
315 case 0x20:
316 strcat(cpu_model, "/P54C");
317 break;
318 case 0x30:
319 strcat(cpu_model, "/P24T");
320 break;
321 case 0x40:
322 strcat(cpu_model, "/P55C");
323 break;
324 case 0x70:
325 strcat(cpu_model, "/P54C");
326 break;
327 case 0x80:
328 strcat(cpu_model, "/P55C (quarter-micron)");
329 break;
330 default:
331 /* nothing */
332 break;
333 }
334 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
335 /*
336 * XXX - If/when Intel fixes the bug, this
337 * should also check the version of the
338 * CPU, not just that it's a Pentium.
339 */
340 has_f00f_bug = 1;
341 #endif
342 break;
343 case 0x600:
344 /* Check the particular flavor of 686 */
345 switch (cpu_id & 0xf0) {
346 case 0x00:
347 strcat(cpu_model, "Pentium Pro A-step");
348 break;
349 case 0x10:
350 strcat(cpu_model, "Pentium Pro");
351 break;
352 case 0x30:
353 case 0x50:
354 case 0x60:
355 strcat(cpu_model,
356 "Pentium II/Pentium II Xeon/Celeron");
357 cpu = CPU_PII;
358 break;
359 case 0x70:
360 case 0x80:
361 case 0xa0:
362 case 0xb0:
363 strcat(cpu_model,
364 "Pentium III/Pentium III Xeon/Celeron");
365 cpu = CPU_PIII;
366 break;
367 default:
368 strcat(cpu_model, "Unknown 80686");
369 break;
370 }
371 break;
372 case 0xf00:
373 strcat(cpu_model, "Pentium 4");
374 cpu = CPU_P4;
375 break;
376 default:
377 strcat(cpu_model, "unknown");
378 break;
379 }
380
381 /*
382 * If we didn't get a brand name from the extended
383 * CPUID, try to look it up in the brand table.
384 */
385 if (cpu_high > 0 && *cpu_brand == '\0') {
386 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
387 if (brand_index <= MAX_BRAND_INDEX &&
388 cpu_brandtable[brand_index] != NULL)
389 strcpy(cpu_brand,
390 cpu_brandtable[brand_index]);
391 }
392 }
393 #else
394 /* Please make up your mind folks! */
395 strcat(cpu_model, "EM64T");
396 #endif
397 break;
398 case CPU_VENDOR_AMD:
399 /*
400 * Values taken from AMD Processor Recognition
401 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
402 * (also describes ``Features'' encodings.
403 */
404 strcpy(cpu_model, "AMD ");
405 #ifdef __i386__
406 switch (cpu_id & 0xFF0) {
407 case 0x410:
408 strcat(cpu_model, "Standard Am486DX");
409 break;
410 case 0x430:
411 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
412 break;
413 case 0x470:
414 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
415 break;
416 case 0x480:
417 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
418 break;
419 case 0x490:
420 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
421 break;
422 case 0x4E0:
423 strcat(cpu_model, "Am5x86 Write-Through");
424 break;
425 case 0x4F0:
426 strcat(cpu_model, "Am5x86 Write-Back");
427 break;
428 case 0x500:
429 strcat(cpu_model, "K5 model 0");
430 break;
431 case 0x510:
432 strcat(cpu_model, "K5 model 1");
433 break;
434 case 0x520:
435 strcat(cpu_model, "K5 PR166 (model 2)");
436 break;
437 case 0x530:
438 strcat(cpu_model, "K5 PR200 (model 3)");
439 break;
440 case 0x560:
441 strcat(cpu_model, "K6");
442 break;
443 case 0x570:
444 strcat(cpu_model, "K6 266 (model 1)");
445 break;
446 case 0x580:
447 strcat(cpu_model, "K6-2");
448 break;
449 case 0x590:
450 strcat(cpu_model, "K6-III");
451 break;
452 case 0x5a0:
453 strcat(cpu_model, "Geode LX");
454 break;
455 default:
456 strcat(cpu_model, "Unknown");
457 break;
458 }
459 #else
460 if ((cpu_id & 0xf00) == 0xf00)
461 strcat(cpu_model, "AMD64 Processor");
462 else
463 strcat(cpu_model, "Unknown");
464 #endif
465 break;
466 #ifdef __i386__
467 case CPU_VENDOR_CYRIX:
468 strcpy(cpu_model, "Cyrix ");
469 switch (cpu_id & 0xff0) {
470 case 0x440:
471 strcat(cpu_model, "MediaGX");
472 break;
473 case 0x520:
474 strcat(cpu_model, "6x86");
475 break;
476 case 0x540:
477 cpu_class = CPUCLASS_586;
478 strcat(cpu_model, "GXm");
479 break;
480 case 0x600:
481 strcat(cpu_model, "6x86MX");
482 break;
483 default:
484 /*
485 * Even though CPU supports the cpuid
486 * instruction, it can be disabled.
487 * Therefore, this routine supports all Cyrix
488 * CPUs.
489 */
490 switch (cyrix_did & 0xf0) {
491 case 0x00:
492 switch (cyrix_did & 0x0f) {
493 case 0x00:
494 strcat(cpu_model, "486SLC");
495 break;
496 case 0x01:
497 strcat(cpu_model, "486DLC");
498 break;
499 case 0x02:
500 strcat(cpu_model, "486SLC2");
501 break;
502 case 0x03:
503 strcat(cpu_model, "486DLC2");
504 break;
505 case 0x04:
506 strcat(cpu_model, "486SRx");
507 break;
508 case 0x05:
509 strcat(cpu_model, "486DRx");
510 break;
511 case 0x06:
512 strcat(cpu_model, "486SRx2");
513 break;
514 case 0x07:
515 strcat(cpu_model, "486DRx2");
516 break;
517 case 0x08:
518 strcat(cpu_model, "486SRu");
519 break;
520 case 0x09:
521 strcat(cpu_model, "486DRu");
522 break;
523 case 0x0a:
524 strcat(cpu_model, "486SRu2");
525 break;
526 case 0x0b:
527 strcat(cpu_model, "486DRu2");
528 break;
529 default:
530 strcat(cpu_model, "Unknown");
531 break;
532 }
533 break;
534 case 0x10:
535 switch (cyrix_did & 0x0f) {
536 case 0x00:
537 strcat(cpu_model, "486S");
538 break;
539 case 0x01:
540 strcat(cpu_model, "486S2");
541 break;
542 case 0x02:
543 strcat(cpu_model, "486Se");
544 break;
545 case 0x03:
546 strcat(cpu_model, "486S2e");
547 break;
548 case 0x0a:
549 strcat(cpu_model, "486DX");
550 break;
551 case 0x0b:
552 strcat(cpu_model, "486DX2");
553 break;
554 case 0x0f:
555 strcat(cpu_model, "486DX4");
556 break;
557 default:
558 strcat(cpu_model, "Unknown");
559 break;
560 }
561 break;
562 case 0x20:
563 if ((cyrix_did & 0x0f) < 8)
564 strcat(cpu_model, "6x86"); /* Where did you get it? */
565 else
566 strcat(cpu_model, "5x86");
567 break;
568 case 0x30:
569 strcat(cpu_model, "6x86");
570 break;
571 case 0x40:
572 if ((cyrix_did & 0xf000) == 0x3000) {
573 cpu_class = CPUCLASS_586;
574 strcat(cpu_model, "GXm");
575 } else
576 strcat(cpu_model, "MediaGX");
577 break;
578 case 0x50:
579 strcat(cpu_model, "6x86MX");
580 break;
581 case 0xf0:
582 switch (cyrix_did & 0x0f) {
583 case 0x0d:
584 strcat(cpu_model, "Overdrive CPU");
585 break;
586 case 0x0e:
587 strcpy(cpu_model, "Texas Instruments 486SXL");
588 break;
589 case 0x0f:
590 strcat(cpu_model, "486SLC/DLC");
591 break;
592 default:
593 strcat(cpu_model, "Unknown");
594 break;
595 }
596 break;
597 default:
598 strcat(cpu_model, "Unknown");
599 break;
600 }
601 break;
602 }
603 break;
604 case CPU_VENDOR_RISE:
605 strcpy(cpu_model, "Rise ");
606 switch (cpu_id & 0xff0) {
607 case 0x500: /* 6401 and 6441 (Kirin) */
608 case 0x520: /* 6510 (Lynx) */
609 strcat(cpu_model, "mP6");
610 break;
611 default:
612 strcat(cpu_model, "Unknown");
613 }
614 break;
615 #endif
616 case CPU_VENDOR_CENTAUR:
617 #ifdef __i386__
618 switch (cpu_id & 0xff0) {
619 case 0x540:
620 strcpy(cpu_model, "IDT WinChip C6");
621 break;
622 case 0x580:
623 strcpy(cpu_model, "IDT WinChip 2");
624 break;
625 case 0x590:
626 strcpy(cpu_model, "IDT WinChip 3");
627 break;
628 case 0x660:
629 strcpy(cpu_model, "VIA C3 Samuel");
630 break;
631 case 0x670:
632 if (cpu_id & 0x8)
633 strcpy(cpu_model, "VIA C3 Ezra");
634 else
635 strcpy(cpu_model, "VIA C3 Samuel 2");
636 break;
637 case 0x680:
638 strcpy(cpu_model, "VIA C3 Ezra-T");
639 break;
640 case 0x690:
641 strcpy(cpu_model, "VIA C3 Nehemiah");
642 break;
643 case 0x6a0:
644 case 0x6d0:
645 strcpy(cpu_model, "VIA C7 Esther");
646 break;
647 case 0x6f0:
648 strcpy(cpu_model, "VIA Nano");
649 break;
650 default:
651 strcpy(cpu_model, "VIA/IDT Unknown");
652 }
653 #else
654 strcpy(cpu_model, "VIA ");
655 if ((cpu_id & 0xff0) == 0x6f0)
656 strcat(cpu_model, "Nano Processor");
657 else
658 strcat(cpu_model, "Unknown");
659 #endif
660 break;
661 #ifdef __i386__
662 case CPU_VENDOR_IBM:
663 strcpy(cpu_model, "Blue Lightning CPU");
664 break;
665 case CPU_VENDOR_NSC:
666 switch (cpu_id & 0xff0) {
667 case 0x540:
668 strcpy(cpu_model, "Geode SC1100");
669 cpu = CPU_GEODE1100;
670 break;
671 default:
672 strcpy(cpu_model, "Geode/NSC unknown");
673 break;
674 }
675 break;
676 #endif
677 default:
678 strcat(cpu_model, "Unknown");
679 break;
680 }
681
682 /*
683 * Replace cpu_model with cpu_brand minus leading spaces if
684 * we have one.
685 */
686 brand = cpu_brand;
687 while (*brand == ' ')
688 ++brand;
689 if (*brand != '\0')
690 strcpy(cpu_model, brand);
691
692 printf("%s (", cpu_model);
693 if (tsc_freq != 0) {
694 hw_clockrate = (tsc_freq + 5000) / 1000000;
695 printf("%jd.%02d-MHz ",
696 (intmax_t)(tsc_freq + 4999) / 1000000,
697 (u_int)((tsc_freq + 4999) / 10000) % 100);
698 }
699 #ifdef __i386__
700 switch(cpu_class) {
701 case CPUCLASS_286:
702 printf("286");
703 break;
704 case CPUCLASS_386:
705 printf("386");
706 break;
707 #if defined(I486_CPU)
708 case CPUCLASS_486:
709 printf("486");
710 break;
711 #endif
712 #if defined(I586_CPU)
713 case CPUCLASS_586:
714 printf("586");
715 break;
716 #endif
717 #if defined(I686_CPU)
718 case CPUCLASS_686:
719 printf("686");
720 break;
721 #endif
722 default:
723 printf("Unknown"); /* will panic below... */
724 }
725 #else
726 printf("K8");
727 #endif
728 printf("-class CPU)\n");
729 if (*cpu_vendor)
730 printf(" Origin=\"%s\"", cpu_vendor);
731 if (cpu_id)
732 printf(" Id=0x%x", cpu_id);
733
734 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
735 cpu_vendor_id == CPU_VENDOR_AMD ||
736 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
737 #ifdef __i386__
738 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
739 cpu_vendor_id == CPU_VENDOR_RISE ||
740 cpu_vendor_id == CPU_VENDOR_NSC ||
741 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
742 #endif
743 0) {
744 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
745 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
746 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
747 #ifdef __i386__
748 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
749 printf("\n DIR=0x%04x", cyrix_did);
750 #endif
751
752 /*
753 * AMD CPUID Specification
754 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
755 *
756 * Intel Processor Identification and CPUID Instruction
757 * http://www.intel.com/assets/pdf/appnote/241618.pdf
758 */
759 if (cpu_high > 0) {
760
761 /*
762 * Here we should probably set up flags indicating
763 * whether or not various features are available.
764 * The interesting ones are probably VME, PSE, PAE,
765 * and PGE. The code already assumes without bothering
766 * to check that all CPUs >= Pentium have a TSC and
767 * MSRs.
768 */
769 printf("\n Features=0x%b", cpu_feature,
770 "\020"
771 "\001FPU" /* Integral FPU */
772 "\002VME" /* Extended VM86 mode support */
773 "\003DE" /* Debugging Extensions (CR4.DE) */
774 "\004PSE" /* 4MByte page tables */
775 "\005TSC" /* Timestamp counter */
776 "\006MSR" /* Machine specific registers */
777 "\007PAE" /* Physical address extension */
778 "\010MCE" /* Machine Check support */
779 "\011CX8" /* CMPEXCH8 instruction */
780 "\012APIC" /* SMP local APIC */
781 "\013oldMTRR" /* Previous implementation of MTRR */
782 "\014SEP" /* Fast System Call */
783 "\015MTRR" /* Memory Type Range Registers */
784 "\016PGE" /* PG_G (global bit) support */
785 "\017MCA" /* Machine Check Architecture */
786 "\020CMOV" /* CMOV instruction */
787 "\021PAT" /* Page attributes table */
788 "\022PSE36" /* 36 bit address space support */
789 "\023PN" /* Processor Serial number */
790 "\024CLFLUSH" /* Has the CLFLUSH instruction */
791 "\025<b20>"
792 "\026DTS" /* Debug Trace Store */
793 "\027ACPI" /* ACPI support */
794 "\030MMX" /* MMX instructions */
795 "\031FXSR" /* FXSAVE/FXRSTOR */
796 "\032SSE" /* Streaming SIMD Extensions */
797 "\033SSE2" /* Streaming SIMD Extensions #2 */
798 "\034SS" /* Self snoop */
799 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
800 "\036TM" /* Thermal Monitor clock slowdown */
801 "\037IA64" /* CPU can execute IA64 instructions */
802 "\040PBE" /* Pending Break Enable */
803 );
804
805 if (cpu_feature2 != 0) {
806 printf("\n Features2=0x%b", cpu_feature2,
807 "\020"
808 "\001SSE3" /* SSE3 */
809 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
810 "\003DTES64" /* 64-bit Debug Trace */
811 "\004MON" /* MONITOR/MWAIT Instructions */
812 "\005DS_CPL" /* CPL Qualified Debug Store */
813 "\006VMX" /* Virtual Machine Extensions */
814 "\007SMX" /* Safer Mode Extensions */
815 "\010EST" /* Enhanced SpeedStep */
816 "\011TM2" /* Thermal Monitor 2 */
817 "\012SSSE3" /* SSSE3 */
818 "\013CNXT-ID" /* L1 context ID available */
819 "\014SDBG" /* IA32 silicon debug */
820 "\015FMA" /* Fused Multiply Add */
821 "\016CX16" /* CMPXCHG16B Instruction */
822 "\017xTPR" /* Send Task Priority Messages*/
823 "\020PDCM" /* Perf/Debug Capability MSR */
824 "\021<b16>"
825 "\022PCID" /* Process-context Identifiers*/
826 "\023DCA" /* Direct Cache Access */
827 "\024SSE4.1" /* SSE 4.1 */
828 "\025SSE4.2" /* SSE 4.2 */
829 "\026x2APIC" /* xAPIC Extensions */
830 "\027MOVBE" /* MOVBE Instruction */
831 "\030POPCNT" /* POPCNT Instruction */
832 "\031TSCDLT" /* TSC-Deadline Timer */
833 "\032AESNI" /* AES Crypto */
834 "\033XSAVE" /* XSAVE/XRSTOR States */
835 "\034OSXSAVE" /* OS-Enabled State Management*/
836 "\035AVX" /* Advanced Vector Extensions */
837 "\036F16C" /* Half-precision conversions */
838 "\037RDRAND" /* RDRAND Instruction */
839 "\040HV" /* Hypervisor */
840 );
841 }
842
843 if (amd_feature != 0) {
844 printf("\n AMD Features=0x%b", amd_feature,
845 "\020" /* in hex */
846 "\001<s0>" /* Same */
847 "\002<s1>" /* Same */
848 "\003<s2>" /* Same */
849 "\004<s3>" /* Same */
850 "\005<s4>" /* Same */
851 "\006<s5>" /* Same */
852 "\007<s6>" /* Same */
853 "\010<s7>" /* Same */
854 "\011<s8>" /* Same */
855 "\012<s9>" /* Same */
856 "\013<b10>" /* Undefined */
857 "\014SYSCALL" /* Have SYSCALL/SYSRET */
858 "\015<s12>" /* Same */
859 "\016<s13>" /* Same */
860 "\017<s14>" /* Same */
861 "\020<s15>" /* Same */
862 "\021<s16>" /* Same */
863 "\022<s17>" /* Same */
864 "\023<b18>" /* Reserved, unknown */
865 "\024MP" /* Multiprocessor Capable */
866 "\025NX" /* Has EFER.NXE, NX */
867 "\026<b21>" /* Undefined */
868 "\027MMX+" /* AMD MMX Extensions */
869 "\030<s23>" /* Same */
870 "\031<s24>" /* Same */
871 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
872 "\033Page1GB" /* 1-GB large page support */
873 "\034RDTSCP" /* RDTSCP */
874 "\035<b28>" /* Undefined */
875 "\036LM" /* 64 bit long mode */
876 "\0373DNow!+" /* AMD 3DNow! Extensions */
877 "\0403DNow!" /* AMD 3DNow! */
878 );
879 }
880
881 if (amd_feature2 != 0) {
882 printf("\n AMD Features2=0x%b", amd_feature2,
883 "\020"
884 "\001LAHF" /* LAHF/SAHF in long mode */
885 "\002CMP" /* CMP legacy */
886 "\003SVM" /* Secure Virtual Mode */
887 "\004ExtAPIC" /* Extended APIC register */
888 "\005CR8" /* CR8 in legacy mode */
889 "\006ABM" /* LZCNT instruction */
890 "\007SSE4A" /* SSE4A */
891 "\010MAS" /* Misaligned SSE mode */
892 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
893 "\012OSVW" /* OS visible workaround */
894 "\013IBS" /* Instruction based sampling */
895 "\014XOP" /* XOP extended instructions */
896 "\015SKINIT" /* SKINIT/STGI */
897 "\016WDT" /* Watchdog timer */
898 "\017<b14>"
899 "\020LWP" /* Lightweight Profiling */
900 "\021FMA4" /* 4-operand FMA instructions */
901 "\022TCE" /* Translation Cache Extension */
902 "\023<b18>"
903 "\024NodeId" /* NodeId MSR support */
904 "\025<b20>"
905 "\026TBM" /* Trailing Bit Manipulation */
906 "\027Topology" /* Topology Extensions */
907 "\030PCXC" /* Core perf count */
908 "\031PNXC" /* NB perf count */
909 "\032<b25>"
910 "\033DBE" /* Data Breakpoint extension */
911 "\034PTSC" /* Performance TSC */
912 "\035PL2I" /* L2I perf count */
913 "\036MWAITX" /* MONITORX/MWAITX instructions */
914 "\037<b30>"
915 "\040<b31>"
916 );
917 }
918
919 if (cpu_stdext_feature != 0) {
920 printf("\n Structured Extended Features=0x%b",
921 cpu_stdext_feature,
922 "\020"
923 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
924 "\001FSGSBASE"
925 "\002TSCADJ"
926 "\003SGX"
927 /* Bit Manipulation Instructions */
928 "\004BMI1"
929 /* Hardware Lock Elision */
930 "\005HLE"
931 /* Advanced Vector Instructions 2 */
932 "\006AVX2"
933 /* FDP_EXCPTN_ONLY */
934 "\007FDPEXC"
935 /* Supervisor Mode Execution Prot. */
936 "\010SMEP"
937 /* Bit Manipulation Instructions */
938 "\011BMI2"
939 "\012ERMS"
940 /* Invalidate Processor Context ID */
941 "\013INVPCID"
942 /* Restricted Transactional Memory */
943 "\014RTM"
944 "\015PQM"
945 "\016NFPUSG"
946 /* Intel Memory Protection Extensions */
947 "\017MPX"
948 "\020PQE"
949 /* AVX512 Foundation */
950 "\021AVX512F"
951 "\022AVX512DQ"
952 /* Enhanced NRBG */
953 "\023RDSEED"
954 /* ADCX + ADOX */
955 "\024ADX"
956 /* Supervisor Mode Access Prevention */
957 "\025SMAP"
958 "\026AVX512IFMA"
959 "\027PCOMMIT"
960 "\030CLFLUSHOPT"
961 "\031CLWB"
962 "\032PROCTRACE"
963 "\033AVX512PF"
964 "\034AVX512ER"
965 "\035AVX512CD"
966 "\036SHA"
967 "\037AVX512BW"
968 "\040AVX512VL"
969 );
970 }
971
972 if (cpu_stdext_feature2 != 0) {
973 printf("\n Structured Extended Features2=0x%b",
974 cpu_stdext_feature2,
975 "\020"
976 "\001PREFETCHWT1"
977 "\002AVX512VBMI"
978 "\003UMIP"
979 "\004PKU"
980 "\005OSPKE"
981 "\006WAITPKG"
982 "\011GFNI"
983 "\027RDPID"
984 "\032CLDEMOTE"
985 "\034MOVDIRI"
986 "\035MOVDIRI64B"
987 "\037SGXLC"
988 );
989 }
990
991 if (cpu_stdext_feature3 != 0) {
992 printf("\n Structured Extended Features3=0x%b",
993 cpu_stdext_feature3,
994 "\020"
995 "\013MD_CLEAR"
996 "\016TSXFA"
997 "\033IBPB"
998 "\034STIBP"
999 "\035L1DFL"
1000 "\036ARCH_CAP"
1001 "\037CORE_CAP"
1002 "\040SSBD"
1003 );
1004 }
1005
1006 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1007 cpuid_count(0xd, 0x1, regs);
1008 if (regs[0] != 0) {
1009 printf("\n XSAVE Features=0x%b",
1010 regs[0],
1011 "\020"
1012 "\001XSAVEOPT"
1013 "\002XSAVEC"
1014 "\003XINUSE"
1015 "\004XSAVES");
1016 }
1017 }
1018
1019 if (cpu_ia32_arch_caps != 0) {
1020 printf("\n IA32_ARCH_CAPS=0x%b",
1021 (u_int)cpu_ia32_arch_caps,
1022 "\020"
1023 "\001RDCL_NO"
1024 "\002IBRS_ALL"
1025 "\003RSBA"
1026 "\004SKIP_L1DFL_VME"
1027 "\005SSB_NO"
1028 );
1029 }
1030
1031 if (amd_extended_feature_extensions != 0) {
1032 printf("\n "
1033 "AMD Extended Feature Extensions ID EBX="
1034 "0x%b", amd_extended_feature_extensions,
1035 "\020"
1036 "\001CLZERO"
1037 "\002IRPerf"
1038 "\003XSaveErPtr");
1039 }
1040
1041 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1042 print_via_padlock_info();
1043
1044 if (cpu_feature2 & CPUID2_VMX)
1045 print_vmx_info();
1046
1047 if (amd_feature2 & AMDID2_SVM)
1048 print_svm_info();
1049
1050 if ((cpu_feature & CPUID_HTT) &&
1051 cpu_vendor_id == CPU_VENDOR_AMD)
1052 cpu_feature &= ~CPUID_HTT;
1053
1054 /*
1055 * If this CPU supports P-state invariant TSC then
1056 * mention the capability.
1057 */
1058 if (tsc_is_invariant) {
1059 printf("\n TSC: P-state invariant");
1060 if (tsc_perf_stat)
1061 printf(", performance statistics");
1062 }
1063 }
1064 #ifdef __i386__
1065 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1066 printf(" DIR=0x%04x", cyrix_did);
1067 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1068 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1069 #ifndef CYRIX_CACHE_REALLY_WORKS
1070 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1071 printf("\n CPU cache: write-through mode");
1072 #endif
1073 #endif
1074 }
1075
1076 /* Avoid ugly blank lines: only print newline when we have to. */
1077 if (*cpu_vendor || cpu_id)
1078 printf("\n");
1079
1080 if (bootverbose) {
1081 if (cpu_vendor_id == CPU_VENDOR_AMD)
1082 print_AMD_info();
1083 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1084 print_INTEL_info();
1085 #ifdef __i386__
1086 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1087 print_transmeta_info();
1088 #endif
1089 }
1090
1091 print_hypervisor_info();
1092 }
1093
1094 #ifdef __i386__
1095 void
panicifcpuunsupported(void)1096 panicifcpuunsupported(void)
1097 {
1098
1099 #if !defined(lint)
1100 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1101 #error This kernel is not configured for one of the supported CPUs
1102 #endif
1103 #else /* lint */
1104 #endif /* lint */
1105 /*
1106 * Now that we have told the user what they have,
1107 * let them know if that machine type isn't configured.
1108 */
1109 switch (cpu_class) {
1110 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1111 case CPUCLASS_386:
1112 #if !defined(I486_CPU)
1113 case CPUCLASS_486:
1114 #endif
1115 #if !defined(I586_CPU)
1116 case CPUCLASS_586:
1117 #endif
1118 #if !defined(I686_CPU)
1119 case CPUCLASS_686:
1120 #endif
1121 panic("CPU class not configured");
1122 default:
1123 break;
1124 }
1125 }
1126
1127 static volatile u_int trap_by_rdmsr;
1128
1129 /*
1130 * Special exception 6 handler.
1131 * The rdmsr instruction generates invalid opcodes fault on 486-class
1132 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1133 * function identblue() when this handler is called. Stacked eip should
1134 * be advanced.
1135 */
1136 inthand_t bluetrap6;
1137 #ifdef __GNUCLIKE_ASM
1138 __asm
1139 (" \n\
1140 .text \n\
1141 .p2align 2,0x90 \n\
1142 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1143 " __XSTRING(CNAME(bluetrap6)) ": \n\
1144 ss \n\
1145 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1146 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1147 iret \n\
1148 ");
1149 #endif
1150
1151 /*
1152 * Special exception 13 handler.
1153 * Accessing non-existent MSR generates general protection fault.
1154 */
1155 inthand_t bluetrap13;
1156 #ifdef __GNUCLIKE_ASM
1157 __asm
1158 (" \n\
1159 .text \n\
1160 .p2align 2,0x90 \n\
1161 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1162 " __XSTRING(CNAME(bluetrap13)) ": \n\
1163 ss \n\
1164 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1165 popl %eax /* discard error code */ \n\
1166 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1167 iret \n\
1168 ");
1169 #endif
1170
1171 /*
1172 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1173 * support cpuid instruction. This function should be called after
1174 * loading interrupt descriptor table register.
1175 *
1176 * I don't like this method that handles fault, but I couldn't get
1177 * information for any other methods. Does blue giant know?
1178 */
1179 static int
identblue(void)1180 identblue(void)
1181 {
1182
1183 trap_by_rdmsr = 0;
1184
1185 /*
1186 * Cyrix 486-class CPU does not support rdmsr instruction.
1187 * The rdmsr instruction generates invalid opcode fault, and exception
1188 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1189 * bluetrap6() set the magic number to trap_by_rdmsr.
1190 */
1191 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1192 GSEL(GCODE_SEL, SEL_KPL));
1193
1194 /*
1195 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1196 * In this case, rdmsr generates general protection fault, and
1197 * exception will be trapped by bluetrap13().
1198 */
1199 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1200 GSEL(GCODE_SEL, SEL_KPL));
1201
1202 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1203
1204 if (trap_by_rdmsr == 0xa8c1d)
1205 return IDENTBLUE_CYRIX486;
1206 else if (trap_by_rdmsr == 0xa89c4)
1207 return IDENTBLUE_CYRIXM2;
1208 return IDENTBLUE_IBMCPU;
1209 }
1210
1211
1212 /*
1213 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1214 *
1215 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1216 * +-------+-------+---------------+
1217 * | SID | RID | Device ID |
1218 * | (DIR 1) | (DIR 0) |
1219 * +-------+-------+---------------+
1220 */
1221 static void
identifycyrix(void)1222 identifycyrix(void)
1223 {
1224 register_t saveintr;
1225 int ccr2_test = 0, dir_test = 0;
1226 u_char ccr2, ccr3;
1227
1228 saveintr = intr_disable();
1229
1230 ccr2 = read_cyrix_reg(CCR2);
1231 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1232 read_cyrix_reg(CCR2);
1233 if (read_cyrix_reg(CCR2) != ccr2)
1234 ccr2_test = 1;
1235 write_cyrix_reg(CCR2, ccr2);
1236
1237 ccr3 = read_cyrix_reg(CCR3);
1238 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1239 read_cyrix_reg(CCR3);
1240 if (read_cyrix_reg(CCR3) != ccr3)
1241 dir_test = 1; /* CPU supports DIRs. */
1242 write_cyrix_reg(CCR3, ccr3);
1243
1244 if (dir_test) {
1245 /* Device ID registers are available. */
1246 cyrix_did = read_cyrix_reg(DIR1) << 8;
1247 cyrix_did += read_cyrix_reg(DIR0);
1248 } else if (ccr2_test)
1249 cyrix_did = 0x0010; /* 486S A-step */
1250 else
1251 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1252
1253 intr_restore(saveintr);
1254 }
1255 #endif
1256
1257 /* Update TSC freq with the value indicated by the caller. */
1258 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1259 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1260 {
1261
1262 /* If there was an error during the transition, don't do anything. */
1263 if (status != 0)
1264 return;
1265
1266 /* Total setting for this level gives the new frequency in MHz. */
1267 hw_clockrate = level->total_set.freq;
1268 }
1269
1270 static void
hook_tsc_freq(void * arg __unused)1271 hook_tsc_freq(void *arg __unused)
1272 {
1273
1274 if (tsc_is_invariant)
1275 return;
1276
1277 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1278 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1279 }
1280
1281 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1282
1283 static const char *const vm_bnames[] = {
1284 "QEMU", /* QEMU */
1285 "Plex86", /* Plex86 */
1286 "Bochs", /* Bochs */
1287 "Xen", /* Xen */
1288 "BHYVE", /* bhyve */
1289 "Seabios", /* KVM */
1290 NULL
1291 };
1292
1293 static const char *const vm_pnames[] = {
1294 "VMware Virtual Platform", /* VMWare VM */
1295 "Virtual Machine", /* Microsoft VirtualPC */
1296 "VirtualBox", /* Sun xVM VirtualBox */
1297 "Parallels Virtual Platform", /* Parallels VM */
1298 "KVM", /* KVM */
1299 NULL
1300 };
1301
1302 void
identify_hypervisor(void)1303 identify_hypervisor(void)
1304 {
1305 u_int regs[4];
1306 char *p;
1307 int i;
1308
1309 /*
1310 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1311 * http://lkml.org/lkml/2008/10/1/246
1312 *
1313 * KB1009458: Mechanisms to determine if software is running in
1314 * a VMware virtual machine
1315 * http://kb.vmware.com/kb/1009458
1316 */
1317 if (cpu_feature2 & CPUID2_HV) {
1318 vm_guest = VM_GUEST_VM;
1319 do_cpuid(0x40000000, regs);
1320
1321 /*
1322 * KVM from Linux kernels prior to commit
1323 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1324 * to 0 rather than a valid hv_high value. Check for
1325 * the KVM signature bytes and fixup %eax to the
1326 * highest supported leaf in that case.
1327 */
1328 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1329 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1330 regs[0] = 0x40000001;
1331
1332 if (regs[0] >= 0x40000000) {
1333 hv_high = regs[0];
1334 ((u_int *)&hv_vendor)[0] = regs[1];
1335 ((u_int *)&hv_vendor)[1] = regs[2];
1336 ((u_int *)&hv_vendor)[2] = regs[3];
1337 hv_vendor[12] = '\0';
1338 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1339 vm_guest = VM_GUEST_VMWARE;
1340 else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1341 vm_guest = VM_GUEST_HV;
1342 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1343 vm_guest = VM_GUEST_KVM;
1344 else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1345 vm_guest = VM_GUEST_BHYVE;
1346 }
1347 return;
1348 }
1349
1350 /*
1351 * Examine SMBIOS strings for older hypervisors.
1352 */
1353 p = kern_getenv("smbios.system.serial");
1354 if (p != NULL) {
1355 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1356 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1357 if (regs[1] == VMW_HVMAGIC) {
1358 vm_guest = VM_GUEST_VMWARE;
1359 freeenv(p);
1360 return;
1361 }
1362 }
1363 freeenv(p);
1364 }
1365
1366 /*
1367 * XXX: Some of these entries may not be needed since they were
1368 * added to FreeBSD before the checks above.
1369 */
1370 p = kern_getenv("smbios.bios.vendor");
1371 if (p != NULL) {
1372 for (i = 0; vm_bnames[i] != NULL; i++)
1373 if (strcmp(p, vm_bnames[i]) == 0) {
1374 vm_guest = VM_GUEST_VM;
1375 freeenv(p);
1376 return;
1377 }
1378 freeenv(p);
1379 }
1380 p = kern_getenv("smbios.system.product");
1381 if (p != NULL) {
1382 for (i = 0; vm_pnames[i] != NULL; i++)
1383 if (strcmp(p, vm_pnames[i]) == 0) {
1384 vm_guest = VM_GUEST_VM;
1385 freeenv(p);
1386 return;
1387 }
1388 freeenv(p);
1389 }
1390 }
1391
1392 bool
fix_cpuid(void)1393 fix_cpuid(void)
1394 {
1395 uint64_t msr;
1396
1397 /*
1398 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1399 * get the largest standard CPUID function number again if it is set
1400 * from BIOS. It is necessary for probing correct CPU topology later
1401 * and for the correct operation of the AVX-aware userspace.
1402 */
1403 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1404 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1405 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1406 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1407 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1408 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1409 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1410 msr &= ~IA32_MISC_EN_LIMCPUID;
1411 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1412 return (true);
1413 }
1414 }
1415
1416 /*
1417 * Re-enable AMD Topology Extension that could be disabled by BIOS
1418 * on some notebook processors. Without the extension it's really
1419 * hard to determine the correct CPU cache topology.
1420 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1421 * Models 60h-6Fh Processors, Publication # 50742.
1422 */
1423 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1424 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1425 msr = rdmsr(MSR_EXTFEATURES);
1426 if ((msr & ((uint64_t)1 << 54)) == 0) {
1427 msr |= (uint64_t)1 << 54;
1428 wrmsr(MSR_EXTFEATURES, msr);
1429 return (true);
1430 }
1431 }
1432 return (false);
1433 }
1434
1435 void
identify_cpu1(void)1436 identify_cpu1(void)
1437 {
1438 u_int regs[4];
1439
1440 do_cpuid(0, regs);
1441 cpu_high = regs[0];
1442 ((u_int *)&cpu_vendor)[0] = regs[1];
1443 ((u_int *)&cpu_vendor)[1] = regs[3];
1444 ((u_int *)&cpu_vendor)[2] = regs[2];
1445 cpu_vendor[12] = '\0';
1446
1447 do_cpuid(1, regs);
1448 cpu_id = regs[0];
1449 cpu_procinfo = regs[1];
1450 cpu_feature = regs[3];
1451 cpu_feature2 = regs[2];
1452 }
1453
1454 void
identify_cpu2(void)1455 identify_cpu2(void)
1456 {
1457 u_int regs[4], cpu_stdext_disable;
1458
1459 if (cpu_high >= 7) {
1460 cpuid_count(7, 0, regs);
1461 cpu_stdext_feature = regs[1];
1462
1463 /*
1464 * Some hypervisors failed to filter out unsupported
1465 * extended features. Allow to disable the
1466 * extensions, activation of which requires setting a
1467 * bit in CR4, and which VM monitors do not support.
1468 */
1469 cpu_stdext_disable = 0;
1470 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1471 cpu_stdext_feature &= ~cpu_stdext_disable;
1472
1473 cpu_stdext_feature2 = regs[2];
1474 cpu_stdext_feature3 = regs[3];
1475
1476 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1477 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1478 }
1479 }
1480
1481 void
identify_cpu_fixup_bsp(void)1482 identify_cpu_fixup_bsp(void)
1483 {
1484 u_int regs[4];
1485
1486 cpu_vendor_id = find_cpu_vendor_id();
1487
1488 if (fix_cpuid()) {
1489 do_cpuid(0, regs);
1490 cpu_high = regs[0];
1491 }
1492 }
1493
1494 /*
1495 * Final stage of CPU identification.
1496 */
1497 void
finishidentcpu(void)1498 finishidentcpu(void)
1499 {
1500 u_int regs[4];
1501 #ifdef __i386__
1502 u_char ccr3;
1503 #endif
1504
1505 identify_cpu_fixup_bsp();
1506
1507 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1508 do_cpuid(5, regs);
1509 cpu_mon_mwait_flags = regs[2];
1510 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1511 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1512 }
1513
1514 identify_cpu2();
1515
1516 #ifdef __i386__
1517 if (cpu_high > 0 &&
1518 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1519 cpu_vendor_id == CPU_VENDOR_AMD ||
1520 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1521 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1522 cpu_vendor_id == CPU_VENDOR_NSC)) {
1523 do_cpuid(0x80000000, regs);
1524 if (regs[0] >= 0x80000000)
1525 cpu_exthigh = regs[0];
1526 }
1527 #else
1528 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1529 cpu_vendor_id == CPU_VENDOR_AMD ||
1530 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1531 do_cpuid(0x80000000, regs);
1532 cpu_exthigh = regs[0];
1533 }
1534 #endif
1535 if (cpu_exthigh >= 0x80000001) {
1536 do_cpuid(0x80000001, regs);
1537 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1538 amd_feature2 = regs[2];
1539 }
1540 if (cpu_exthigh >= 0x80000007) {
1541 do_cpuid(0x80000007, regs);
1542 amd_rascap = regs[1];
1543 amd_pminfo = regs[3];
1544 }
1545 if (cpu_exthigh >= 0x80000008) {
1546 do_cpuid(0x80000008, regs);
1547 cpu_maxphyaddr = regs[0] & 0xff;
1548 amd_extended_feature_extensions = regs[1];
1549 cpu_procinfo2 = regs[2];
1550 } else {
1551 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1552 }
1553
1554 #ifdef __i386__
1555 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1556 if (cpu == CPU_486) {
1557 /*
1558 * These conditions are equivalent to:
1559 * - CPU does not support cpuid instruction.
1560 * - Cyrix/IBM CPU is detected.
1561 */
1562 if (identblue() == IDENTBLUE_IBMCPU) {
1563 strcpy(cpu_vendor, "IBM");
1564 cpu_vendor_id = CPU_VENDOR_IBM;
1565 cpu = CPU_BLUE;
1566 return;
1567 }
1568 }
1569 switch (cpu_id & 0xf00) {
1570 case 0x600:
1571 /*
1572 * Cyrix's datasheet does not describe DIRs.
1573 * Therefor, I assume it does not have them
1574 * and use the result of the cpuid instruction.
1575 * XXX they seem to have it for now at least. -Peter
1576 */
1577 identifycyrix();
1578 cpu = CPU_M2;
1579 break;
1580 default:
1581 identifycyrix();
1582 /*
1583 * This routine contains a trick.
1584 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1585 */
1586 switch (cyrix_did & 0x00f0) {
1587 case 0x00:
1588 case 0xf0:
1589 cpu = CPU_486DLC;
1590 break;
1591 case 0x10:
1592 cpu = CPU_CY486DX;
1593 break;
1594 case 0x20:
1595 if ((cyrix_did & 0x000f) < 8)
1596 cpu = CPU_M1;
1597 else
1598 cpu = CPU_M1SC;
1599 break;
1600 case 0x30:
1601 cpu = CPU_M1;
1602 break;
1603 case 0x40:
1604 /* MediaGX CPU */
1605 cpu = CPU_M1SC;
1606 break;
1607 default:
1608 /* M2 and later CPUs are treated as M2. */
1609 cpu = CPU_M2;
1610
1611 /*
1612 * enable cpuid instruction.
1613 */
1614 ccr3 = read_cyrix_reg(CCR3);
1615 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1616 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1617 write_cyrix_reg(CCR3, ccr3);
1618
1619 do_cpuid(0, regs);
1620 cpu_high = regs[0]; /* eax */
1621 do_cpuid(1, regs);
1622 cpu_id = regs[0]; /* eax */
1623 cpu_feature = regs[3]; /* edx */
1624 break;
1625 }
1626 }
1627 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1628 /*
1629 * There are BlueLightning CPUs that do not change
1630 * undefined flags by dividing 5 by 2. In this case,
1631 * the CPU identification routine in locore.s leaves
1632 * cpu_vendor null string and puts CPU_486 into the
1633 * cpu.
1634 */
1635 if (identblue() == IDENTBLUE_IBMCPU) {
1636 strcpy(cpu_vendor, "IBM");
1637 cpu_vendor_id = CPU_VENDOR_IBM;
1638 cpu = CPU_BLUE;
1639 return;
1640 }
1641 }
1642 #endif
1643 }
1644
1645 int
pti_get_default(void)1646 pti_get_default(void)
1647 {
1648
1649 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1650 return (0);
1651 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1652 return (0);
1653 return (1);
1654 }
1655
1656 static u_int
find_cpu_vendor_id(void)1657 find_cpu_vendor_id(void)
1658 {
1659 int i;
1660
1661 for (i = 0; i < nitems(cpu_vendors); i++)
1662 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1663 return (cpu_vendors[i].vendor_id);
1664 return (0);
1665 }
1666
1667 static void
print_AMD_assoc(int i)1668 print_AMD_assoc(int i)
1669 {
1670 if (i == 255)
1671 printf(", fully associative\n");
1672 else
1673 printf(", %d-way associative\n", i);
1674 }
1675
1676 static void
print_AMD_l2_assoc(int i)1677 print_AMD_l2_assoc(int i)
1678 {
1679 switch (i & 0x0f) {
1680 case 0: printf(", disabled/not present\n"); break;
1681 case 1: printf(", direct mapped\n"); break;
1682 case 2: printf(", 2-way associative\n"); break;
1683 case 4: printf(", 4-way associative\n"); break;
1684 case 6: printf(", 8-way associative\n"); break;
1685 case 8: printf(", 16-way associative\n"); break;
1686 case 15: printf(", fully associative\n"); break;
1687 default: printf(", reserved configuration\n"); break;
1688 }
1689 }
1690
1691 static void
print_AMD_info(void)1692 print_AMD_info(void)
1693 {
1694 #ifdef __i386__
1695 uint64_t amd_whcr;
1696 #endif
1697 u_int regs[4];
1698
1699 if (cpu_exthigh >= 0x80000005) {
1700 do_cpuid(0x80000005, regs);
1701 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1702 print_AMD_assoc(regs[0] >> 24);
1703
1704 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1705 print_AMD_assoc((regs[0] >> 8) & 0xff);
1706
1707 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1708 print_AMD_assoc(regs[1] >> 24);
1709
1710 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1711 print_AMD_assoc((regs[1] >> 8) & 0xff);
1712
1713 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1714 printf(", %d bytes/line", regs[2] & 0xff);
1715 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1716 print_AMD_assoc((regs[2] >> 16) & 0xff);
1717
1718 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1719 printf(", %d bytes/line", regs[3] & 0xff);
1720 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1721 print_AMD_assoc((regs[3] >> 16) & 0xff);
1722 }
1723
1724 if (cpu_exthigh >= 0x80000006) {
1725 do_cpuid(0x80000006, regs);
1726 if ((regs[0] >> 16) != 0) {
1727 printf("L2 2MB data TLB: %d entries",
1728 (regs[0] >> 16) & 0xfff);
1729 print_AMD_l2_assoc(regs[0] >> 28);
1730 printf("L2 2MB instruction TLB: %d entries",
1731 regs[0] & 0xfff);
1732 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1733 } else {
1734 printf("L2 2MB unified TLB: %d entries",
1735 regs[0] & 0xfff);
1736 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1737 }
1738 if ((regs[1] >> 16) != 0) {
1739 printf("L2 4KB data TLB: %d entries",
1740 (regs[1] >> 16) & 0xfff);
1741 print_AMD_l2_assoc(regs[1] >> 28);
1742
1743 printf("L2 4KB instruction TLB: %d entries",
1744 (regs[1] >> 16) & 0xfff);
1745 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1746 } else {
1747 printf("L2 4KB unified TLB: %d entries",
1748 (regs[1] >> 16) & 0xfff);
1749 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1750 }
1751 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1752 printf(", %d bytes/line", regs[2] & 0xff);
1753 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1754 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1755 }
1756
1757 #ifdef __i386__
1758 if (((cpu_id & 0xf00) == 0x500)
1759 && (((cpu_id & 0x0f0) > 0x80)
1760 || (((cpu_id & 0x0f0) == 0x80)
1761 && (cpu_id & 0x00f) > 0x07))) {
1762 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1763 amd_whcr = rdmsr(0xc0000082);
1764 if (!(amd_whcr & (0x3ff << 22))) {
1765 printf("Write Allocate Disable\n");
1766 } else {
1767 printf("Write Allocate Enable Limit: %dM bytes\n",
1768 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1769 printf("Write Allocate 15-16M bytes: %s\n",
1770 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1771 }
1772 } else if (((cpu_id & 0xf00) == 0x500)
1773 && ((cpu_id & 0x0f0) > 0x50)) {
1774 /* K6, K6-2(old core) */
1775 amd_whcr = rdmsr(0xc0000082);
1776 if (!(amd_whcr & (0x7f << 1))) {
1777 printf("Write Allocate Disable\n");
1778 } else {
1779 printf("Write Allocate Enable Limit: %dM bytes\n",
1780 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1781 printf("Write Allocate 15-16M bytes: %s\n",
1782 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1783 printf("Hardware Write Allocate Control: %s\n",
1784 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1785 }
1786 }
1787 #endif
1788 /*
1789 * Opteron Rev E shows a bug as in very rare occasions a read memory
1790 * barrier is not performed as expected if it is followed by a
1791 * non-atomic read-modify-write instruction.
1792 * As long as that bug pops up very rarely (intensive machine usage
1793 * on other operating systems generally generates one unexplainable
1794 * crash any 2 months) and as long as a model specific fix would be
1795 * impractical at this stage, print out a warning string if the broken
1796 * model and family are identified.
1797 */
1798 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1799 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1800 printf("WARNING: This architecture revision has known SMP "
1801 "hardware bugs which may cause random instability\n");
1802 }
1803
1804 static void
print_INTEL_info(void)1805 print_INTEL_info(void)
1806 {
1807 u_int regs[4];
1808 u_int rounds, regnum;
1809 u_int nwaycode, nway;
1810
1811 if (cpu_high >= 2) {
1812 rounds = 0;
1813 do {
1814 do_cpuid(0x2, regs);
1815 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1816 break; /* we have a buggy CPU */
1817
1818 for (regnum = 0; regnum <= 3; ++regnum) {
1819 if (regs[regnum] & (1<<31))
1820 continue;
1821 if (regnum != 0)
1822 print_INTEL_TLB(regs[regnum] & 0xff);
1823 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1824 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1825 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1826 }
1827 } while (--rounds > 0);
1828 }
1829
1830 if (cpu_exthigh >= 0x80000006) {
1831 do_cpuid(0x80000006, regs);
1832 nwaycode = (regs[2] >> 12) & 0x0f;
1833 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1834 nway = 1 << (nwaycode / 2);
1835 else
1836 nway = 0;
1837 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1838 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1839 }
1840 }
1841
1842 static void
print_INTEL_TLB(u_int data)1843 print_INTEL_TLB(u_int data)
1844 {
1845 switch (data) {
1846 case 0x0:
1847 case 0x40:
1848 default:
1849 break;
1850 case 0x1:
1851 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1852 break;
1853 case 0x2:
1854 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1855 break;
1856 case 0x3:
1857 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1858 break;
1859 case 0x4:
1860 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1861 break;
1862 case 0x6:
1863 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1864 break;
1865 case 0x8:
1866 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1867 break;
1868 case 0x9:
1869 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1870 break;
1871 case 0xa:
1872 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1873 break;
1874 case 0xb:
1875 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1876 break;
1877 case 0xc:
1878 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1879 break;
1880 case 0xd:
1881 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1882 break;
1883 case 0xe:
1884 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1885 break;
1886 case 0x1d:
1887 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1888 break;
1889 case 0x21:
1890 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1891 break;
1892 case 0x22:
1893 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1894 break;
1895 case 0x23:
1896 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1897 break;
1898 case 0x24:
1899 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1900 break;
1901 case 0x25:
1902 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1903 break;
1904 case 0x29:
1905 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1906 break;
1907 case 0x2c:
1908 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1909 break;
1910 case 0x30:
1911 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1912 break;
1913 case 0x39: /* De-listed in SDM rev. 54 */
1914 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1915 break;
1916 case 0x3b: /* De-listed in SDM rev. 54 */
1917 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1918 break;
1919 case 0x3c: /* De-listed in SDM rev. 54 */
1920 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1921 break;
1922 case 0x41:
1923 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1924 break;
1925 case 0x42:
1926 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1927 break;
1928 case 0x43:
1929 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1930 break;
1931 case 0x44:
1932 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1933 break;
1934 case 0x45:
1935 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1936 break;
1937 case 0x46:
1938 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1939 break;
1940 case 0x47:
1941 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1942 break;
1943 case 0x48:
1944 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1945 break;
1946 case 0x49:
1947 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1948 CPUID_TO_MODEL(cpu_id) == 0x6)
1949 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1950 else
1951 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1952 break;
1953 case 0x4a:
1954 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1955 break;
1956 case 0x4b:
1957 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1958 break;
1959 case 0x4c:
1960 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1961 break;
1962 case 0x4d:
1963 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1964 break;
1965 case 0x4e:
1966 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1967 break;
1968 case 0x4f:
1969 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1970 break;
1971 case 0x50:
1972 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1973 break;
1974 case 0x51:
1975 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1976 break;
1977 case 0x52:
1978 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1979 break;
1980 case 0x55:
1981 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1982 break;
1983 case 0x56:
1984 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1985 break;
1986 case 0x57:
1987 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1988 break;
1989 case 0x59:
1990 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1991 break;
1992 case 0x5a:
1993 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1994 break;
1995 case 0x5b:
1996 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1997 break;
1998 case 0x5c:
1999 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2000 break;
2001 case 0x5d:
2002 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2003 break;
2004 case 0x60:
2005 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2006 break;
2007 case 0x61:
2008 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2009 break;
2010 case 0x63:
2011 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2012 break;
2013 case 0x64:
2014 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2015 break;
2016 case 0x66:
2017 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2018 break;
2019 case 0x67:
2020 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2021 break;
2022 case 0x68:
2023 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2024 break;
2025 case 0x6a:
2026 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2027 break;
2028 case 0x6b:
2029 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2030 break;
2031 case 0x6c:
2032 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2033 break;
2034 case 0x6d:
2035 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2036 break;
2037 case 0x70:
2038 printf("Trace cache: 12K-uops, 8-way set associative\n");
2039 break;
2040 case 0x71:
2041 printf("Trace cache: 16K-uops, 8-way set associative\n");
2042 break;
2043 case 0x72:
2044 printf("Trace cache: 32K-uops, 8-way set associative\n");
2045 break;
2046 case 0x76:
2047 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2048 break;
2049 case 0x78:
2050 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2051 break;
2052 case 0x79:
2053 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2054 break;
2055 case 0x7a:
2056 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2057 break;
2058 case 0x7b:
2059 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2060 break;
2061 case 0x7c:
2062 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2063 break;
2064 case 0x7d:
2065 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2066 break;
2067 case 0x7f:
2068 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2069 break;
2070 case 0x80:
2071 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2072 break;
2073 case 0x82:
2074 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2075 break;
2076 case 0x83:
2077 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2078 break;
2079 case 0x84:
2080 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2081 break;
2082 case 0x85:
2083 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2084 break;
2085 case 0x86:
2086 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2087 break;
2088 case 0x87:
2089 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2090 break;
2091 case 0xa0:
2092 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2093 break;
2094 case 0xb0:
2095 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2096 break;
2097 case 0xb1:
2098 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2099 break;
2100 case 0xb2:
2101 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2102 break;
2103 case 0xb3:
2104 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2105 break;
2106 case 0xb4:
2107 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2108 break;
2109 case 0xb5:
2110 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2111 break;
2112 case 0xb6:
2113 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2114 break;
2115 case 0xba:
2116 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2117 break;
2118 case 0xc0:
2119 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2120 break;
2121 case 0xc1:
2122 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2123 break;
2124 case 0xc2:
2125 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2126 break;
2127 case 0xc3:
2128 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2129 break;
2130 case 0xc4:
2131 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2132 break;
2133 case 0xca:
2134 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2135 break;
2136 case 0xd0:
2137 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2138 break;
2139 case 0xd1:
2140 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2141 break;
2142 case 0xd2:
2143 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2144 break;
2145 case 0xd6:
2146 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2147 break;
2148 case 0xd7:
2149 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2150 break;
2151 case 0xd8:
2152 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2153 break;
2154 case 0xdc:
2155 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2156 break;
2157 case 0xdd:
2158 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2159 break;
2160 case 0xde:
2161 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2162 break;
2163 case 0xe2:
2164 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2165 break;
2166 case 0xe3:
2167 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2168 break;
2169 case 0xe4:
2170 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2171 break;
2172 case 0xea:
2173 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2174 break;
2175 case 0xeb:
2176 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2177 break;
2178 case 0xec:
2179 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2180 break;
2181 case 0xf0:
2182 printf("64-Byte prefetching\n");
2183 break;
2184 case 0xf1:
2185 printf("128-Byte prefetching\n");
2186 break;
2187 }
2188 }
2189
2190 static void
print_svm_info(void)2191 print_svm_info(void)
2192 {
2193 u_int features, regs[4];
2194 uint64_t msr;
2195 int comma;
2196
2197 printf("\n SVM: ");
2198 do_cpuid(0x8000000A, regs);
2199 features = regs[3];
2200
2201 msr = rdmsr(MSR_VM_CR);
2202 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2203 printf("(disabled in BIOS) ");
2204
2205 if (!bootverbose) {
2206 comma = 0;
2207 if (features & (1 << 0)) {
2208 printf("%sNP", comma ? "," : "");
2209 comma = 1;
2210 }
2211 if (features & (1 << 3)) {
2212 printf("%sNRIP", comma ? "," : "");
2213 comma = 1;
2214 }
2215 if (features & (1 << 5)) {
2216 printf("%sVClean", comma ? "," : "");
2217 comma = 1;
2218 }
2219 if (features & (1 << 6)) {
2220 printf("%sAFlush", comma ? "," : "");
2221 comma = 1;
2222 }
2223 if (features & (1 << 7)) {
2224 printf("%sDAssist", comma ? "," : "");
2225 comma = 1;
2226 }
2227 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2228 return;
2229 }
2230
2231 printf("Features=0x%b", features,
2232 "\020"
2233 "\001NP" /* Nested paging */
2234 "\002LbrVirt" /* LBR virtualization */
2235 "\003SVML" /* SVM lock */
2236 "\004NRIPS" /* NRIP save */
2237 "\005TscRateMsr" /* MSR based TSC rate control */
2238 "\006VmcbClean" /* VMCB clean bits */
2239 "\007FlushByAsid" /* Flush by ASID */
2240 "\010DecodeAssist" /* Decode assist */
2241 "\011<b8>"
2242 "\012<b9>"
2243 "\013PauseFilter" /* PAUSE intercept filter */
2244 "\014EncryptedMcodePatch"
2245 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2246 "\016AVIC" /* virtual interrupt controller */
2247 "\017<b14>"
2248 "\020V_VMSAVE_VMLOAD"
2249 "\021vGIF"
2250 "\022<b17>"
2251 "\023<b18>"
2252 "\024<b19>"
2253 "\025<b20>"
2254 "\026<b21>"
2255 "\027<b22>"
2256 "\030<b23>"
2257 "\031<b24>"
2258 "\032<b25>"
2259 "\033<b26>"
2260 "\034<b27>"
2261 "\035<b28>"
2262 "\036<b29>"
2263 "\037<b30>"
2264 "\040<b31>"
2265 );
2266 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2267 }
2268
2269 #ifdef __i386__
2270 static void
print_transmeta_info(void)2271 print_transmeta_info(void)
2272 {
2273 u_int regs[4], nreg = 0;
2274
2275 do_cpuid(0x80860000, regs);
2276 nreg = regs[0];
2277 if (nreg >= 0x80860001) {
2278 do_cpuid(0x80860001, regs);
2279 printf(" Processor revision %u.%u.%u.%u\n",
2280 (regs[1] >> 24) & 0xff,
2281 (regs[1] >> 16) & 0xff,
2282 (regs[1] >> 8) & 0xff,
2283 regs[1] & 0xff);
2284 }
2285 if (nreg >= 0x80860002) {
2286 do_cpuid(0x80860002, regs);
2287 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2288 (regs[1] >> 24) & 0xff,
2289 (regs[1] >> 16) & 0xff,
2290 (regs[1] >> 8) & 0xff,
2291 regs[1] & 0xff,
2292 regs[2]);
2293 }
2294 if (nreg >= 0x80860006) {
2295 char info[65];
2296 do_cpuid(0x80860003, (u_int*) &info[0]);
2297 do_cpuid(0x80860004, (u_int*) &info[16]);
2298 do_cpuid(0x80860005, (u_int*) &info[32]);
2299 do_cpuid(0x80860006, (u_int*) &info[48]);
2300 info[64] = 0;
2301 printf(" %s\n", info);
2302 }
2303 }
2304 #endif
2305
2306 static void
print_via_padlock_info(void)2307 print_via_padlock_info(void)
2308 {
2309 u_int regs[4];
2310
2311 do_cpuid(0xc0000001, regs);
2312 printf("\n VIA Padlock Features=0x%b", regs[3],
2313 "\020"
2314 "\003RNG" /* RNG */
2315 "\007AES" /* ACE */
2316 "\011AES-CTR" /* ACE2 */
2317 "\013SHA1,SHA256" /* PHE */
2318 "\015RSA" /* PMM */
2319 );
2320 }
2321
2322 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2323 vmx_settable(uint64_t basic, int msr, int true_msr)
2324 {
2325 uint64_t val;
2326
2327 if (basic & (1ULL << 55))
2328 val = rdmsr(true_msr);
2329 else
2330 val = rdmsr(msr);
2331
2332 /* Just report the controls that can be set to 1. */
2333 return (val >> 32);
2334 }
2335
2336 static void
print_vmx_info(void)2337 print_vmx_info(void)
2338 {
2339 uint64_t basic, msr;
2340 uint32_t entry, exit, mask, pin, proc, proc2;
2341 int comma;
2342
2343 printf("\n VT-x: ");
2344 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2345 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2346 printf("(disabled in BIOS) ");
2347 basic = rdmsr(MSR_VMX_BASIC);
2348 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2349 MSR_VMX_TRUE_PINBASED_CTLS);
2350 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2351 MSR_VMX_TRUE_PROCBASED_CTLS);
2352 if (proc & PROCBASED_SECONDARY_CONTROLS)
2353 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2354 MSR_VMX_PROCBASED_CTLS2);
2355 else
2356 proc2 = 0;
2357 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2358 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2359
2360 if (!bootverbose) {
2361 comma = 0;
2362 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2363 entry & VM_ENTRY_LOAD_PAT) {
2364 printf("%sPAT", comma ? "," : "");
2365 comma = 1;
2366 }
2367 if (proc & PROCBASED_HLT_EXITING) {
2368 printf("%sHLT", comma ? "," : "");
2369 comma = 1;
2370 }
2371 if (proc & PROCBASED_MTF) {
2372 printf("%sMTF", comma ? "," : "");
2373 comma = 1;
2374 }
2375 if (proc & PROCBASED_PAUSE_EXITING) {
2376 printf("%sPAUSE", comma ? "," : "");
2377 comma = 1;
2378 }
2379 if (proc2 & PROCBASED2_ENABLE_EPT) {
2380 printf("%sEPT", comma ? "," : "");
2381 comma = 1;
2382 }
2383 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2384 printf("%sUG", comma ? "," : "");
2385 comma = 1;
2386 }
2387 if (proc2 & PROCBASED2_ENABLE_VPID) {
2388 printf("%sVPID", comma ? "," : "");
2389 comma = 1;
2390 }
2391 if (proc & PROCBASED_USE_TPR_SHADOW &&
2392 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2393 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2394 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2395 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2396 printf("%sVID", comma ? "," : "");
2397 comma = 1;
2398 if (pin & PINBASED_POSTED_INTERRUPT)
2399 printf(",PostIntr");
2400 }
2401 return;
2402 }
2403
2404 mask = basic >> 32;
2405 printf("Basic Features=0x%b", mask,
2406 "\020"
2407 "\02132PA" /* 32-bit physical addresses */
2408 "\022SMM" /* SMM dual-monitor */
2409 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2410 "\030TRUE" /* TRUE_CTLS MSRs */
2411 );
2412 printf("\n Pin-Based Controls=0x%b", pin,
2413 "\020"
2414 "\001ExtINT" /* External-interrupt exiting */
2415 "\004NMI" /* NMI exiting */
2416 "\006VNMI" /* Virtual NMIs */
2417 "\007PreTmr" /* Activate VMX-preemption timer */
2418 "\010PostIntr" /* Process posted interrupts */
2419 );
2420 printf("\n Primary Processor Controls=0x%b", proc,
2421 "\020"
2422 "\003INTWIN" /* Interrupt-window exiting */
2423 "\004TSCOff" /* Use TSC offsetting */
2424 "\010HLT" /* HLT exiting */
2425 "\012INVLPG" /* INVLPG exiting */
2426 "\013MWAIT" /* MWAIT exiting */
2427 "\014RDPMC" /* RDPMC exiting */
2428 "\015RDTSC" /* RDTSC exiting */
2429 "\020CR3-LD" /* CR3-load exiting */
2430 "\021CR3-ST" /* CR3-store exiting */
2431 "\024CR8-LD" /* CR8-load exiting */
2432 "\025CR8-ST" /* CR8-store exiting */
2433 "\026TPR" /* Use TPR shadow */
2434 "\027NMIWIN" /* NMI-window exiting */
2435 "\030MOV-DR" /* MOV-DR exiting */
2436 "\031IO" /* Unconditional I/O exiting */
2437 "\032IOmap" /* Use I/O bitmaps */
2438 "\034MTF" /* Monitor trap flag */
2439 "\035MSRmap" /* Use MSR bitmaps */
2440 "\036MONITOR" /* MONITOR exiting */
2441 "\037PAUSE" /* PAUSE exiting */
2442 );
2443 if (proc & PROCBASED_SECONDARY_CONTROLS)
2444 printf("\n Secondary Processor Controls=0x%b", proc2,
2445 "\020"
2446 "\001APIC" /* Virtualize APIC accesses */
2447 "\002EPT" /* Enable EPT */
2448 "\003DT" /* Descriptor-table exiting */
2449 "\004RDTSCP" /* Enable RDTSCP */
2450 "\005x2APIC" /* Virtualize x2APIC mode */
2451 "\006VPID" /* Enable VPID */
2452 "\007WBINVD" /* WBINVD exiting */
2453 "\010UG" /* Unrestricted guest */
2454 "\011APIC-reg" /* APIC-register virtualization */
2455 "\012VID" /* Virtual-interrupt delivery */
2456 "\013PAUSE-loop" /* PAUSE-loop exiting */
2457 "\014RDRAND" /* RDRAND exiting */
2458 "\015INVPCID" /* Enable INVPCID */
2459 "\016VMFUNC" /* Enable VM functions */
2460 "\017VMCS" /* VMCS shadowing */
2461 "\020EPT#VE" /* EPT-violation #VE */
2462 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2463 );
2464 printf("\n Exit Controls=0x%b", mask,
2465 "\020"
2466 "\003DR" /* Save debug controls */
2467 /* Ignore Host address-space size */
2468 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2469 "\020AckInt" /* Acknowledge interrupt on exit */
2470 "\023PAT-SV" /* Save MSR_PAT */
2471 "\024PAT-LD" /* Load MSR_PAT */
2472 "\025EFER-SV" /* Save MSR_EFER */
2473 "\026EFER-LD" /* Load MSR_EFER */
2474 "\027PTMR-SV" /* Save VMX-preemption timer value */
2475 );
2476 printf("\n Entry Controls=0x%b", mask,
2477 "\020"
2478 "\003DR" /* Save debug controls */
2479 /* Ignore IA-32e mode guest */
2480 /* Ignore Entry to SMM */
2481 /* Ignore Deactivate dual-monitor treatment */
2482 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2483 "\017PAT" /* Load MSR_PAT */
2484 "\020EFER" /* Load MSR_EFER */
2485 );
2486 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2487 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2488 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2489 mask = msr;
2490 printf("\n EPT Features=0x%b", mask,
2491 "\020"
2492 "\001XO" /* Execute-only translations */
2493 "\007PW4" /* Page-walk length of 4 */
2494 "\011UC" /* EPT paging-structure mem can be UC */
2495 "\017WB" /* EPT paging-structure mem can be WB */
2496 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2497 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2498 "\025INVEPT" /* INVEPT is supported */
2499 "\026AD" /* Accessed and dirty flags for EPT */
2500 "\032single" /* INVEPT single-context type */
2501 "\033all" /* INVEPT all-context type */
2502 );
2503 mask = msr >> 32;
2504 printf("\n VPID Features=0x%b", mask,
2505 "\020"
2506 "\001INVVPID" /* INVVPID is supported */
2507 "\011individual" /* INVVPID individual-address type */
2508 "\012single" /* INVVPID single-context type */
2509 "\013all" /* INVVPID all-context type */
2510 /* INVVPID single-context-retaining-globals type */
2511 "\014single-globals"
2512 );
2513 }
2514 }
2515
2516 static void
print_hypervisor_info(void)2517 print_hypervisor_info(void)
2518 {
2519
2520 if (*hv_vendor)
2521 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2522 }
2523