1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Written by: [email protected]
5 * Copyright (c) 2002 Myson Technology Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
30 */
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/module.h>
43 #include <sys/lock.h>
44 #include <sys/mutex.h>
45
46 #define NBPFILTER 1
47
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_dl.h>
55 #include <net/bpf.h>
56
57 #include <vm/vm.h> /* for vtophys */
58 #include <vm/pmap.h> /* for vtophys */
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <sys/bus.h>
62 #include <sys/rman.h>
63
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66
67 /*
68 * #define MY_USEIOSPACE
69 */
70
71 static int MY_USEIOSPACE = 1;
72
73 #ifdef MY_USEIOSPACE
74 #define MY_RES SYS_RES_IOPORT
75 #define MY_RID MY_PCI_LOIO
76 #else
77 #define MY_RES SYS_RES_MEMORY
78 #define MY_RID MY_PCI_LOMEM
79 #endif
80
81 #include <dev/my/if_myreg.h>
82
83 /*
84 * Various supported device vendors/types and their names.
85 */
86 struct my_type *my_info_tmp;
87 static struct my_type my_devs[] = {
88 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
89 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
90 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
91 {0, 0, NULL}
92 };
93
94 /*
95 * Various supported PHY vendors/types and their names. Note that this driver
96 * will work with pretty much any MII-compliant PHY, so failure to positively
97 * identify the chip is not a fatal error.
98 */
99 static struct my_type my_phys[] = {
100 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
101 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
102 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
103 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
104 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
105 {0, 0, "<MII-compliant physical interface>"}
106 };
107
108 static int my_probe(device_t);
109 static int my_attach(device_t);
110 static int my_detach(device_t);
111 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
112 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
113 static void my_rxeof(struct my_softc *);
114 static void my_txeof(struct my_softc *);
115 static void my_txeoc(struct my_softc *);
116 static void my_intr(void *);
117 static void my_start(if_t);
118 static void my_start_locked(if_t);
119 static int my_ioctl(if_t, u_long, caddr_t);
120 static void my_init(void *);
121 static void my_init_locked(struct my_softc *);
122 static void my_stop(struct my_softc *);
123 static void my_autoneg_timeout(void *);
124 static void my_watchdog(void *);
125 static int my_shutdown(device_t);
126 static int my_ifmedia_upd(if_t);
127 static void my_ifmedia_sts(if_t, struct ifmediareq *);
128 static u_int16_t my_phy_readreg(struct my_softc *, int);
129 static void my_phy_writereg(struct my_softc *, int, int);
130 static void my_autoneg_xmit(struct my_softc *);
131 static void my_autoneg_mii(struct my_softc *, int, int);
132 static void my_setmode_mii(struct my_softc *, int);
133 static void my_getmode_mii(struct my_softc *);
134 static void my_setcfg(struct my_softc *, int);
135 static void my_setmulti(struct my_softc *);
136 static void my_reset(struct my_softc *);
137 static int my_list_rx_init(struct my_softc *);
138 static int my_list_tx_init(struct my_softc *);
139 static long my_send_cmd_to_phy(struct my_softc *, int, int);
140
141 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
142 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
143
144 static device_method_t my_methods[] = {
145 /* Device interface */
146 DEVMETHOD(device_probe, my_probe),
147 DEVMETHOD(device_attach, my_attach),
148 DEVMETHOD(device_detach, my_detach),
149 DEVMETHOD(device_shutdown, my_shutdown),
150
151 DEVMETHOD_END
152 };
153
154 static driver_t my_driver = {
155 "my",
156 my_methods,
157 sizeof(struct my_softc)
158 };
159
160 DRIVER_MODULE(my, pci, my_driver, 0, 0);
161 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, my, my_devs,
162 nitems(my_devs) - 1);
163 MODULE_DEPEND(my, pci, 1, 1, 1);
164 MODULE_DEPEND(my, ether, 1, 1, 1);
165
166 static long
my_send_cmd_to_phy(struct my_softc * sc,int opcode,int regad)167 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
168 {
169 long miir;
170 int i;
171 int mask, data;
172
173 MY_LOCK_ASSERT(sc);
174
175 /* enable MII output */
176 miir = CSR_READ_4(sc, MY_MANAGEMENT);
177 miir &= 0xfffffff0;
178
179 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
180
181 /* send 32 1's preamble */
182 for (i = 0; i < 32; i++) {
183 /* low MDC; MDO is already high (miir) */
184 miir &= ~MY_MASK_MIIR_MII_MDC;
185 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
186
187 /* high MDC */
188 miir |= MY_MASK_MIIR_MII_MDC;
189 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
190 }
191
192 /* calculate ST+OP+PHYAD+REGAD+TA */
193 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
194
195 /* sent out */
196 mask = 0x8000;
197 while (mask) {
198 /* low MDC, prepare MDO */
199 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
200 if (mask & data)
201 miir |= MY_MASK_MIIR_MII_MDO;
202
203 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
204 /* high MDC */
205 miir |= MY_MASK_MIIR_MII_MDC;
206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
207 DELAY(30);
208
209 /* next */
210 mask >>= 1;
211 if (mask == 0x2 && opcode == MY_OP_READ)
212 miir &= ~MY_MASK_MIIR_MII_WRITE;
213 }
214
215 return miir;
216 }
217
218 static u_int16_t
my_phy_readreg(struct my_softc * sc,int reg)219 my_phy_readreg(struct my_softc * sc, int reg)
220 {
221 long miir;
222 int mask, data;
223
224 MY_LOCK_ASSERT(sc);
225
226 if (sc->my_info->my_did == MTD803ID)
227 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
228 else {
229 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
230
231 /* read data */
232 mask = 0x8000;
233 data = 0;
234 while (mask) {
235 /* low MDC */
236 miir &= ~MY_MASK_MIIR_MII_MDC;
237 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
238
239 /* read MDI */
240 miir = CSR_READ_4(sc, MY_MANAGEMENT);
241 if (miir & MY_MASK_MIIR_MII_MDI)
242 data |= mask;
243
244 /* high MDC, and wait */
245 miir |= MY_MASK_MIIR_MII_MDC;
246 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
247 DELAY(30);
248
249 /* next */
250 mask >>= 1;
251 }
252
253 /* low MDC */
254 miir &= ~MY_MASK_MIIR_MII_MDC;
255 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
256 }
257
258 return (u_int16_t) data;
259 }
260
261 static void
my_phy_writereg(struct my_softc * sc,int reg,int data)262 my_phy_writereg(struct my_softc * sc, int reg, int data)
263 {
264 long miir;
265 int mask;
266
267 MY_LOCK_ASSERT(sc);
268
269 if (sc->my_info->my_did == MTD803ID)
270 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
271 else {
272 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
273
274 /* write data */
275 mask = 0x8000;
276 while (mask) {
277 /* low MDC, prepare MDO */
278 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
279 if (mask & data)
280 miir |= MY_MASK_MIIR_MII_MDO;
281 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
282 DELAY(1);
283
284 /* high MDC */
285 miir |= MY_MASK_MIIR_MII_MDC;
286 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
287 DELAY(1);
288
289 /* next */
290 mask >>= 1;
291 }
292
293 /* low MDC */
294 miir &= ~MY_MASK_MIIR_MII_MDC;
295 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
296 }
297 return;
298 }
299
300 static u_int
my_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)301 my_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
302 {
303 uint32_t *hashes = arg;
304 int h;
305
306 h = ~ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
307 if (h < 32)
308 hashes[0] |= (1 << h);
309 else
310 hashes[1] |= (1 << (h - 32));
311
312 return (1);
313 }
314 /*
315 * Program the 64-bit multicast hash filter.
316 */
317 static void
my_setmulti(struct my_softc * sc)318 my_setmulti(struct my_softc * sc)
319 {
320 if_t ifp;
321 u_int32_t hashes[2] = {0, 0};
322 u_int32_t rxfilt;
323
324 MY_LOCK_ASSERT(sc);
325
326 ifp = sc->my_ifp;
327
328 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
329
330 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
331 rxfilt |= MY_AM;
332 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
333 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
334 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
335
336 return;
337 }
338 /* first, zot all the existing hash bits */
339 CSR_WRITE_4(sc, MY_MAR0, 0);
340 CSR_WRITE_4(sc, MY_MAR1, 0);
341
342 /* now program new ones */
343 if (if_foreach_llmaddr(ifp, my_hash_maddr, hashes) > 0)
344 rxfilt |= MY_AM;
345 else
346 rxfilt &= ~MY_AM;
347 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
348 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
349 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
350 }
351
352 /*
353 * Initiate an autonegotiation session.
354 */
355 static void
my_autoneg_xmit(struct my_softc * sc)356 my_autoneg_xmit(struct my_softc * sc)
357 {
358 u_int16_t phy_sts = 0;
359
360 MY_LOCK_ASSERT(sc);
361
362 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
363 DELAY(500);
364 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
365
366 phy_sts = my_phy_readreg(sc, PHY_BMCR);
367 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
368 my_phy_writereg(sc, PHY_BMCR, phy_sts);
369
370 return;
371 }
372
373 static void
my_autoneg_timeout(void * arg)374 my_autoneg_timeout(void *arg)
375 {
376 struct my_softc *sc;
377
378 sc = arg;
379 MY_LOCK_ASSERT(sc);
380 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
381 }
382
383 /*
384 * Invoke autonegotiation on a PHY.
385 */
386 static void
my_autoneg_mii(struct my_softc * sc,int flag,int verbose)387 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
388 {
389 u_int16_t phy_sts = 0, media, advert, ability;
390 u_int16_t ability2 = 0;
391 if_t ifp;
392 struct ifmedia *ifm;
393
394 MY_LOCK_ASSERT(sc);
395
396 ifm = &sc->ifmedia;
397 ifp = sc->my_ifp;
398
399 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
400
401 #ifndef FORCE_AUTONEG_TFOUR
402 /*
403 * First, see if autoneg is supported. If not, there's no point in
404 * continuing.
405 */
406 phy_sts = my_phy_readreg(sc, PHY_BMSR);
407 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
408 if (verbose)
409 device_printf(sc->my_dev,
410 "autonegotiation not supported\n");
411 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
412 return;
413 }
414 #endif
415 switch (flag) {
416 case MY_FLAG_FORCEDELAY:
417 /*
418 * XXX Never use this option anywhere but in the probe
419 * routine: making the kernel stop dead in its tracks for
420 * three whole seconds after we've gone multi-user is really
421 * bad manners.
422 */
423 my_autoneg_xmit(sc);
424 DELAY(5000000);
425 break;
426 case MY_FLAG_SCHEDDELAY:
427 /*
428 * Wait for the transmitter to go idle before starting an
429 * autoneg session, otherwise my_start() may clobber our
430 * timeout, and we don't want to allow transmission during an
431 * autoneg session since that can screw it up.
432 */
433 if (sc->my_cdata.my_tx_head != NULL) {
434 sc->my_want_auto = 1;
435 MY_UNLOCK(sc);
436 return;
437 }
438 my_autoneg_xmit(sc);
439 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
440 sc);
441 sc->my_autoneg = 1;
442 sc->my_want_auto = 0;
443 return;
444 case MY_FLAG_DELAYTIMEO:
445 callout_stop(&sc->my_autoneg_timer);
446 sc->my_autoneg = 0;
447 break;
448 default:
449 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
450 return;
451 }
452
453 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
454 if (verbose)
455 device_printf(sc->my_dev, "autoneg complete, ");
456 phy_sts = my_phy_readreg(sc, PHY_BMSR);
457 } else {
458 if (verbose)
459 device_printf(sc->my_dev, "autoneg not complete, ");
460 }
461
462 media = my_phy_readreg(sc, PHY_BMCR);
463
464 /* Link is good. Report modes and set duplex mode. */
465 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
466 if (verbose)
467 device_printf(sc->my_dev, "link status good. ");
468 advert = my_phy_readreg(sc, PHY_ANAR);
469 ability = my_phy_readreg(sc, PHY_LPAR);
470 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
471 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
472 ability2 = my_phy_readreg(sc, PHY_1000SR);
473 if (ability2 & PHY_1000SR_1000BTXFULL) {
474 advert = 0;
475 ability = 0;
476 /*
477 * this version did not support 1000M,
478 * ifm->ifm_media =
479 * IFM_ETHER|IFM_1000_T|IFM_FDX;
480 */
481 ifm->ifm_media =
482 IFM_ETHER | IFM_100_TX | IFM_FDX;
483 media &= ~PHY_BMCR_SPEEDSEL;
484 media |= PHY_BMCR_1000;
485 media |= PHY_BMCR_DUPLEX;
486 printf("(full-duplex, 1000Mbps)\n");
487 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
488 advert = 0;
489 ability = 0;
490 /*
491 * this version did not support 1000M,
492 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
493 */
494 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
495 media &= ~PHY_BMCR_SPEEDSEL;
496 media &= ~PHY_BMCR_DUPLEX;
497 media |= PHY_BMCR_1000;
498 printf("(half-duplex, 1000Mbps)\n");
499 }
500 }
501 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
502 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
503 media |= PHY_BMCR_SPEEDSEL;
504 media &= ~PHY_BMCR_DUPLEX;
505 printf("(100baseT4)\n");
506 } else if (advert & PHY_ANAR_100BTXFULL &&
507 ability & PHY_ANAR_100BTXFULL) {
508 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
509 media |= PHY_BMCR_SPEEDSEL;
510 media |= PHY_BMCR_DUPLEX;
511 printf("(full-duplex, 100Mbps)\n");
512 } else if (advert & PHY_ANAR_100BTXHALF &&
513 ability & PHY_ANAR_100BTXHALF) {
514 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
515 media |= PHY_BMCR_SPEEDSEL;
516 media &= ~PHY_BMCR_DUPLEX;
517 printf("(half-duplex, 100Mbps)\n");
518 } else if (advert & PHY_ANAR_10BTFULL &&
519 ability & PHY_ANAR_10BTFULL) {
520 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
521 media &= ~PHY_BMCR_SPEEDSEL;
522 media |= PHY_BMCR_DUPLEX;
523 printf("(full-duplex, 10Mbps)\n");
524 } else if (advert) {
525 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
526 media &= ~PHY_BMCR_SPEEDSEL;
527 media &= ~PHY_BMCR_DUPLEX;
528 printf("(half-duplex, 10Mbps)\n");
529 }
530 media &= ~PHY_BMCR_AUTONEGENBL;
531
532 /* Set ASIC's duplex mode to match the PHY. */
533 my_phy_writereg(sc, PHY_BMCR, media);
534 my_setcfg(sc, media);
535 } else {
536 if (verbose)
537 device_printf(sc->my_dev, "no carrier\n");
538 }
539
540 my_init_locked(sc);
541 if (sc->my_tx_pend) {
542 sc->my_autoneg = 0;
543 sc->my_tx_pend = 0;
544 my_start_locked(ifp);
545 }
546 return;
547 }
548
549 /*
550 * To get PHY ability.
551 */
552 static void
my_getmode_mii(struct my_softc * sc)553 my_getmode_mii(struct my_softc * sc)
554 {
555 u_int16_t bmsr;
556 if_t ifp;
557
558 MY_LOCK_ASSERT(sc);
559 ifp = sc->my_ifp;
560 bmsr = my_phy_readreg(sc, PHY_BMSR);
561 if (bootverbose)
562 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
563
564 /* fallback */
565 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
566
567 if (bmsr & PHY_BMSR_10BTHALF) {
568 if (bootverbose)
569 device_printf(sc->my_dev,
570 "10Mbps half-duplex mode supported\n");
571 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
572 0, NULL);
573 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
574 }
575 if (bmsr & PHY_BMSR_10BTFULL) {
576 if (bootverbose)
577 device_printf(sc->my_dev,
578 "10Mbps full-duplex mode supported\n");
579
580 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
581 0, NULL);
582 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
583 }
584 if (bmsr & PHY_BMSR_100BTXHALF) {
585 if (bootverbose)
586 device_printf(sc->my_dev,
587 "100Mbps half-duplex mode supported\n");
588 if_setbaudrate(ifp, 100000000);
589 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
590 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
591 0, NULL);
592 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
593 }
594 if (bmsr & PHY_BMSR_100BTXFULL) {
595 if (bootverbose)
596 device_printf(sc->my_dev,
597 "100Mbps full-duplex mode supported\n");
598 if_setbaudrate(ifp, 100000000);
599 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
600 0, NULL);
601 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
602 }
603 /* Some also support 100BaseT4. */
604 if (bmsr & PHY_BMSR_100BT4) {
605 if (bootverbose)
606 device_printf(sc->my_dev, "100baseT4 mode supported\n");
607 if_setbaudrate(ifp, 100000000);
608 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
610 #ifdef FORCE_AUTONEG_TFOUR
611 if (bootverbose)
612 device_printf(sc->my_dev,
613 "forcing on autoneg support for BT4\n");
614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
615 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
616 #endif
617 }
618 #if 0 /* this version did not support 1000M, */
619 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
620 if (bootverbose)
621 device_printf(sc->my_dev,
622 "1000Mbps half-duplex mode supported\n");
623
624 if_setbaudrate(ifp, 1000000000);
625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
627 0, NULL);
628 if (bootverbose)
629 device_printf(sc->my_dev,
630 "1000Mbps full-duplex mode supported\n");
631 if_setbaudrate(ifp, 1000000000);
632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
633 0, NULL);
634 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
635 }
636 #endif
637 if (bmsr & PHY_BMSR_CANAUTONEG) {
638 if (bootverbose)
639 device_printf(sc->my_dev, "autoneg supported\n");
640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
642 }
643 return;
644 }
645
646 /*
647 * Set speed and duplex mode.
648 */
649 static void
my_setmode_mii(struct my_softc * sc,int media)650 my_setmode_mii(struct my_softc * sc, int media)
651 {
652 u_int16_t bmcr;
653
654 MY_LOCK_ASSERT(sc);
655 /*
656 * If an autoneg session is in progress, stop it.
657 */
658 if (sc->my_autoneg) {
659 device_printf(sc->my_dev, "canceling autoneg session\n");
660 callout_stop(&sc->my_autoneg_timer);
661 sc->my_autoneg = sc->my_want_auto = 0;
662 bmcr = my_phy_readreg(sc, PHY_BMCR);
663 bmcr &= ~PHY_BMCR_AUTONEGENBL;
664 my_phy_writereg(sc, PHY_BMCR, bmcr);
665 }
666 device_printf(sc->my_dev, "selecting MII, ");
667 bmcr = my_phy_readreg(sc, PHY_BMCR);
668 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
669 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
670
671 #if 0 /* this version did not support 1000M, */
672 if (IFM_SUBTYPE(media) == IFM_1000_T) {
673 printf("1000Mbps/T4, half-duplex\n");
674 bmcr &= ~PHY_BMCR_SPEEDSEL;
675 bmcr &= ~PHY_BMCR_DUPLEX;
676 bmcr |= PHY_BMCR_1000;
677 }
678 #endif
679 if (IFM_SUBTYPE(media) == IFM_100_T4) {
680 printf("100Mbps/T4, half-duplex\n");
681 bmcr |= PHY_BMCR_SPEEDSEL;
682 bmcr &= ~PHY_BMCR_DUPLEX;
683 }
684 if (IFM_SUBTYPE(media) == IFM_100_TX) {
685 printf("100Mbps, ");
686 bmcr |= PHY_BMCR_SPEEDSEL;
687 }
688 if (IFM_SUBTYPE(media) == IFM_10_T) {
689 printf("10Mbps, ");
690 bmcr &= ~PHY_BMCR_SPEEDSEL;
691 }
692 if ((media & IFM_GMASK) == IFM_FDX) {
693 printf("full duplex\n");
694 bmcr |= PHY_BMCR_DUPLEX;
695 } else {
696 printf("half duplex\n");
697 bmcr &= ~PHY_BMCR_DUPLEX;
698 }
699 my_phy_writereg(sc, PHY_BMCR, bmcr);
700 my_setcfg(sc, bmcr);
701 return;
702 }
703
704 /*
705 * The Myson manual states that in order to fiddle with the 'full-duplex' and
706 * '100Mbps' bits in the netconfig register, we first have to put the
707 * transmit and/or receive logic in the idle state.
708 */
709 static void
my_setcfg(struct my_softc * sc,int bmcr)710 my_setcfg(struct my_softc * sc, int bmcr)
711 {
712 int i, restart = 0;
713
714 MY_LOCK_ASSERT(sc);
715 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
716 restart = 1;
717 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
718 for (i = 0; i < MY_TIMEOUT; i++) {
719 DELAY(10);
720 if (!(CSR_READ_4(sc, MY_TCRRCR) &
721 (MY_TXRUN | MY_RXRUN)))
722 break;
723 }
724 if (i == MY_TIMEOUT)
725 device_printf(sc->my_dev,
726 "failed to force tx and rx to idle \n");
727 }
728 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
729 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
730 if (bmcr & PHY_BMCR_1000)
731 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
732 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
733 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
734 if (bmcr & PHY_BMCR_DUPLEX)
735 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
736 else
737 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
738 if (restart)
739 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
740 return;
741 }
742
743 static void
my_reset(struct my_softc * sc)744 my_reset(struct my_softc * sc)
745 {
746 int i;
747
748 MY_LOCK_ASSERT(sc);
749 MY_SETBIT(sc, MY_BCR, MY_SWR);
750 for (i = 0; i < MY_TIMEOUT; i++) {
751 DELAY(10);
752 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
753 break;
754 }
755 if (i == MY_TIMEOUT)
756 device_printf(sc->my_dev, "reset never completed!\n");
757
758 /* Wait a little while for the chip to get its brains in order. */
759 DELAY(1000);
760 return;
761 }
762
763 /*
764 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
765 * list and return a device name if we find a match.
766 */
767 static int
my_probe(device_t dev)768 my_probe(device_t dev)
769 {
770 struct my_type *t;
771
772 t = my_devs;
773 while (t->my_name != NULL) {
774 if ((pci_get_vendor(dev) == t->my_vid) &&
775 (pci_get_device(dev) == t->my_did)) {
776 device_set_desc(dev, t->my_name);
777 my_info_tmp = t;
778 return (BUS_PROBE_DEFAULT);
779 }
780 t++;
781 }
782 return (ENXIO);
783 }
784
785 /*
786 * Attach the interface. Allocate softc structures, do ifmedia setup and
787 * ethernet/BPF attach.
788 */
789 static int
my_attach(device_t dev)790 my_attach(device_t dev)
791 {
792 int i;
793 u_char eaddr[ETHER_ADDR_LEN];
794 u_int32_t iobase;
795 struct my_softc *sc;
796 if_t ifp;
797 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
798 unsigned int round;
799 caddr_t roundptr;
800 struct my_type *p;
801 u_int16_t phy_vid, phy_did, phy_sts = 0;
802 int rid, error = 0;
803
804 sc = device_get_softc(dev);
805 sc->my_dev = dev;
806 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
807 MTX_DEF);
808 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
809 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
810
811 /*
812 * Map control/status registers.
813 */
814 pci_enable_busmaster(dev);
815
816 if (my_info_tmp->my_did == MTD800ID) {
817 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
818 if (iobase & 0x300)
819 MY_USEIOSPACE = 0;
820 }
821
822 rid = MY_RID;
823 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
824
825 if (sc->my_res == NULL) {
826 device_printf(dev, "couldn't map ports/memory\n");
827 error = ENXIO;
828 goto destroy_mutex;
829 }
830 sc->my_btag = rman_get_bustag(sc->my_res);
831 sc->my_bhandle = rman_get_bushandle(sc->my_res);
832
833 rid = 0;
834 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
835 RF_SHAREABLE | RF_ACTIVE);
836
837 if (sc->my_irq == NULL) {
838 device_printf(dev, "couldn't map interrupt\n");
839 error = ENXIO;
840 goto release_io;
841 }
842
843 sc->my_info = my_info_tmp;
844
845 /* Reset the adapter. */
846 MY_LOCK(sc);
847 my_reset(sc);
848 MY_UNLOCK(sc);
849
850 /*
851 * Get station address
852 */
853 for (i = 0; i < ETHER_ADDR_LEN; ++i)
854 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
855
856 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
857 M_DEVBUF, M_NOWAIT);
858 if (sc->my_ldata_ptr == NULL) {
859 device_printf(dev, "no memory for list buffers!\n");
860 error = ENXIO;
861 goto release_irq;
862 }
863 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
864 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
865 roundptr = sc->my_ldata_ptr;
866 for (i = 0; i < 8; i++) {
867 if (round % 8) {
868 round++;
869 roundptr++;
870 } else
871 break;
872 }
873 sc->my_ldata = (struct my_list_data *) roundptr;
874 bzero(sc->my_ldata, sizeof(struct my_list_data));
875
876 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
877 if_setsoftc(ifp, sc);
878 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
879 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
880 if_setioctlfn(ifp, my_ioctl);
881 if_setstartfn(ifp, my_start);
882 if_setinitfn(ifp, my_init);
883 if_setbaudrate(ifp, 10000000);
884 if_setsendqlen(ifp, ifqmaxlen);
885 if_setsendqready(ifp);
886
887 if (sc->my_info->my_did == MTD803ID)
888 sc->my_pinfo = my_phys;
889 else {
890 if (bootverbose)
891 device_printf(dev, "probing for a PHY\n");
892 MY_LOCK(sc);
893 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
894 if (bootverbose)
895 device_printf(dev, "checking address: %d\n", i);
896 sc->my_phy_addr = i;
897 phy_sts = my_phy_readreg(sc, PHY_BMSR);
898 if ((phy_sts != 0) && (phy_sts != 0xffff))
899 break;
900 else
901 phy_sts = 0;
902 }
903 if (phy_sts) {
904 phy_vid = my_phy_readreg(sc, PHY_VENID);
905 phy_did = my_phy_readreg(sc, PHY_DEVID);
906 if (bootverbose) {
907 device_printf(dev, "found PHY at address %d, ",
908 sc->my_phy_addr);
909 printf("vendor id: %x device id: %x\n",
910 phy_vid, phy_did);
911 }
912 p = my_phys;
913 while (p->my_vid) {
914 if (phy_vid == p->my_vid) {
915 sc->my_pinfo = p;
916 break;
917 }
918 p++;
919 }
920 if (sc->my_pinfo == NULL)
921 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
922 if (bootverbose)
923 device_printf(dev, "PHY type: %s\n",
924 sc->my_pinfo->my_name);
925 } else {
926 MY_UNLOCK(sc);
927 device_printf(dev, "MII without any phy!\n");
928 error = ENXIO;
929 goto free_if;
930 }
931 MY_UNLOCK(sc);
932 }
933
934 /* Do ifmedia setup. */
935 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
936 MY_LOCK(sc);
937 my_getmode_mii(sc);
938 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
939 media = sc->ifmedia.ifm_media;
940 my_stop(sc);
941 MY_UNLOCK(sc);
942 ifmedia_set(&sc->ifmedia, media);
943
944 ether_ifattach(ifp, eaddr);
945
946 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
947 NULL, my_intr, sc, &sc->my_intrhand);
948
949 if (error) {
950 device_printf(dev, "couldn't set up irq\n");
951 goto detach_if;
952 }
953
954 return (0);
955
956 detach_if:
957 ether_ifdetach(ifp);
958 free_if:
959 if_free(ifp);
960 free(sc->my_ldata_ptr, M_DEVBUF);
961 release_irq:
962 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
963 release_io:
964 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
965 destroy_mutex:
966 mtx_destroy(&sc->my_mtx);
967 return (error);
968 }
969
970 static int
my_detach(device_t dev)971 my_detach(device_t dev)
972 {
973 struct my_softc *sc;
974 if_t ifp;
975
976 sc = device_get_softc(dev);
977 ifp = sc->my_ifp;
978 ether_ifdetach(ifp);
979 MY_LOCK(sc);
980 my_stop(sc);
981 MY_UNLOCK(sc);
982 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
983 callout_drain(&sc->my_watchdog);
984 callout_drain(&sc->my_autoneg_timer);
985
986 if_free(ifp);
987 free(sc->my_ldata_ptr, M_DEVBUF);
988
989 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
990 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
991 mtx_destroy(&sc->my_mtx);
992 return (0);
993 }
994
995 /*
996 * Initialize the transmit descriptors.
997 */
998 static int
my_list_tx_init(struct my_softc * sc)999 my_list_tx_init(struct my_softc * sc)
1000 {
1001 struct my_chain_data *cd;
1002 struct my_list_data *ld;
1003 int i;
1004
1005 MY_LOCK_ASSERT(sc);
1006 cd = &sc->my_cdata;
1007 ld = sc->my_ldata;
1008 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1009 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1010 if (i == (MY_TX_LIST_CNT - 1))
1011 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1012 else
1013 cd->my_tx_chain[i].my_nextdesc =
1014 &cd->my_tx_chain[i + 1];
1015 }
1016 cd->my_tx_free = &cd->my_tx_chain[0];
1017 cd->my_tx_tail = cd->my_tx_head = NULL;
1018 return (0);
1019 }
1020
1021 /*
1022 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1023 * arrange the descriptors in a closed ring, so that the last descriptor
1024 * points back to the first.
1025 */
1026 static int
my_list_rx_init(struct my_softc * sc)1027 my_list_rx_init(struct my_softc * sc)
1028 {
1029 struct my_chain_data *cd;
1030 struct my_list_data *ld;
1031 int i;
1032
1033 MY_LOCK_ASSERT(sc);
1034 cd = &sc->my_cdata;
1035 ld = sc->my_ldata;
1036 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1037 cd->my_rx_chain[i].my_ptr =
1038 (struct my_desc *) & ld->my_rx_list[i];
1039 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1040 MY_UNLOCK(sc);
1041 return (ENOBUFS);
1042 }
1043 if (i == (MY_RX_LIST_CNT - 1)) {
1044 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1045 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1046 } else {
1047 cd->my_rx_chain[i].my_nextdesc =
1048 &cd->my_rx_chain[i + 1];
1049 ld->my_rx_list[i].my_next =
1050 vtophys(&ld->my_rx_list[i + 1]);
1051 }
1052 }
1053 cd->my_rx_head = &cd->my_rx_chain[0];
1054 return (0);
1055 }
1056
1057 /*
1058 * Initialize an RX descriptor and attach an MBUF cluster.
1059 */
1060 static int
my_newbuf(struct my_softc * sc,struct my_chain_onefrag * c)1061 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1062 {
1063 struct mbuf *m_new = NULL;
1064
1065 MY_LOCK_ASSERT(sc);
1066 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1067 if (m_new == NULL) {
1068 device_printf(sc->my_dev,
1069 "no memory for rx list -- packet dropped!\n");
1070 return (ENOBUFS);
1071 }
1072 if (!(MCLGET(m_new, M_NOWAIT))) {
1073 device_printf(sc->my_dev,
1074 "no memory for rx list -- packet dropped!\n");
1075 m_freem(m_new);
1076 return (ENOBUFS);
1077 }
1078 c->my_mbuf = m_new;
1079 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1080 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1081 c->my_ptr->my_status = MY_OWNByNIC;
1082 return (0);
1083 }
1084
1085 /*
1086 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1087 * level protocols.
1088 */
1089 static void
my_rxeof(struct my_softc * sc)1090 my_rxeof(struct my_softc * sc)
1091 {
1092 struct ether_header *eh;
1093 struct mbuf *m;
1094 if_t ifp;
1095 struct my_chain_onefrag *cur_rx;
1096 int total_len = 0;
1097 u_int32_t rxstat;
1098
1099 MY_LOCK_ASSERT(sc);
1100 ifp = sc->my_ifp;
1101 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1102 & MY_OWNByNIC)) {
1103 cur_rx = sc->my_cdata.my_rx_head;
1104 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1105
1106 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1107 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1108 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1109 continue;
1110 }
1111 /* No errors; receive the packet. */
1112 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1113 total_len -= ETHER_CRC_LEN;
1114
1115 if (total_len < MINCLSIZE) {
1116 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1117 total_len, 0, ifp, NULL);
1118 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1119 if (m == NULL) {
1120 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1121 continue;
1122 }
1123 } else {
1124 m = cur_rx->my_mbuf;
1125 /*
1126 * Try to conjure up a new mbuf cluster. If that
1127 * fails, it means we have an out of memory condition
1128 * and should leave the buffer in place and continue.
1129 * This will result in a lost packet, but there's
1130 * little else we can do in this situation.
1131 */
1132 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1133 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1134 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1135 continue;
1136 }
1137 m->m_pkthdr.rcvif = ifp;
1138 m->m_pkthdr.len = m->m_len = total_len;
1139 }
1140 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1141 eh = mtod(m, struct ether_header *);
1142 #if NBPFILTER > 0
1143 /*
1144 * Handle BPF listeners. Let the BPF user see the packet, but
1145 * don't pass it up to the ether_input() layer unless it's a
1146 * broadcast packet, multicast packet, matches our ethernet
1147 * address or the interface is in promiscuous mode.
1148 */
1149 if (bpf_peers_present_if(ifp)) {
1150 bpf_mtap_if(ifp, m);
1151 if (if_getflags(ifp) & IFF_PROMISC &&
1152 (bcmp(eh->ether_dhost, if_getlladdr(sc->my_ifp),
1153 ETHER_ADDR_LEN) &&
1154 (eh->ether_dhost[0] & 1) == 0)) {
1155 m_freem(m);
1156 continue;
1157 }
1158 }
1159 #endif
1160 MY_UNLOCK(sc);
1161 if_input(ifp, m);
1162 MY_LOCK(sc);
1163 }
1164 return;
1165 }
1166
1167 /*
1168 * A frame was downloaded to the chip. It's safe for us to clean up the list
1169 * buffers.
1170 */
1171 static void
my_txeof(struct my_softc * sc)1172 my_txeof(struct my_softc * sc)
1173 {
1174 struct my_chain *cur_tx;
1175 if_t ifp;
1176
1177 MY_LOCK_ASSERT(sc);
1178 ifp = sc->my_ifp;
1179 /* Clear the timeout timer. */
1180 sc->my_timer = 0;
1181 if (sc->my_cdata.my_tx_head == NULL) {
1182 return;
1183 }
1184 /*
1185 * Go through our tx list and free mbufs for those frames that have
1186 * been transmitted.
1187 */
1188 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1189 u_int32_t txstat;
1190
1191 cur_tx = sc->my_cdata.my_tx_head;
1192 txstat = MY_TXSTATUS(cur_tx);
1193 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1194 break;
1195 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1196 if (txstat & MY_TXERR) {
1197 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1198 if (txstat & MY_EC) /* excessive collision */
1199 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1200 if (txstat & MY_LC) /* late collision */
1201 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1202 }
1203 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1204 (txstat & MY_NCRMASK) >> MY_NCRShift);
1205 }
1206 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1207 m_freem(cur_tx->my_mbuf);
1208 cur_tx->my_mbuf = NULL;
1209 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1210 sc->my_cdata.my_tx_head = NULL;
1211 sc->my_cdata.my_tx_tail = NULL;
1212 break;
1213 }
1214 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1215 }
1216 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1217 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask));
1218 }
1219 return;
1220 }
1221
1222 /*
1223 * TX 'end of channel' interrupt handler.
1224 */
1225 static void
my_txeoc(struct my_softc * sc)1226 my_txeoc(struct my_softc * sc)
1227 {
1228 if_t ifp;
1229
1230 MY_LOCK_ASSERT(sc);
1231 ifp = sc->my_ifp;
1232 sc->my_timer = 0;
1233 if (sc->my_cdata.my_tx_head == NULL) {
1234 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1235 sc->my_cdata.my_tx_tail = NULL;
1236 if (sc->my_want_auto)
1237 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1238 } else {
1239 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1240 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1241 sc->my_timer = 5;
1242 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1243 }
1244 }
1245 return;
1246 }
1247
1248 static void
my_intr(void * arg)1249 my_intr(void *arg)
1250 {
1251 struct my_softc *sc;
1252 if_t ifp;
1253 u_int32_t status;
1254
1255 sc = arg;
1256 MY_LOCK(sc);
1257 ifp = sc->my_ifp;
1258 if (!(if_getflags(ifp) & IFF_UP)) {
1259 MY_UNLOCK(sc);
1260 return;
1261 }
1262 /* Disable interrupts. */
1263 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1264
1265 for (;;) {
1266 status = CSR_READ_4(sc, MY_ISR);
1267 status &= MY_INTRS;
1268 if (status)
1269 CSR_WRITE_4(sc, MY_ISR, status);
1270 else
1271 break;
1272
1273 if (status & MY_RI) /* receive interrupt */
1274 my_rxeof(sc);
1275
1276 if ((status & MY_RBU) || (status & MY_RxErr)) {
1277 /* rx buffer unavailable or rx error */
1278 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1279 #ifdef foo
1280 my_stop(sc);
1281 my_reset(sc);
1282 my_init_locked(sc);
1283 #endif
1284 }
1285 if (status & MY_TI) /* tx interrupt */
1286 my_txeof(sc);
1287 if (status & MY_ETI) /* tx early interrupt */
1288 my_txeof(sc);
1289 if (status & MY_TBU) /* tx buffer unavailable */
1290 my_txeoc(sc);
1291
1292 #if 0 /* 90/1/18 delete */
1293 if (status & MY_FBE) {
1294 my_reset(sc);
1295 my_init_locked(sc);
1296 }
1297 #endif
1298 }
1299
1300 /* Re-enable interrupts. */
1301 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1302 if (!if_sendq_empty(ifp))
1303 my_start_locked(ifp);
1304 MY_UNLOCK(sc);
1305 return;
1306 }
1307
1308 /*
1309 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1310 * pointers to the fragment pointers.
1311 */
1312 static int
my_encap(struct my_softc * sc,struct my_chain * c,struct mbuf * m_head)1313 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1314 {
1315 struct my_desc *f = NULL;
1316 int total_len;
1317 struct mbuf *m, *m_new = NULL;
1318
1319 MY_LOCK_ASSERT(sc);
1320 /* calculate the total tx pkt length */
1321 total_len = 0;
1322 for (m = m_head; m != NULL; m = m->m_next)
1323 total_len += m->m_len;
1324 /*
1325 * Start packing the mbufs in this chain into the fragment pointers.
1326 * Stop when we run out of fragments or hit the end of the mbuf
1327 * chain.
1328 */
1329 m = m_head;
1330 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1331 if (m_new == NULL) {
1332 device_printf(sc->my_dev, "no memory for tx list");
1333 return (1);
1334 }
1335 if (m_head->m_pkthdr.len > MHLEN) {
1336 if (!(MCLGET(m_new, M_NOWAIT))) {
1337 m_freem(m_new);
1338 device_printf(sc->my_dev, "no memory for tx list");
1339 return (1);
1340 }
1341 }
1342 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1343 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1344 m_freem(m_head);
1345 m_head = m_new;
1346 f = &c->my_ptr->my_frag[0];
1347 f->my_status = 0;
1348 f->my_data = vtophys(mtod(m_new, caddr_t));
1349 total_len = m_new->m_len;
1350 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1351 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1352 f->my_ctl |= total_len; /* buffer size */
1353 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1354 if (sc->my_info->my_did == MTD891ID)
1355 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1356 c->my_mbuf = m_head;
1357 c->my_lastdesc = 0;
1358 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1359 return (0);
1360 }
1361
1362 /*
1363 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1364 * to the mbuf data regions directly in the transmit lists. We also save a
1365 * copy of the pointers since the transmit list fragment pointers are
1366 * physical addresses.
1367 */
1368 static void
my_start(if_t ifp)1369 my_start(if_t ifp)
1370 {
1371 struct my_softc *sc;
1372
1373 sc = if_getsoftc(ifp);
1374 MY_LOCK(sc);
1375 my_start_locked(ifp);
1376 MY_UNLOCK(sc);
1377 }
1378
1379 static void
my_start_locked(if_t ifp)1380 my_start_locked(if_t ifp)
1381 {
1382 struct my_softc *sc;
1383 struct mbuf *m_head = NULL;
1384 struct my_chain *cur_tx = NULL, *start_tx;
1385
1386 sc = if_getsoftc(ifp);
1387 MY_LOCK_ASSERT(sc);
1388 if (sc->my_autoneg) {
1389 sc->my_tx_pend = 1;
1390 return;
1391 }
1392 /*
1393 * Check for an available queue slot. If there are none, punt.
1394 */
1395 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1396 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1397 return;
1398 }
1399 start_tx = sc->my_cdata.my_tx_free;
1400 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1401 m_head = if_dequeue(ifp);
1402 if (m_head == NULL)
1403 break;
1404
1405 /* Pick a descriptor off the free list. */
1406 cur_tx = sc->my_cdata.my_tx_free;
1407 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1408
1409 /* Pack the data into the descriptor. */
1410 my_encap(sc, cur_tx, m_head);
1411
1412 if (cur_tx != start_tx)
1413 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1414 #if NBPFILTER > 0
1415 /*
1416 * If there's a BPF listener, bounce a copy of this frame to
1417 * him.
1418 */
1419 BPF_MTAP(ifp, cur_tx->my_mbuf);
1420 #endif
1421 }
1422 /*
1423 * If there are no packets queued, bail.
1424 */
1425 if (cur_tx == NULL) {
1426 return;
1427 }
1428 /*
1429 * Place the request for the upload interrupt in the last descriptor
1430 * in the chain. This way, if we're chaining several packets at once,
1431 * we'll only get an interrupt once for the whole chain rather than
1432 * once for each packet.
1433 */
1434 MY_TXCTL(cur_tx) |= MY_TXIC;
1435 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1436 sc->my_cdata.my_tx_tail = cur_tx;
1437 if (sc->my_cdata.my_tx_head == NULL)
1438 sc->my_cdata.my_tx_head = start_tx;
1439 MY_TXOWN(start_tx) = MY_OWNByNIC;
1440 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1441
1442 /*
1443 * Set a timeout in case the chip goes out to lunch.
1444 */
1445 sc->my_timer = 5;
1446 return;
1447 }
1448
1449 static void
my_init(void * xsc)1450 my_init(void *xsc)
1451 {
1452 struct my_softc *sc = xsc;
1453
1454 MY_LOCK(sc);
1455 my_init_locked(sc);
1456 MY_UNLOCK(sc);
1457 }
1458
1459 static void
my_init_locked(struct my_softc * sc)1460 my_init_locked(struct my_softc *sc)
1461 {
1462 if_t ifp = sc->my_ifp;
1463 u_int16_t phy_bmcr = 0;
1464
1465 MY_LOCK_ASSERT(sc);
1466 if (sc->my_autoneg) {
1467 return;
1468 }
1469 if (sc->my_pinfo != NULL)
1470 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1471 /*
1472 * Cancel pending I/O and free all RX/TX buffers.
1473 */
1474 my_stop(sc);
1475 my_reset(sc);
1476
1477 /*
1478 * Set cache alignment and burst length.
1479 */
1480 #if 0 /* 89/9/1 modify, */
1481 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1482 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1483 #endif
1484 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1485 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1486 /*
1487 * 89/12/29 add, for mtd891,
1488 */
1489 if (sc->my_info->my_did == MTD891ID) {
1490 MY_SETBIT(sc, MY_BCR, MY_PROG);
1491 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1492 }
1493 my_setcfg(sc, phy_bmcr);
1494 /* Init circular RX list. */
1495 if (my_list_rx_init(sc) == ENOBUFS) {
1496 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1497 my_stop(sc);
1498 return;
1499 }
1500 /* Init TX descriptors. */
1501 my_list_tx_init(sc);
1502
1503 /* If we want promiscuous mode, set the allframes bit. */
1504 if (if_getflags(ifp) & IFF_PROMISC)
1505 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1506 else
1507 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1508
1509 /*
1510 * Set capture broadcast bit to capture broadcast frames.
1511 */
1512 if (if_getflags(ifp) & IFF_BROADCAST)
1513 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1514 else
1515 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1516
1517 /*
1518 * Program the multicast filter, if necessary.
1519 */
1520 my_setmulti(sc);
1521
1522 /*
1523 * Load the address of the RX list.
1524 */
1525 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1526 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1527
1528 /*
1529 * Enable interrupts.
1530 */
1531 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1532 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1533
1534 /* Enable receiver and transmitter. */
1535 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1536 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1537 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1538 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1539
1540 /* Restore state of BMCR */
1541 if (sc->my_pinfo != NULL)
1542 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1543 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1544 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1545
1546 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1547 return;
1548 }
1549
1550 /*
1551 * Set media options.
1552 */
1553
1554 static int
my_ifmedia_upd(if_t ifp)1555 my_ifmedia_upd(if_t ifp)
1556 {
1557 struct my_softc *sc;
1558 struct ifmedia *ifm;
1559
1560 sc = if_getsoftc(ifp);
1561 MY_LOCK(sc);
1562 ifm = &sc->ifmedia;
1563 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1564 MY_UNLOCK(sc);
1565 return (EINVAL);
1566 }
1567 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1568 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1569 else
1570 my_setmode_mii(sc, ifm->ifm_media);
1571 MY_UNLOCK(sc);
1572 return (0);
1573 }
1574
1575 /*
1576 * Report current media status.
1577 */
1578
1579 static void
my_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1580 my_ifmedia_sts(if_t ifp, struct ifmediareq * ifmr)
1581 {
1582 struct my_softc *sc;
1583 u_int16_t advert = 0, ability = 0;
1584
1585 sc = if_getsoftc(ifp);
1586 MY_LOCK(sc);
1587 ifmr->ifm_active = IFM_ETHER;
1588 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1589 #if 0 /* this version did not support 1000M, */
1590 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1591 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1592 #endif
1593 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1594 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1595 else
1596 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1597 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1598 ifmr->ifm_active |= IFM_FDX;
1599 else
1600 ifmr->ifm_active |= IFM_HDX;
1601
1602 MY_UNLOCK(sc);
1603 return;
1604 }
1605 ability = my_phy_readreg(sc, PHY_LPAR);
1606 advert = my_phy_readreg(sc, PHY_ANAR);
1607
1608 #if 0 /* this version did not support 1000M, */
1609 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1610 ability2 = my_phy_readreg(sc, PHY_1000SR);
1611 if (ability2 & PHY_1000SR_1000BTXFULL) {
1612 advert = 0;
1613 ability = 0;
1614 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1615 } else if (ability & PHY_1000SR_1000BTXHALF) {
1616 advert = 0;
1617 ability = 0;
1618 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1619 }
1620 }
1621 #endif
1622 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1623 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1624 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1625 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1626 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1627 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1628 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1629 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1630 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1631 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1632 MY_UNLOCK(sc);
1633 return;
1634 }
1635
1636 static int
my_ioctl(if_t ifp,u_long command,caddr_t data)1637 my_ioctl(if_t ifp, u_long command, caddr_t data)
1638 {
1639 struct my_softc *sc = if_getsoftc(ifp);
1640 struct ifreq *ifr = (struct ifreq *) data;
1641 int error;
1642
1643 switch (command) {
1644 case SIOCSIFFLAGS:
1645 MY_LOCK(sc);
1646 if (if_getflags(ifp) & IFF_UP)
1647 my_init_locked(sc);
1648 else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1649 my_stop(sc);
1650 MY_UNLOCK(sc);
1651 error = 0;
1652 break;
1653 case SIOCADDMULTI:
1654 case SIOCDELMULTI:
1655 MY_LOCK(sc);
1656 my_setmulti(sc);
1657 MY_UNLOCK(sc);
1658 error = 0;
1659 break;
1660 case SIOCGIFMEDIA:
1661 case SIOCSIFMEDIA:
1662 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1663 break;
1664 default:
1665 error = ether_ioctl(ifp, command, data);
1666 break;
1667 }
1668 return (error);
1669 }
1670
1671 static void
my_watchdog(void * arg)1672 my_watchdog(void *arg)
1673 {
1674 struct my_softc *sc;
1675 if_t ifp;
1676
1677 sc = arg;
1678 MY_LOCK_ASSERT(sc);
1679 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1680 if (sc->my_timer == 0 || --sc->my_timer > 0)
1681 return;
1682
1683 ifp = sc->my_ifp;
1684 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1685 if_printf(ifp, "watchdog timeout\n");
1686 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1687 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1688 my_stop(sc);
1689 my_reset(sc);
1690 my_init_locked(sc);
1691 if (!if_sendq_empty(ifp))
1692 my_start_locked(ifp);
1693 }
1694
1695 /*
1696 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1697 */
1698 static void
my_stop(struct my_softc * sc)1699 my_stop(struct my_softc * sc)
1700 {
1701 int i;
1702 if_t ifp;
1703
1704 MY_LOCK_ASSERT(sc);
1705 ifp = sc->my_ifp;
1706
1707 callout_stop(&sc->my_autoneg_timer);
1708 callout_stop(&sc->my_watchdog);
1709
1710 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1711 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1712 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1713 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1714
1715 /*
1716 * Free data in the RX lists.
1717 */
1718 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1719 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1720 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1721 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1722 }
1723 }
1724 bzero((char *)&sc->my_ldata->my_rx_list,
1725 sizeof(sc->my_ldata->my_rx_list));
1726 /*
1727 * Free the TX list buffers.
1728 */
1729 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1730 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1731 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1732 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1733 }
1734 }
1735 bzero((char *)&sc->my_ldata->my_tx_list,
1736 sizeof(sc->my_ldata->my_tx_list));
1737 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1738 return;
1739 }
1740
1741 /*
1742 * Stop all chip I/O so that the kernel's probe routines don't get confused
1743 * by errant DMAs when rebooting.
1744 */
1745 static int
my_shutdown(device_t dev)1746 my_shutdown(device_t dev)
1747 {
1748 struct my_softc *sc;
1749
1750 sc = device_get_softc(dev);
1751 MY_LOCK(sc);
1752 my_stop(sc);
1753 MY_UNLOCK(sc);
1754 return 0;
1755 }
1756